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Merge gblack@m5.eecs.umich.edu:/bk/multiarch

Browse source 
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : c7caf571575fb0e7136770864371300d3f11787e
This commit is contained in:
Gabe Black 2006-02-08 01:04:32 -05:00
commit 29bc6c086a
14 changed files with 391 additions and 145 deletions
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8
arch/mips/isa_desc/bitfields.h → arch/mips/isa/bitfields.isa
View file

@ -9,6 +9,7 @@ def bitfield OPCODE_LO <28:26>;
def bitfield FUNCTION_HI < 5: 3>;
def bitfield FUNCTION_LO < 2: 0>;
// Integer operate format
def bitfield RT <20:16>;
def bitfield RT_HI <20:19>;
def bitfield RT_LO <18:16>;
@ -19,8 +20,10 @@ def bitfield RS_LO <23:21>;
def bitfield RD <15:11>;
def bitfield INTIMM <15: 0>; // integer immediate (literal)
// Floating-point operate format
def bitfield FMT <25:21>;
def bitfield FMT <25:21>;
def bitfield FT <20:16>;
def bitfield FS <15:11>;
def bitfield FD <10:6>;
@ -34,9 +37,6 @@ def bitfield SA <10: 6>;
// Interrupts
def bitfield SC < 5: 5>;
// Integer operate format(s>;
def bitfield INTIMM <15: 0>; // integer immediate (literal)
// Branch format
def bitfield OFFSET <15: 0>; // displacement

318
arch/mips/isa_desc/decoder.h → arch/mips/isa/decoder.isa
View file

@ -18,31 +18,37 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x0: decode FUNCTION_LO {
0x1: decode MOVCI {
format Move {
0: movc({{ }});
1: movt({{ }});
0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}});
1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}});
}
}
format ShiftRotate {
format BasicOp {
//Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
//are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
0x0: sll({{ }});
0x0: sll({{ Rd = Rt.uw << SA; }});
0x2: decode SRL {
0: srl({{ }});
1: rotr({{ }});
0: srl({{ Rd = Rt.uw >> SA; }});
//Hardcoded assuming 32-bit ISA, probably need parameter here
1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
}
0x3: sar({{ }});
0x3: sra({{ Rd = Rt.sw >> SA; }});
0x4: sllv({{ }});
0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
0x6: decode SRLV {
0: srlv({{ }});
1: rotrv({{ }});
0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
//Hardcoded assuming 32-bit ISA, probably need parameter here
1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
}
0x7: srav({{ }});
0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
}
}
@ -51,58 +57,75 @@ decode OPCODE_HI default FailUnimpl::unknown() {
//Table A-3 Note: "Specific encodings of the hint field are used
//to distinguish JR from JR.HB and JALR from JALR.HB"
format Jump {
0x0: jr({{ }});
0x1: jalr({{ }});
0x0: jr(IsReturn);
0x1: jalr(IsCall,IsReturn);
}
format Move {
0x2: movz({{ }});
0x3: movn({{ }});
0x2: movz({{ if (Rt == 0) Rd = Rs; }});
0x3: movn({{ if (Rt != 0) Rd = Rs; }});
}
0x4: Syscall::syscall({{ }});
0x5: Break::break({{ }});
0x7: Synchronize::synch({{ }});
format Trap {
0x4: syscall({{ xc->syscall()}},IsNonSpeculative);
0x5: break({{ }});
0x7: sync({{ }});
}
}
0x2: decode FUNCTION_LO {
format MultDiv {
0x0: mfhi({{ }});
0x1: mthi({{ }});
0x2: mflo({{ }});
0x3: mtlo({{ }});
format BasicOp {
0x0: mfhi({{ Rd = xc->miscRegs.Hi; }});
0x1: mthi({{ xc->miscRegs.Hi = Rs; }});
0x2: mflo({{ Rd = xc->miscRegs.Lo; }});
0x3: mtlo({{ xc->miscRegs.Lo = Rs; }});
}
};
0x3: decode FUNCTION_LO {
format MultDiv {
0x0: mult({{ }});
0x1: multu({{ }});
0x2: div({{ }});
0x3: divu({{ }});
format IntOp {
0x0: mult({{
INT64 temp1 = Rs.sw * Rt.sw;
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
}});
0x1: multu({{
INT64 temp1 = Rs.uw * Rt.uw;
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
Rd.sw = Rs.uw * Rt.uw;
}});
0x2: div({{
xc->miscRegs.Hi = Rs.sw % Rt.sw;
xc->miscRegs.Lo = Rs.sw / Rt.sw;
}});
0x3: divu({{
xc->miscRegs.Hi = Rs.uw % Rt.uw;
xc->miscRegs.Lo = Rs.uw / Rt.uw;
}});
}
};
0x4: decode FUNCTION_LO {
format Arithmetic {
0x0: add({{ }});
0x1: addu({{ }});
0x2: sub({{ }});
0x3: subu({{ }});
}
format Logical {
0x0: and({{ }});
0x1: or({{ }});
0x2: xor({{ }});
0x3: nor({{ }});
format IntOp {
0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}});
0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}});
0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}});
0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}});
0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}});
0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}});
0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}});
0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}});
}
}
0x5: decode FUNCTION_LO {
format SetInstructions{
0x2: slt({{ }});
0x3: sltu({{ }});
format IntOp{
0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
}
};
@ -121,12 +144,12 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode REGIMM_HI {
0x0: decode REGIMM_LO {
format Branch {
0x0: bltz({{ }});
0x1: bgez({{ }});
0x0: bltz({{ cond = (Rs.sq < 0); }});
0x1: bgez({{ cond = (Rs.sq >= 0); }});
//MIPS obsolete instructions
0x2: bltzl({{ }});
0x3: bgezl({{ }});
0x2: bltzl({{ cond = (Rs.sq < 0); }});
0x3: bgezl({{ cond = (Rs.sq >= 0); }});
}
}
@ -143,43 +166,45 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x2: decode REGIMM_LO {
format Branch {
0x0: bltzal({{ }});
0x1: bgezal({{ }});
0x0: bltzal({{ cond = (Rs.sq < 0); }});
0x1: bgezal({{ cond = (Rs.sq >= 0); }});
//MIPS obsolete instructions
0x2: bltzall({{ }});
0x3: bgezall({{ }});
0x2: bltzall({{ cond = (Rs.sq < 0); }});
0x3: bgezall({{ cond = (Rs.sq >= 0); }});
}
}
0x3: decode REGIMM_LO {
0x7: synci({{ }});
format Trap {
0x7: synci({{ }});
}
}
}
format Jump {
0x2: j({{ }});
0x3: jal({{ }});
0x2: j();
0x3: jal(IsCall);
}
format Branch {
0x4: beq({{ }});
0x5: bne({{ }});
0x6: blez({{ }});
0x7: bgtz({{ }});
0x4: beq({{ cond = (Rs.sq == 0); }});
0x5: bne({{ cond = (Rs.sq != 0); }});
0x6: blez({{ cond = (Rs.sq <= 0); }});
0x7: bgtz({{ cond = (Rs.sq > 0); }});
}
};
0x1: decode OPCODE_LO default FailUnimpl::reserved(){
format IntImmediate {
0x0: addi({{ }});
0x1: addiu({{ }});
0x2: slti({{ }});
0x3: sltiu({{ }});
0x4: andi({{ }});
0x5: ori({{ }});
0x6: xori({{ }});
0x7: lui({{ }});
format IntOp {
0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }});
0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}});
0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }});
0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }});
0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
0x7: lui({{ Rt = INTIMM << 16}});
};
};
@ -193,8 +218,10 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0xA: rdpgpr({{ }});
0xB: decode SC {
0x0: di({{ }});
0x1: ei({{ }});
format BasicOp {
0x0: di({{ }});
0x1: ei({{ }});
}
}
0xE: wrpgpr({{ }});
@ -202,13 +229,18 @@ decode OPCODE_HI default FailUnimpl::unknown() {
//Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
0x1: decode FUNCTION {
0x01: tlbr({{ }});
0x02: tlbwi({{ }});
0x06: tlbwr({{ }});
0x08: tlbp({{ }});
0x18: eret({{ }});
0x1F: deret({{ }});
0x20: wait({{ }});
format Trap {
0x01: tlbr({{ }});
0x02: tlbwi({{ }});
0x06: tlbwr({{ }});
0x08: tlbp({{ }});
}
format BasicOp {
0x18: eret({{ }});
0x1F: deret({{ }});
0x20: wait({{ }});
}
}
}
@ -227,13 +259,17 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode ND {
0x0: decode TF {
0x0: bc1f({{ }});
0x1: bc1t({{ }});
format Branch {
0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
}
}
0x1: decode TF {
0x0: bc1fl({{ }});
0x1: bc1tl({{ }});
format Branch {
0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
}
}
}
}
@ -276,8 +312,10 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: movt_fmt({{ }});
}
0x2: movz({{ }});
0x3: movn({{ }});
format Move {
0x2: movz({{ if (Rt == 0) Rd = Rs; }});
0x3: movn({{ if (Rt != 0) Rd = Rs; }});
}
format mode64 {
0x2: recip({{ }});
@ -331,8 +369,10 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: movt_fmt({{ }});
}
0x2: movz({{ }});
0x3: movn({{ }});
format Move {
0x2: movz({{ if (Rt == 0) Rd = Rs; }});
0x3: movn({{ if (Rt != 0) Rd = Rs; }});
}
format mode64 {
0x5: recip({{ }});
@ -384,8 +424,6 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: movt_fmt({{ }});
}
0x2: movz({{ }});
0x3: movn({{ }});
}
0x4: decode RS_LO {
@ -416,13 +454,17 @@ decode OPCODE_HI default FailUnimpl::unknown() {
0x1: decode ND {
0x0: decode TF {
0x0: bc2f({{ }});
0x1: bc2t({{ }});
format Branch {
0x0: bc2f({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2);
0x1: bc2t({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
}
}
0x1: decode TF {
0x0: bc2fl({{ }});
0x1: bc2tl({{ }});
format Branch {
0x0: bc2fl({{ cond = (xc->miscRegs.cop2cc == 0); }}, COP2}});
0x1: bc2tl({{ cond = (xc->miscRegs.cop2cc == 1); }}, COP2}});
}
}
}
}
@ -473,23 +515,49 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
//MIPS obsolete instructions
0x4: beql({{ }});
0x5: bnel({{ }});
0x6: blezl({{ }});
0x7: bgtzl({{ }});
0x4: beql({{ cond = (Rs.sq == 0); }});
0x5: bnel({{ cond = (Rs.sq != 0); }});
0x6: blezl({{ cond = (Rs.sq <= 0); }});
0x7: bgtzl({{ cond = (Rs.sq > 0); }});
};
0x3: decode OPCODE_LO default FailUnimpl::reserved(){
0x3: decode OPCODE_LO default FailUnimpl::reserved() {
//Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
0x4: decode FUNCTION_HI {
0x0: decode FUNCTION_LO {
0x0: madd({{ }});
0x1: maddu({{ }});
0x2: mult({{ }});
0x4: msub({{ }});
0x5: msubu({{ }});
format IntOp {
0x0: madd({{
INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
temp1 = temp1 + (Rs.sw * Rt.sw);
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
}});
0x1: maddu({{
INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 + (Rs.uw * Rt.uw);
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
}});
0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }});
0x4: msub({{
INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32;
temp1 = temp1 - (Rs.sw * Rt.sw);
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
}});
0x5: msubu({{
INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32;
temp1 = temp1 - (Rs.uw * Rt.uw);
xc->miscRegs.Hi->temp1<63:32>;
xc->miscRegs.Lo->temp1<31:0>
}});
}
}
0x4: decode FUNCTION_LO {
@ -523,30 +591,30 @@ decode OPCODE_HI default FailUnimpl::unknown() {
}
};
0x4: decode OPCODE_LO default FailUnimpl::reserved(){
format LoadMemory{
0x0: lb({{ }});
0x1: lh({{ }});
0x2: lwl({{ }});
0x3: lw({{ }});
0x4: lbu({{ }});
0x5: lhu({{ }});
0x6: lhu({{ }});
0x4: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory {
0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }});
0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }});
0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }}, WordAlign);
0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }});
0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }});
0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }});
0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }}, WordAlign);
};
0x7: FailUnimpl::reserved({{ }});
};
0x5: decode OPCODE_LO default FailUnimpl::reserved(){
format StoreMemory{
0x0: sb({{ }});
0x1: sh({{ }});
0x2: swl({{ }});
0x3: sw({{ }});
0x6: swr({{ }});
0x5: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory {
0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }});
0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }});
0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});
0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }},WordAlign);
};
format FailUnimpl{
format FailUnimpl {
0x4: reserved({{ }});
0x5: reserved({{ }});
0x7: cache({{ }});
@ -554,19 +622,19 @@ decode OPCODE_HI default FailUnimpl::unknown() {
};
0x6: decode OPCODE_LO default FailUnimpl::reserved(){
format LoadMemory{
0x6: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory {
0x0: ll({{ }});
0x1: lwc1({{ }});
0x5: ldc1({{ }});
0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }});
0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }});
};
};
0x7: decode OPCODE_LO default FailUnimpl::reserved(){
format StoreMemory{
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
format Memory {
0x0: sc({{ }});
0x1: swc1({{ }});
0x5: sdc1({{ }});
0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }});
0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }});
};
}

0
arch/mips/isa_desc/formats.h → arch/mips/isa/formats.isa
View file

0
arch/mips/isa_desc/formats/basic.format → arch/mips/isa/formats/basic.format
View file

0
arch/mips/isa_desc/formats/branch.format → arch/mips/isa/formats/branch.format
View file

14
arch/mips/isa_desc/formats/integerop.format → arch/mips/isa/formats/fp.format
View file

@ -1,18 +1,18 @@
////////////////////////////////////////////////////////////////////
//
// Integer operate instructions
// Floating Point operate instructions
//
output header {{
/**
* Base class for integer operations.
*/
class IntegerOp : public MipsStaticInst
class FPOp : public MipsStaticInst
{
protected:
/// Constructor
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
{
}
@ -21,13 +21,13 @@ output header {{
}};
output decoder {{
std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Disassembly of integer instruction\n";
}
}};
def template IntegerExecute {{
def template FPExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
//These are set to constants when the execute method
@ -70,7 +70,7 @@ def template IntegerExecute {{
}};
// Primary format for integer operate instructions:
def format IntegerOp(code, *opt_flags) {{
def format FPOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
@ -90,7 +90,7 @@ def format IntegerOp(code, *opt_flags) {{
}};
// Primary format for integer operate instructions:
def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)

70
arch/mips/isa/formats/int.format Normal file
View file

@ -0,0 +1,70 @@
////////////////////////////////////////////////////////////////////
//
// Integer operate instructions
//
output header {{
/**
* Base class for integer operations.
*/
class IntOp : public MipsStaticInst
{
protected:
/// Constructor
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class IntImmOp : public MipsStaticInst
{
protected:
uint16_t imm;
/// Constructor
IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Disassembly of integer instruction\n";
}
std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Disassembly of integer immediate instruction\n";
}
}};
// Primary format for integer operate instructions:
def format IntOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
//Figure out if we are creating a IntImmOp or a IntOp
strlen = len(name)
if ( name[strlen-1] = 'i' or ( name[strlen-2:] = 'iu'))
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
else:
iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = OperateNopCheckDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

0
arch/mips/isa_desc/formats/mem.format → arch/mips/isa/formats/mem.format
View file

0
arch/mips/isa_desc/formats/noop.format → arch/mips/isa/formats/noop.format
View file

53
arch/mips/isa/formats/tlbop.format Normal file
View file

@ -0,0 +1,53 @@
////////////////////////////////////////////////////////////////////
//
// TlbOp instructions
//
output header {{
/**
* Base class for integer operations.
*/
class TlbOp : public MipsStaticInst
{
protected:
/// Constructor
TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Disassembly of integer instruction\n";
}
}};
def template TlbOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
//Call into the trap handler with the appropriate fault
return No_Fault;
}
//Write the resulting state to the execution context
%(op_wb)s;
return No_Fault;
}
}};
// Primary format for integer operate instructions:
def format TlbOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = TlbOpExecute.subst(iop)
}};

0
arch/mips/isa_desc/formats/trap.format → arch/mips/isa/formats/trap.format
View file

0
arch/mips/isa_desc/includes.h → arch/mips/isa/includes.isa
View file

52
arch/mips/isa/mips.isa Normal file
View file

@ -0,0 +1,52 @@
// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
##include "m5/arch/sparc/isa_desc/includes.h"
////////////////////////////////////////////////////////////////////
//
// Namespace statement. Everything below this line will be in the
// MipsISAInst namespace.
//
namespace MipsISA;
//Include the bitfield definitions
##include "m5/arch/mips/isa_desc/bitfields.h"
//Include the operand_types and operand definitions
##include "m5/arch/mips/isa_desc/operands.h"
//Include the base class for mips instructions, and some support code
##include "m5/arch/mips/isa_desc/base.h"
//Include the definitions for the instruction formats
##include "m5/arch/mips/isa_desc/formats.h"
//Include the decoder definition
##include "m5/arch/mips/isa_desc/decoder.h"

21
arch/mips/isa_desc/operands.h → arch/mips/isa/operands.isa
View file

@ -13,17 +13,20 @@ def operand_types {{
}};
def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1),
'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2),
'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3),
#'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
#'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
#'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
'Rd': IntRegOperandTraits('uw', 'RD', 'IsInteger', 1),
'Rs': IntRegOperandTraits('uw', 'RS', 'IsInteger', 2),
'Rt': IntRegOperandTraits('uw', 'RT', 'IsInteger', 3),
'IntImm': IntRegOperandTraits('uw', 'INTIMM', 'IsInteger', 3),
'Sa': IntRegOperandTraits('uw', 'SA', 'IsInteger', 4),
'Fd': FloatRegOperandTraits('sf', 'FD', 'IsFloating', 1),
'Fs': FloatRegOperandTraits('sf', 'FS', 'IsFloating', 2),
'Ft': FloatRegOperandTraits('sf', 'FT', 'IsFloating', 3),
'Mem': MemOperandTraits('udw', None,
('IsMemRef', 'IsLoad', 'IsStore'), 4)
#'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
#'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),