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Checkin (Merge?) files ... Added a few new format files

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arch/mips/isa/formats/fpop.format:
    Floating Point Formats
arch/mips/isa/formats/tlb.format:
    TLB Ops Format
arch/mips/isa/mips.isa:
    Name change to mips.isa

--HG--
rename : arch/mips/isa_desc/bitfields.h => arch/mips/isa/bitfields.h
rename : arch/mips/isa_desc/decoder.h => arch/mips/isa/decoder.h
rename : arch/mips/isa_desc/formats.h => arch/mips/isa/formats.h
rename : arch/mips/isa_desc/formats/basic.format => arch/mips/isa/formats/basic.format
rename : arch/mips/isa_desc/formats/branch.format => arch/mips/isa/formats/branch.format
rename : arch/mips/isa_desc/formats/integerop.format => arch/mips/isa/formats/integerop.format
rename : arch/mips/isa_desc/formats/mem.format => arch/mips/isa/formats/mem.format
rename : arch/mips/isa_desc/formats/noop.format => arch/mips/isa/formats/noop.format
rename : arch/mips/isa_desc/formats/trap.format => arch/mips/isa/formats/trap.format
rename : arch/mips/isa_desc/includes.h => arch/mips/isa/includes.h
rename : arch/mips/isa_desc/operands.h => arch/mips/isa/operands.h
extra : convert_revision : 069a24da405b613f688e693fd038ac7a30a4faed
This commit is contained in:
Korey Sewell 2006-02-03 03:38:27 -05:00
parent 3d2773195c
commit f7a75d872b
14 changed files with 215 additions and 0 deletions
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arch/mips/isa_desc/bitfields.h → arch/mips/isa/bitfields.h
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arch/mips/isa_desc/decoder.h → arch/mips/isa/decoder.h
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arch/mips/isa_desc/formats.h → arch/mips/isa/formats.h
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arch/mips/isa_desc/formats/basic.format → arch/mips/isa/formats/basic.format
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arch/mips/isa_desc/formats/branch.format → arch/mips/isa/formats/branch.format
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arch/mips/isa/formats/fpop.format Normal file
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////////////////////////////////////////////////////////////////////
//
// Floating Point operate instructions
//
output header {{
/**
* Base class for integer operations.
*/
class FPOp : public MipsStaticInst
{
protected:
/// Constructor
FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Disassembly of integer instruction\n";
}
}};
def template IntegerExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
//These are set to constants when the execute method
//is generated
bool useCc = ;
bool checkPriv = ;
//Attempt to execute the instruction
try
{
checkPriv;
%(op_decl)s;
%(op_rd)s;
%(code)s;
}
//If we have an exception for some reason,
//deal with it
catch(MipsException except)
{
//Deal with exception
return No_Fault;
}
//Write the resulting state to the execution context
%(op_wb)s;
if(useCc)
{
xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
}
return No_Fault;
}
}};
// Primary format for integer operate instructions:
def format FPOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
code.replace('checkPriv', '')
if checkPriv:
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
else:
code.replace('checkPriv;', '')
for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
('xvValue', '0'), ('xcValue', '0')):
code.replace(marker, value)
iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = IntegerExecute.subst(iop)
}};
// Primary format for integer operate instructions:
def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
checkPriv = (code.find('checkPriv') != -1)
code.replace('checkPriv', '')
if checkPriv:
code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
else:
code.replace('checkPriv;', '')
for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
('xvValue', xvValue), ('xcValue', xcValue)):
code.replace(marker, value)
iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = IntegerExecute.subst(iop)
}};

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arch/mips/isa_desc/formats/integerop.format → arch/mips/isa/formats/integerop.format
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arch/mips/isa_desc/formats/mem.format → arch/mips/isa/formats/mem.format
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arch/mips/isa_desc/formats/noop.format → arch/mips/isa/formats/noop.format
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arch/mips/isa/formats/tlb.format Normal file
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////////////////////////////////////////////////////////////////////
//
// TlbOp instructions
//
output header {{
/**
* Base class for integer operations.
*/
class TlbOp : public MipsStaticInst
{
protected:
/// Constructor
TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return "Disassembly of integer instruction\n";
}
}};
def template TlbOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
//Call into the trap handler with the appropriate fault
return No_Fault;
}
//Write the resulting state to the execution context
%(op_wb)s;
return No_Fault;
}
}};
// Primary format for integer operate instructions:
def format TlbOp(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
exec_output = TlbOpExecute.subst(iop)
}};

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arch/mips/isa_desc/formats/trap.format → arch/mips/isa/formats/trap.format
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arch/mips/isa_desc/includes.h → arch/mips/isa/includes.h
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arch/mips/isa/mips.isa Normal file
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// -*- mode:c++ -*-
// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
##include "m5/arch/sparc/isa_desc/includes.h"
////////////////////////////////////////////////////////////////////
//
// Namespace statement. Everything below this line will be in the
// MipsISAInst namespace.
//
namespace MipsISA;
//Include the bitfield definitions
##include "m5/arch/mips/isa_desc/bitfields.h"
//Include the operand_types and operand definitions
##include "m5/arch/mips/isa_desc/operands.h"
//Include the base class for mips instructions, and some support code
##include "m5/arch/mips/isa_desc/base.h"
//Include the definitions for the instruction formats
##include "m5/arch/mips/isa_desc/formats.h"
//Include the decoder definition
##include "m5/arch/mips/isa_desc/decoder.h"

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arch/mips/isa_desc/operands.h → arch/mips/isa/operands.h
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