Ali Saidi 6c954de33e added m5 debug and m5 switch cpu instruction (doesn't work yet) and ... a p4 memory/cpu config arch/alpha/alpha_memory.cc: Added code to fault on an unaligned access arch/alpha/isa_desc: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: Added m5debug break and m5switchcpu (the latter doesn't work) --HG-- extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916		2004-08-02 17:10:02 -04:00
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alpha	added m5 debug and m5 switch cpu instruction (doesn't work yet) and	2004-08-02 17:10:02 -04:00
isa_parser.py	Renamed OpClass enum members: they all end in 'Op' now.	2004-05-31 16:19:31 -07:00