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Made Addr a global type

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--HG--
extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
This commit is contained in:
Gabe Black 2006-02-21 03:38:21 -05:00
parent 74d7cd1cea
commit 3f7979c99d
50 changed files with 58 additions and 143 deletions
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2
arch/alpha/alpha_memory.hh
View file

@ -42,7 +42,6 @@ class ExecContext;
class AlphaTLB : public SimObject
{
protected:
typedef TheISA::Addr Addr;
typedef std::multimap<Addr, int> PageTable;
PageTable lookupTable; // Quick lookup into page table
@ -83,7 +82,6 @@ class AlphaTLB : public SimObject
class AlphaITB : public AlphaTLB
{
protected:
typedef TheISA::Addr Addr;
mutable Stats::Scalar<> hits;
mutable Stats::Scalar<> misses;
mutable Stats::Scalar<> acv;

4
arch/alpha/faults.hh
View file

@ -34,14 +34,12 @@
class AlphaFault : public Fault
{
protected:
typedef TheISA::Addr Addr;
public:
AlphaFault(char * newName, int newId, Addr newVect)
: Fault(newName, newId), vect(newVect)
{;}
TheISA::Addr vect;
Addr vect;
};
extern class ResetFaultType : public AlphaFault

4
arch/alpha/isa/branch.isa
View file

@ -39,8 +39,6 @@ output header {{
*/
class PCDependentDisassembly : public AlphaStaticInst
{
protected:
typedef TheISA::Addr Addr;
protected:
/// Cached program counter from last disassembly
mutable Addr cachedPC;
@ -66,7 +64,6 @@ output header {{
class Branch : public PCDependentDisassembly
{
protected:
typedef TheISA::Addr Addr;
/// Displacement to target address (signed).
int32_t disp;
@ -90,7 +87,6 @@ output header {{
class Jump : public PCDependentDisassembly
{
protected:
typedef TheISA::Addr Addr;
/// Displacement to target address (signed).
int32_t disp;

2
arch/alpha/isa_traits.hh
View file

@ -56,7 +56,7 @@ namespace AlphaISA
{
typedef uint32_t MachInst;
typedef uint64_t Addr;
// typedef uint64_t Addr;
typedef uint8_t RegIndex;
enum {

3
arch/alpha/stacktrace.hh
View file

@ -37,8 +37,6 @@ class StackTrace;
class ProcessInfo
{
protected:
typedef TheISA::Addr Addr;
private:
ExecContext *xc;
@ -59,7 +57,6 @@ class ProcessInfo
class StackTrace
{
protected:
typedef TheISA::Addr Addr;
typedef TheISA::MachInst MachInst;
private:
ExecContext *xc;

16
arch/alpha/vtophys.hh
View file

@ -35,16 +35,16 @@ class ExecContext;
class PhysicalMemory;
AlphaISA::PageTableEntry
kernel_pte_lookup(PhysicalMemory *pmem, AlphaISA::Addr ptbr, AlphaISA::VAddr vaddr);
kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr);
AlphaISA::Addr vtophys(PhysicalMemory *xc, AlphaISA::Addr vaddr);
AlphaISA::Addr vtophys(ExecContext *xc, AlphaISA::Addr vaddr);
uint8_t *vtomem(ExecContext *xc, AlphaISA::Addr vaddr, size_t len);
uint8_t *ptomem(ExecContext *xc, AlphaISA::Addr paddr, size_t len);
Addr vtophys(PhysicalMemory *xc, Addr vaddr);
Addr vtophys(ExecContext *xc, Addr vaddr);
uint8_t *vtomem(ExecContext *xc, Addr vaddr, size_t len);
uint8_t *ptomem(ExecContext *xc, Addr paddr, size_t len);
void CopyOut(ExecContext *xc, void *dst, AlphaISA::Addr src, size_t len);
void CopyIn(ExecContext *xc, AlphaISA::Addr dst, void *src, size_t len);
void CopyString(ExecContext *xc, char *dst, AlphaISA::Addr vaddr, size_t maxlen);
void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
void CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
#endif // __ARCH_ALPHA_VTOPHYS_H__

1
base/loader/object_file.hh
View file

@ -37,7 +37,6 @@ class SymbolTable;
class ObjectFile
{
public:
typedef TheISA::Addr Addr;
enum Arch {
UnknownArch,

3
base/loader/symtab.hh
View file

@ -37,9 +37,8 @@
class Checkpoint;
class SymbolTable
{
typedef TheISA::Addr Addr;
public:
typedef std::map<TheISA::Addr, std::string> ATable;
typedef std::map<Addr, std::string> ATable;
typedef std::map<std::string, Addr> STable;
private:

1
base/remote_gdb.hh
View file

@ -44,7 +44,6 @@ class GDBListener;
class RemoteGDB
{
protected:
typedef TheISA::Addr Addr;
typedef TheISA::MachInst MachInst;
private:
friend void debugger();

1
cpu/base.hh
View file

@ -48,7 +48,6 @@ class ExecContext;
class BaseCPU : public SimObject
{
protected:
typedef TheISA::Addr Addr;
// CPU's clock period in terms of the number of ticks of curTime.
Tick clock;

2
cpu/base_dyn_inst.hh
View file

@ -62,8 +62,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
/// Binary machine instruction type.
typedef TheISA::MachInst MachInst;
/// Memory address type.
typedef TheISA::Addr Addr;
/// Logical register index type.
typedef TheISA::RegIndex RegIndex;
/// Integer register index type.

1
cpu/exec_context.hh
View file

@ -69,7 +69,6 @@ class ExecContext
{
protected:
typedef TheISA::RegFile RegFile;
typedef TheISA::Addr Addr;
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscRegFile MiscRegFile;
public:

3
cpu/exetrace.hh
View file

@ -46,7 +46,6 @@ namespace Trace {
class InstRecord : public Record
{
protected:
typedef TheISA::Addr Addr;
typedef TheISA::IntRegFile IntRegFile;
// The following fields are initialized by the constructor and
@ -172,7 +171,7 @@ inline
InstRecord *
getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
const StaticInstPtr staticInst,
TheISA::Addr pc, int thread = 0)
Addr pc, int thread = 0)
{
if (DTRACE(InstExec) &&
(InstRecord::traceMisspec() || !xc->misspeculating())) {

2
cpu/memtest/memtest.hh
View file

@ -42,8 +42,6 @@
class ExecContext;
class MemTest : public SimObject
{
protected:
typedef TheISA::Addr Addr;
public:
MemTest(const std::string &name,

2
cpu/o3/2bit_local_pred.hh
View file

@ -35,8 +35,6 @@
class DefaultBP
{
protected:
typedef TheISA::Addr Addr;
public:
/**
* Default branch predictor constructor.

1
cpu/o3/alpha_cpu.hh
View file

@ -40,7 +40,6 @@ template <class Impl>
class AlphaFullCPU : public FullO3CPU<Impl>
{
protected:
typedef AlphaISA::Addr Addr;
typedef TheISA::IntReg IntReg;
public:
typedef typename Impl::Params Params;

2
cpu/o3/alpha_dyn_inst.hh
View file

@ -50,8 +50,6 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
/** Memory address type. */
typedef TheISA::Addr Addr;
/** Logical register index type. */
typedef TheISA::RegIndex RegIndex;
/** Integer register index type. */

2
cpu/o3/bpred_unit.hh
View file

@ -53,8 +53,6 @@
template<class Impl>
class TwobitBPredUnit
{
protected:
typedef TheISA::Addr Addr;
public:
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;

2
cpu/o3/btb.hh
View file

@ -34,8 +34,6 @@
class DefaultBTB
{
protected:
typedef TheISA::Addr Addr;
private:
struct BTBEntry
{

3
cpu/o3/decode.hh
View file

@ -49,9 +49,6 @@ class SimpleDecode
typedef typename CPUPol::DecodeStruct DecodeStruct;
typedef typename CPUPol::TimeStruct TimeStruct;
// Typedefs from the ISA.
typedef TheISA::Addr Addr;
public:
// The only time decode will become blocked is if dispatch becomes
// blocked, which means IQ or ROB is probably full.

1
cpu/o3/fetch.hh
View file

@ -61,7 +61,6 @@ class SimpleFetch
/** Typedefs from ISA. */
typedef TheISA::MachInst MachInst;
typedef TheISA::Addr Addr;
public:
enum Status {

2
cpu/o3/ras.hh
View file

@ -34,8 +34,6 @@
class ReturnAddrStack
{
protected:
typedef TheISA::Addr Addr;
public:
ReturnAddrStack(unsigned numEntries);

1
cpu/o3/regfile.hh
View file

@ -53,7 +53,6 @@ template <class Impl>
class PhysRegFile
{
protected:
typedef TheISA::Addr Addr;
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::MiscRegFile MiscRegFile;

1
cpu/o3/rename.hh
View file

@ -61,7 +61,6 @@ class SimpleRename
typedef typename CPUPol::RenameMap RenameMap;
// Typedefs from the ISA.
typedef TheISA::Addr Addr;
typedef TheISA::RegIndex RegIndex;
public:

2
cpu/o3/store_set.hh
View file

@ -36,8 +36,6 @@
class StoreSet
{
protected:
typedef TheISA::Addr Addr;
public:
typedef unsigned SSID;

2
cpu/o3/tournament_pred.hh
View file

@ -35,8 +35,6 @@
class TournamentBP
{
protected:
typedef TheISA::Addr Addr;
public:
/**
* Default branch predictor constructor.

4
cpu/pc_event.cc
View file

@ -136,14 +136,14 @@ BreakPCEvent::process(ExecContext *xc)
#if FULL_SYSTEM
extern "C"
void
sched_break_pc_sys(System *sys, TheISA::Addr addr)
sched_break_pc_sys(System *sys, Addr addr)
{
new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
}
extern "C"
void
sched_break_pc(TheISA::Addr addr)
sched_break_pc(Addr addr)
{
for (vector<System *>::iterator sysi = System::systemList.begin();
sysi != System::systemList.end(); ++sysi) {

3
cpu/pc_event.hh
View file

@ -39,7 +39,6 @@ class PCEventQueue;
class PCEvent
{
protected:
typedef TheISA::Addr Addr;
static const Addr badpc = MemReq::inval_addr;
protected:
@ -65,7 +64,6 @@ class PCEvent
class PCEventQueue
{
protected:
typedef TheISA::Addr Addr;
typedef PCEvent * record_t;
class MapCompare {
public:
@ -134,7 +132,6 @@ PCEvent::remove()
class BreakPCEvent : public PCEvent
{
protected:
typedef TheISA::Addr Addr;
bool remove;
public:

4
cpu/profile.hh
View file

@ -37,8 +37,6 @@
class ProfileNode
{
protected:
typedef TheISA::Addr Addr;
private:
friend class FunctionProfile;
@ -59,8 +57,6 @@ class ProfileNode
class Callback;
class FunctionProfile
{
public:
typedef TheISA::Addr Addr;
private:
Callback *reset;
const SymbolTable *symtab;

2
cpu/static_inst.hh
View file

@ -229,8 +229,6 @@ class StaticInst : public StaticInstBase
/// Binary machine instruction type.
typedef TheISA::MachInst MachInst;
/// Memory address type.
typedef TheISA::Addr Addr;
/// Logical register index type.
typedef TheISA::RegIndex RegIndex;

2
cpu/trace/opt_cpu.hh
View file

@ -49,8 +49,6 @@ class MemTraceReader;
*/
class OptCPU : public SimObject
{
protected:
typedef TheISA::Addr Addr;
private:
typedef int RefIndex;

2
cpu/trace/reader/itx_reader.hh
View file

@ -46,8 +46,6 @@
*/
class ITXReader : public MemTraceReader
{
protected:
typedef TheISA::Addr Addr;
private:
/** Trace file. */
FILE *trace;

2
dev/ide_disk.hh
View file

@ -187,8 +187,6 @@ class IdeController;
*/
class IdeDisk : public SimObject
{
protected:
typedef TheISA::Addr Addr;
protected:
/** The IDE controller for this disk. */
IdeController *ctrl;

2
dev/pcidev.hh
View file

@ -53,8 +53,6 @@ class MemoryController;
*/
class PciConfigData : public SimObject
{
protected:
typedef TheISA::Addr Addr;
public:
/**
* Constructor to initialize the devices config space to 0.

2
dev/platform.hh
View file

@ -44,8 +44,6 @@ class Uart;
class Platform : public SimObject
{
protected:
typedef TheISA::Addr Addr;
public:
/** Pointer to the interrupt controller */
IntrControl *intrctrl;

2
dev/simple_disk.hh
View file

@ -44,8 +44,6 @@ class PhysicalMemory;
*/
class SimpleDisk : public SimObject
{
protected:
typedef TheISA::Addr Addr;
public:
typedef uint64_t baddr_t;

4
dev/sinicreg.hh
View file

@ -163,7 +163,7 @@ struct Info
/* namespace Regs */ }
inline const Regs::Info&
regInfo(TheISA::Addr daddr)
regInfo(Addr daddr)
{
static Regs::Info invalid = { 0, false, false, "invalid" };
static Regs::Info info [] = {
@ -199,7 +199,7 @@ regInfo(TheISA::Addr daddr)
}
inline bool
regValid(TheISA::Addr daddr)
regValid(Addr daddr)
{
if (daddr > Regs::Size)
return false;

2
dev/tsunami.hh
View file

@ -55,8 +55,6 @@ class System;
class Tsunami : public Platform
{
protected:
typedef TheISA::Addr Addr;
public:
/** Max number of CPUs in a Tsunami */
static const int Max_CPUs = 64;

4
kern/kernel_stats.hh
View file

@ -50,8 +50,6 @@ extern const char *modestr[];
class Binning
{
protected:
typedef TheISA::Addr Addr;
private:
std::string myname;
System *system;
@ -126,8 +124,6 @@ class Binning
class Statistics : public Serializable
{
protected:
typedef TheISA::Addr Addr;
private:
friend class Binning;

2
kern/linux/aligned.hh
View file

@ -37,7 +37,7 @@
#if __GNUC__ == 3 && __GNUC_MINOR__ != 3
typedef uint64_t uint64_ta __attribute__ ((aligned (8))) ;
typedef int64_t int64_ta __attribute__ ((aligned (8))) ;
typedef TheISA::Addr Addr_a __attribute__ ((aligned (8))) ;
typedef Addr Addr_a __attribute__ ((aligned (8))) ;
#else
#define uint64_ta uint64_t __attribute__ ((aligned (8)))
#define int64_ta int64_t __attribute__ ((aligned (8)))

3
kern/linux/linux.hh
View file

@ -53,9 +53,6 @@ class Linux {};
///
class Linux {
protected:
typedef TheISA::Addr Addr;
public:
//@{

2
kern/linux/linux_threadinfo.hh
View file

@ -37,8 +37,6 @@ namespace Linux {
class ThreadInfo
{
protected:
typedef TheISA::Addr Addr;
private:
ExecContext *xc;

22
kern/tru64/mbuf.hh
View file

@ -35,35 +35,35 @@
namespace tru64 {
struct m_hdr {
TheISA::Addr mh_next; // 0x00
TheISA::Addr mh_nextpkt; // 0x08
TheISA::Addr mh_data; // 0x10
Addr mh_next; // 0x00
Addr mh_nextpkt; // 0x08
Addr mh_data; // 0x10
int32_t mh_len; // 0x18
int32_t mh_type; // 0x1C
int32_t mh_flags; // 0x20
int32_t mh_pad0; // 0x24
TheISA::Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40
Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40
};
struct pkthdr {
int32_t len;
int32_t protocolSum;
TheISA::Addr rcvif;
Addr rcvif;
};
struct m_ext {
TheISA::Addr ext_buf; // 0x00
TheISA::Addr ext_free; // 0x08
Addr ext_buf; // 0x00
Addr ext_free; // 0x08
uint32_t ext_size; // 0x10
uint32_t ext_pad0; // 0x14
TheISA::Addr ext_arg; // 0x18
Addr ext_arg; // 0x18
struct ext_refq {
TheISA::Addr forw, back; // 0x20, 0x28
Addr forw, back; // 0x20, 0x28
} ext_ref;
TheISA::Addr uiomove_f; // 0x30
Addr uiomove_f; // 0x30
int32_t protocolSum; // 0x38
int32_t bytesSummed; // 0x3C
TheISA::Addr checksum; // 0x40
Addr checksum; // 0x40
};
struct mbuf {

49
kern/tru64/tru64.hh
View file

@ -392,7 +392,7 @@ class Tru64 {
/// For stack_create.
struct vm_stack {
// was void *
TheISA::Addr address; //!< address hint
Addr address; //!< address hint
size_t rsize; //!< red zone size
size_t ysize; //!< yellow zone size
size_t gsize; //!< green zone size
@ -401,7 +401,7 @@ class Tru64 {
uint64_t align; //!< address alignment
uint64_t flags; //!< MAP_FIXED etc.
// was struct memalloc_attr *
TheISA::Addr attr; //!< allocation policy
Addr attr; //!< allocation policy
uint64_t reserved; //!< reserved
};
@ -433,7 +433,7 @@ class Tru64 {
sigset_t sigmask; //!< thread signal mask
sigset_t sig; //!< thread pending mask
// struct nxm_pth_state *
TheISA::Addr pth_id; //!< out-of-line state
Addr pth_id; //!< out-of-line state
int flags; //!< shared flags
#define US_SIGSTACK 0x1 // thread called sigaltstack
#define US_ONSTACK 0x2 // thread is running on altstack
@ -469,12 +469,12 @@ class Tru64 {
int nxm_set_quantum; //!< quantum reset value
int nxm_sysevent; //!< syscall state
// struct nxm_upcall *
TheISA::Addr nxm_uc_ret; //!< stack ptr of null thread
Addr nxm_uc_ret; //!< stack ptr of null thread
// void *
TheISA::Addr nxm_tid; //!< scheduler's thread id
Addr nxm_tid; //!< scheduler's thread id
int64_t nxm_va; //!< page fault address
// struct nxm_pth_state *
TheISA::Addr nxm_pthid; //!< id of null thread
Addr nxm_pthid; //!< id of null thread
uint64_t nxm_bound_pcs_count; //!< bound PCS thread count
int64_t pad[2]; //!< pad
};
@ -502,9 +502,9 @@ class Tru64 {
int nxm_nslots_per_rad; //!< max number of VP slots per RAD
int nxm_nrads; //!< max number of RADs
// nxm_slot_state_t *
TheISA::Addr nxm_slot_state; //!< per-VP slot state
Addr nxm_slot_state; //!< per-VP slot state
// struct nxm_shared *
TheISA::Addr nxm_rad[1]; //!< per-RAD shared areas
Addr nxm_rad[1]; //!< per-RAD shared areas
};
/// For nxm_thread_create.
@ -523,7 +523,7 @@ class Tru64 {
int policy; //!< policy
int signal_type; //!< signal_type
// void *
TheISA::Addr pthid; //!< pthid
Addr pthid; //!< pthid
sigset_t sigmask; //!< sigmask
/// Initial register values.
struct {
@ -539,7 +539,7 @@ class Tru64 {
/// memory space. Used by stat(), fstat(), and lstat().
template <class T>
static void
copyOutStatBuf(FunctionalMemory *mem, TheISA::Addr addr, global_stat *host)
copyOutStatBuf(FunctionalMemory *mem, Addr addr, global_stat *host)
{
TypedBufferArg<T> tgt(addr);
@ -565,7 +565,7 @@ class Tru64 {
/// memory space. Used by statfs() and fstatfs().
template <class T>
static void
copyOutStatfsBuf(FunctionalMemory *mem, TheISA::Addr addr, global_statfs *host)
copyOutStatfsBuf(FunctionalMemory *mem, Addr addr, global_statfs *host)
{
TypedBufferArg<T> tgt(addr);
@ -589,13 +589,13 @@ class Tru64 {
class F64 {
public:
static void copyOutStatBuf(FunctionalMemory *mem, TheISA::Addr addr,
static void copyOutStatBuf(FunctionalMemory *mem, Addr addr,
global_stat *host)
{
Tru64::copyOutStatBuf<Tru64::F64_stat>(mem, addr, host);
}
static void copyOutStatfsBuf(FunctionalMemory *mem, TheISA::Addr addr,
static void copyOutStatfsBuf(FunctionalMemory *mem, Addr addr,
global_statfs *host)
{
Tru64::copyOutStatfsBuf<Tru64::F64_statfs>(mem, addr, host);
@ -604,13 +604,13 @@ class Tru64 {
class PreF64 {
public:
static void copyOutStatBuf(FunctionalMemory *mem, TheISA::Addr addr,
static void copyOutStatBuf(FunctionalMemory *mem, Addr addr,
global_stat *host)
{
Tru64::copyOutStatBuf<Tru64::pre_F64_stat>(mem, addr, host);
}
static void copyOutStatfsBuf(FunctionalMemory *mem, TheISA::Addr addr,
static void copyOutStatfsBuf(FunctionalMemory *mem, Addr addr,
global_statfs *host)
{
Tru64::copyOutStatfsBuf<Tru64::pre_F64_statfs>(mem, addr, host);
@ -622,7 +622,7 @@ class Tru64 {
/// the simulated memory space. Used by pre_F64_stat(),
/// pre_F64_fstat(), and pre_F64_lstat().
static void
copyOutPreF64StatBuf(FunctionalMemory *mem, TheISA::Addr addr, struct stat *host)
copyOutPreF64StatBuf(FunctionalMemory *mem, Addr addr, struct stat *host)
{
TypedBufferArg<Tru64::pre_F64_stat> tgt(addr);
@ -653,7 +653,6 @@ class Tru64 {
getdirentriesFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
#ifdef __CYGWIN__
panic("getdirent not implemented on cygwin!");
#else
@ -809,7 +808,6 @@ class Tru64 {
nxm_task_initFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
TypedBufferArg<Tru64::nxm_task_attr> attrp(xc->getSyscallArg(0));
TypedBufferArg<Addr> configptr_ptr(xc->getSyscallArg(1));
@ -939,7 +937,6 @@ class Tru64 {
nxm_thread_createFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
TypedBufferArg<Tru64::nxm_thread_attr> attrp(xc->getSyscallArg(0));
TypedBufferArg<uint64_t> kidp(xc->getSyscallArg(1));
int thread_index = xc->getSyscallArg(2);
@ -1079,7 +1076,6 @@ class Tru64 {
nxm_blockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
uint64_t val = xc->getSyscallArg(1);
uint64_t secs = xc->getSyscallArg(2);
@ -1101,7 +1097,6 @@ class Tru64 {
nxm_unblockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
cout << xc->cpu->name() << ": nxm_unblock "
@ -1129,7 +1124,7 @@ class Tru64 {
/// Activate exec context waiting on a channel. Just activate one
/// by default.
static int
activate_waiting_context(TheISA::Addr uaddr, Process *process,
activate_waiting_context(Addr uaddr, Process *process,
bool activate_all = false)
{
int num_activated = 0;
@ -1158,7 +1153,7 @@ class Tru64 {
/// M5 hacked-up lock acquire.
static void
m5_lock_mutex(TheISA::Addr uaddr, Process *process, ExecContext *xc)
m5_lock_mutex(Addr uaddr, Process *process, ExecContext *xc)
{
TypedBufferArg<uint64_t> lockp(uaddr);
@ -1177,7 +1172,7 @@ class Tru64 {
/// M5 unlock call.
static void
m5_unlock_mutex(TheISA::Addr uaddr, Process *process, ExecContext *xc)
m5_unlock_mutex(Addr uaddr, Process *process, ExecContext *xc)
{
TypedBufferArg<uint64_t> lockp(uaddr);
@ -1199,7 +1194,6 @@ class Tru64 {
m5_mutex_lockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
m5_lock_mutex(uaddr, process, xc);
@ -1215,7 +1209,6 @@ class Tru64 {
m5_mutex_trylockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
TypedBufferArg<uint64_t> lockp(uaddr);
@ -1236,7 +1229,6 @@ class Tru64 {
m5_mutex_unlockFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
Addr uaddr = xc->getSyscallArg(0);
m5_unlock_mutex(uaddr, process, xc);
@ -1249,7 +1241,6 @@ class Tru64 {
m5_cond_signalFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
Addr cond_addr = xc->getSyscallArg(0);
// Wake up one process waiting on the condition variable.
@ -1263,7 +1254,6 @@ class Tru64 {
m5_cond_broadcastFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
Addr cond_addr = xc->getSyscallArg(0);
activate_waiting_context(cond_addr, process, true);
@ -1276,7 +1266,6 @@ class Tru64 {
m5_cond_waitFunc(SyscallDesc *desc, int callnum, Process *process,
ExecContext *xc)
{
using TheISA::Addr;
Addr cond_addr = xc->getSyscallArg(0);
Addr lock_addr = xc->getSyscallArg(1);
TypedBufferArg<uint64_t> condp(cond_addr);

8
sim/host.hh
View file

@ -54,4 +54,12 @@ typedef int64_t Counter;
*/
typedef int64_t Tick;
/**
* Address type
* This will probably be moved somewhere else in the near future.
* This should be at least as big as the biggest address width in use
* in the system, which will probably be 64 bits.
*/
typedef uint64_t Addr;
#endif // __HOST_H__

1
sim/process.hh
View file

@ -52,7 +52,6 @@ class SyscallDesc;
class Process : public SimObject
{
protected:
typedef TheISA::Addr Addr;
typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
public:

4
sim/pseudo_inst.hh
View file

@ -52,8 +52,8 @@ namespace AlphaPseudo
void dumpstats(ExecContext *xc, Tick delay, Tick period);
void dumpresetstats(ExecContext *xc, Tick delay, Tick period);
void m5checkpoint(ExecContext *xc, Tick delay, Tick period);
uint64_t readfile(ExecContext *xc, TheISA::Addr vaddr, uint64_t len, uint64_t offset);
uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset);
void debugbreak(ExecContext *xc);
void switchcpu(ExecContext *xc);
void addsymbol(ExecContext *xc, TheISA::Addr addr, TheISA::Addr symbolAddr);
void addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr);
}

5
sim/syscall_emul.hh
View file

@ -90,9 +90,6 @@ class SyscallDesc {
class BaseBufferArg {
protected:
typedef TheISA::Addr Addr;
public:
BaseBufferArg(Addr _addr, int _size) : addr(_addr), size(_size)
@ -643,7 +640,7 @@ template <class OS>
SyscallReturn
mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
{
TheISA::Addr start = xc->getSyscallArg(0);
Addr start = xc->getSyscallArg(0);
uint64_t length = xc->getSyscallArg(1);
// int prot = xc->getSyscallArg(2);
int flags = xc->getSyscallArg(3);

2
sim/system.hh
View file

@ -50,8 +50,6 @@ namespace Kernel { class Binning; }
class System : public SimObject
{
protected:
typedef TheISA::Addr Addr;
public:
MemoryController *memctrl;
PhysicalMemory *physmem;

2
sim/vptr.hh
View file

@ -37,8 +37,6 @@ class ExecContext;
template <class T>
class VPtr
{
protected:
typedef TheISA::Addr Addr;
public:
typedef T Type;