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Pseudo instructions are now passed whatever instructions they need by the decoder, rather than extracting them explicitly. This lets most of the pseudo instruction code to be shared across architectures.

Browse source 
SConscript:
    Moved pseudo_inst.hh from targetarch to full system sources
arch/alpha/SConscript:
    Moved pseudo_inst.cc out of the alpha specific sources
arch/alpha/isa/decoder.isa:
    The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI
arch/alpha/isa/main.isa:
    Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly
sim/pseudo_inst.cc:
    Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments.
sim/pseudo_inst.hh:
    Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context.

--HG--
rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc
rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh
extra : convert_revision : 76ce768cf1d8a838aa7b64878a7ab4c4215ac999
This commit is contained in:
Gabe Black 2006-02-12 17:38:10 -05:00
parent 2c5e03550a
commit 19e5efed03
6 changed files with 37 additions and 44 deletions
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3
SConscript
View file

@ -292,6 +292,7 @@ full_system_sources = Split('''
mem/functional/physical.cc
sim/system.cc
sim/pseudo_inst.cc
''')
# These are now included by the architecture specific SConscript
@ -347,10 +348,10 @@ targetarch_files = Split('''
ecoff_machdep.h
ev5.hh
faults.hh
pseudo_inst.hh
stacktrace.hh
vtophys.hh
''')
# pseudo_inst.hh
# isa_traits.hh
# osfpal.hh
# byte_swap.hh

1
arch/alpha/SConscript
View file

@ -244,7 +244,6 @@ arch_full_system_sources = Split('''
arch/alpha/arguments.cc
arch/alpha/ev5.cc
arch/alpha/osfpal.cc
arch/alpha/pseudo_inst.cc
arch/alpha/stacktrace.cc
arch/alpha/vtophys.cc
''')

14
arch/alpha/isa/decoder.isa
View file

@ -768,23 +768,23 @@ decode OPCODE default Unknown::unknown() {
AlphaPseudo::m5exit_old(xc->xcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
AlphaPseudo::m5exit(xc->xcBase());
AlphaPseudo::m5exit(xc->xcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
0x40: resetstats({{
AlphaPseudo::resetstats(xc->xcBase());
AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
AlphaPseudo::dumpstats(xc->xcBase());
AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
AlphaPseudo::dumpresetstats(xc->xcBase());
AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
AlphaPseudo::m5checkpoint(xc->xcBase());
AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
AlphaPseudo::readfile(xc->xcBase());
R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
AlphaPseudo::debugbreak(xc->xcBase());
@ -793,7 +793,7 @@ decode OPCODE default Unknown::unknown() {
AlphaPseudo::switchcpu(xc->xcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
AlphaPseudo::addsymbol(xc->xcBase());
AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
}

4
arch/alpha/isa/main.isa
View file

@ -160,7 +160,9 @@ def operands {{
'FPCR': (' ControlReg', 'uq', 'Fpcr', None, 1),
# The next two are hacks for non-full-system call-pal emulation
'R0': ('IntReg', 'uq', '0', None, 1),
'R16': ('IntReg', 'uq', '16', None, 1)
'R16': ('IntReg', 'uq', '16', None, 1),
'R17': ('IntReg', 'uq', '17', None, 1),
'R18': ('IntReg', 'uq', '18', None, 1)
}};
////////////////////////////////////////////////////////////////////

40
arch/alpha/pseudo_inst.cc → sim/pseudo_inst.cc
View file

@ -33,8 +33,8 @@
#include <string>
#include "arch/alpha/pseudo_inst.hh"
#include "arch/alpha/vtophys.hh"
#include "sim/pseudo_inst.hh"
#include "targetarch/vtophys.hh"
#include "cpu/base.hh"
#include "cpu/sampler/sampler.hh"
#include "cpu/exec_context.hh"
@ -94,21 +94,18 @@ namespace AlphaPseudo
}
void
m5exit(ExecContext *xc)
m5exit(ExecContext *xc, Tick delay)
{
Tick delay = xc->regs.intRegFile[16];
Tick when = curTick + delay * Clock::Int::ns;
SimExit(when, "m5_exit instruction encountered");
}
void
resetstats(ExecContext *xc)
resetstats(ExecContext *xc, Tick delay, Tick period)
{
if (!doStatisticsInsts)
return;
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + delay * Clock::Int::ns;
Tick repeat = period * Clock::Int::ns;
@ -118,13 +115,11 @@ namespace AlphaPseudo
}
void
dumpstats(ExecContext *xc)
dumpstats(ExecContext *xc, Tick delay, Tick period)
{
if (!doStatisticsInsts)
return;
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + delay * Clock::Int::ns;
Tick repeat = period * Clock::Int::ns;
@ -134,11 +129,10 @@ namespace AlphaPseudo
}
void
addsymbol(ExecContext *xc)
addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr)
{
Addr addr = xc->regs.intRegFile[16];
char symb[100];
CopyString(xc, symb, xc->regs.intRegFile[17], 100);
CopyString(xc, symb, symbolAddr, 100);
std::string symbol(symb);
DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
@ -147,13 +141,11 @@ namespace AlphaPseudo
}
void
dumpresetstats(ExecContext *xc)
dumpresetstats(ExecContext *xc, Tick delay, Tick period)
{
if (!doStatisticsInsts)
return;
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + delay * Clock::Int::ns;
Tick repeat = period * Clock::Int::ns;
@ -163,13 +155,11 @@ namespace AlphaPseudo
}
void
m5checkpoint(ExecContext *xc)
m5checkpoint(ExecContext *xc, Tick delay, Tick period)
{
if (!doCheckpointInsts)
return;
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + delay * Clock::Int::ns;
Tick repeat = period * Clock::Int::ns;
@ -177,18 +167,14 @@ namespace AlphaPseudo
Checkpoint::setup(when, repeat);
}
void
readfile(ExecContext *xc)
uint64_t
readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset)
{
const string &file = xc->cpu->system->params->readfile;
if (file.empty()) {
xc->regs.intRegFile[0] = ULL(0);
return;
return ULL(0);
}
Addr vaddr = xc->regs.intRegFile[16];
uint64_t len = xc->regs.intRegFile[17];
uint64_t offset = xc->regs.intRegFile[18];
uint64_t result = 0;
int fd = ::open(file.c_str(), O_RDONLY, 0);
@ -213,7 +199,7 @@ namespace AlphaPseudo
close(fd);
CopyIn(xc, vaddr, buf, result);
delete [] buf;
xc->regs.intRegFile[0] = result;
return result;
}
class Context : public ParamContext

19
arch/alpha/pseudo_inst.hh → sim/pseudo_inst.hh
View file

@ -28,6 +28,11 @@
class ExecContext;
//We need the "Tick" data type from here
#include "sim/host.hh"
//We need the "Addr" data type from here
#include "arch/isa_traits.hh"
namespace AlphaPseudo
{
/**
@ -41,14 +46,14 @@ namespace AlphaPseudo
void quiesce(ExecContext *xc);
void ivlb(ExecContext *xc);
void ivle(ExecContext *xc);
void m5exit(ExecContext *xc);
void m5exit(ExecContext *xc, Tick delay);
void m5exit_old(ExecContext *xc);
void resetstats(ExecContext *xc);
void dumpstats(ExecContext *xc);
void dumpresetstats(ExecContext *xc);
void m5checkpoint(ExecContext *xc);
void readfile(ExecContext *xc);
void resetstats(ExecContext *xc, Tick delay, Tick period);
void dumpstats(ExecContext *xc, Tick delay, Tick period);
void dumpresetstats(ExecContext *xc, Tick delay, Tick period);
void m5checkpoint(ExecContext *xc, Tick delay, Tick period);
uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset);
void debugbreak(ExecContext *xc);
void switchcpu(ExecContext *xc);
void addsymbol(ExecContext *xc);
void addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr);
}