sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.

Browse source 
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
This commit is contained in:
Gabe Black 2006-02-21 20:10:40 -05:00
parent 3f7979c99d
commit 8d80fd1477
53 changed files with 317 additions and 315 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
arch/alpha/alpha_memory.cc
View file

@ -303,7 +303,7 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const
}
Fault *
Fault
AlphaITB::translate(MemReqPtr &req) const
{
InternalProcReg *ipr = req->xc->regs.ipr;
@ -493,7 +493,7 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
}
}
Fault *
Fault
AlphaDTB::translate(MemReqPtr &req, bool write) const
{
RegFile *regs = &req->xc->regs;
@ -575,7 +575,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
fault(req, (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK);
if (write) { write_misses++; } else { read_misses++; }
return (req->flags & VPTE) ? (Fault *)PDtbMissFault : (Fault *)NDtbMissFault;
return (req->flags & VPTE) ? (Fault)PDtbMissFault : (Fault)NDtbMissFault;
}
req->paddr = (pte->ppn << AlphaISA::PageShift) +

4
arch/alpha/alpha_memory.hh
View file

@ -94,7 +94,7 @@ class AlphaITB : public AlphaTLB
AlphaITB(const std::string &name, int size);
virtual void regStats();
Fault * translate(MemReqPtr &req) const;
Fault translate(MemReqPtr &req) const;
};
class AlphaDTB : public AlphaTLB
@ -120,7 +120,7 @@ class AlphaDTB : public AlphaTLB
AlphaDTB(const std::string &name, int size);
virtual void regStats();
Fault * translate(MemReqPtr &req, bool write) const;
Fault translate(MemReqPtr &req, bool write) const;
};
#endif // __ALPHA_MEMORY_HH__

12
arch/alpha/ev5.cc
View file

@ -85,7 +85,7 @@ AlphaISA::initCPU(RegFile *regs)
// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
//
const Addr
AlphaISA::fault_addr(Fault * fault)
AlphaISA::fault_addr(Fault fault)
{
//Check for the system wide faults
if(fault == NoFault) return 0x0000;
@ -177,7 +177,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
}
void
ExecContext::ev5_trap(Fault * fault)
ExecContext::ev5_trap(Fault fault)
{
DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
cpu->recordEvent(csprintf("Fault %s", fault->name));
@ -209,7 +209,7 @@ ExecContext::ev5_trap(Fault * fault)
void
AlphaISA::intr_post(RegFile *regs, Fault * fault, Addr pc)
AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
{
InternalProcReg *ipr = regs->ipr;
bool use_pc = (fault == NoFault);
@ -235,7 +235,7 @@ AlphaISA::intr_post(RegFile *regs, Fault * fault, Addr pc)
// that's it! (orders of magnitude less painful than x86)
}
Fault *
Fault
ExecContext::hwrei()
{
uint64_t *ipr = regs.ipr;
@ -259,7 +259,7 @@ ExecContext::hwrei()
}
uint64_t
ExecContext::readIpr(int idx, Fault * &fault)
ExecContext::readIpr(int idx, Fault &fault)
{
uint64_t *ipr = regs.ipr;
uint64_t retval = 0; // return value, default 0
@ -370,7 +370,7 @@ ExecContext::readIpr(int idx, Fault * &fault)
int break_ipl = -1;
#endif
Fault *
Fault
ExecContext::setIpr(int idx, uint64_t val)
{
uint64_t *ipr = regs.ipr;

38
arch/alpha/faults.cc
View file

@ -57,24 +57,24 @@ PalFaultType * const PalFault =
IntegerOverflowFaultType * const IntegerOverflowFault =
new IntegerOverflowFaultType("intover", 16, 0x0501);
Fault ** ListOfFaults[] = {
(Fault **)&NoFault,
(Fault **)&ResetFault,
(Fault **)&MachineCheckFault,
(Fault **)&ArithmeticFault,
(Fault **)&InterruptFault,
(Fault **)&NDtbMissFault,
(Fault **)&PDtbMissFault,
(Fault **)&AlignmentFault,
(Fault **)&DtbPageFault,
(Fault **)&DtbAcvFault,
(Fault **)&ItbMissFault,
(Fault **)&ItbPageFault,
(Fault **)&ItbAcvFault,
(Fault **)&UnimplementedOpcodeFault,
(Fault **)&FloatEnableFault,
(Fault **)&PalFault,
(Fault **)&IntegerOverflowFault,
Fault * ListOfFaults[] = {
(Fault *)&NoFault,
(Fault *)&ResetFault,
(Fault *)&MachineCheckFault,
(Fault *)&ArithmeticFault,
(Fault *)&InterruptFault,
(Fault *)&NDtbMissFault,
(Fault *)&PDtbMissFault,
(Fault *)&AlignmentFault,
(Fault *)&DtbPageFault,
(Fault *)&DtbAcvFault,
(Fault *)&ItbMissFault,
(Fault *)&ItbPageFault,
(Fault *)&ItbAcvFault,
(Fault *)&UnimplementedOpcodeFault,
(Fault *)&FloatEnableFault,
(Fault *)&PalFault,
(Fault *)&IntegerOverflowFault,
};
int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **);
int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);

6
arch/alpha/faults.hh
View file

@ -32,11 +32,11 @@
#include "sim/faults.hh"
#include "arch/isa_traits.hh" //For the Addr type
class AlphaFault : public Fault
class AlphaFault : public FaultBase
{
public:
AlphaFault(char * newName, int newId, Addr newVect)
: Fault(newName, newId), vect(newVect)
: FaultBase(newName, newId), vect(newVect)
{;}
Addr vect;
@ -154,7 +154,7 @@ extern class IntegerOverflowFaultType : public AlphaFault
{;}
} * const IntegerOverflowFault;
extern Fault ** ListOfFaults[];
extern Fault * ListOfFaults[];
extern int NumFaults;
#endif // __FAULTS_HH__

14
arch/alpha/isa/fp.isa
View file

@ -32,16 +32,16 @@ output exec {{
/// @retval Full-system mode: NoFault if FP is enabled, FenFault
/// if not. Non-full-system mode: always returns NoFault.
#if FULL_SYSTEM
inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault * fault = NoFault; // dummy... this ipr access should not fault
Fault fault = NoFault; // dummy... this ipr access should not fault
if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
fault = FloatEnableFault;
}
return fault;
}
#else
inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
return NoFault;
}
@ -199,7 +199,7 @@ output decoder {{
// FP instruction class execute method template. Handles non-standard
// rounding modes.
def template FloatingPointExecute {{
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
@ -208,7 +208,7 @@ def template FloatingPointExecute {{
warnedOnTrapping = true;
}
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -242,7 +242,7 @@ def template FloatingPointExecute {{
// rounding mode control is needed. Like BasicExecute, but includes
// check & warning for non-standard trapping mode.
def template FPFixedRoundingExecute {{
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
@ -251,7 +251,7 @@ def template FPFixedRoundingExecute {{
warnedOnTrapping = true;
}
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;

8
arch/alpha/isa/main.isa
View file

@ -258,7 +258,7 @@ output decoder {{
// Declarations for execute() methods.
def template BasicExecDeclare {{
Fault * execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
@ -287,10 +287,10 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -382,7 +382,7 @@ output decoder {{
}};
output exec {{
Fault *
Fault
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{
return NoFault;

52
arch/alpha/isa/mem.isa
View file

@ -173,12 +173,12 @@ def template LoadStoreDeclare {{
def template InitiateAccDeclare {{
Fault * initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template CompleteAccDeclare {{
Fault * completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
@ -208,12 +208,12 @@ def template LoadStoreConstructor {{
def template EACompExecute {{
Fault *
Fault
%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -230,12 +230,12 @@ def template EACompExecute {{
}};
def template LoadMemAccExecute {{
Fault *
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -257,11 +257,11 @@ def template LoadMemAccExecute {{
def template LoadExecute {{
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -283,11 +283,11 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
@ -304,11 +304,11 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault * %(class_name)s::completeAcc(uint8_t *data,
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
@ -330,12 +330,12 @@ def template LoadCompleteAcc {{
def template StoreMemAccExecute {{
Fault *
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@ -367,11 +367,11 @@ def template StoreMemAccExecute {{
def template StoreExecute {{
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@ -402,11 +402,11 @@ def template StoreExecute {{
}};
def template StoreInitiateAcc {{
Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@ -431,11 +431,11 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault * %(class_name)s::completeAcc(uint8_t *data,
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault * fault = NoFault;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@ -457,11 +457,11 @@ def template StoreCompleteAcc {{
def template MiscMemAccExecute {{
Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -477,11 +477,11 @@ def template MiscMemAccExecute {{
}};
def template MiscExecute {{
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -497,7 +497,7 @@ def template MiscExecute {{
}};
def template MiscInitiateAcc {{
Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("Misc instruction does not support split access method!");
@ -507,7 +507,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
Fault * %(class_name)s::completeAcc(uint8_t *data,
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{

4
arch/alpha/isa/unimp.isa
View file

@ -105,7 +105,7 @@ output decoder {{
}};
output exec {{
Fault *
Fault
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@ -114,7 +114,7 @@ output exec {{
return UnimplementedOpcodeFault;
}
Fault *
Fault
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{

2
arch/alpha/isa/unknown.isa
View file

@ -36,7 +36,7 @@ output decoder {{
}};
output exec {{
Fault *
Fault
Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{

40
arch/mips/isa/formats/mem.isa
View file

@ -131,12 +131,12 @@ def template LoadStoreDeclare {{
def template InitiateAccDeclare {{
Fault * initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template CompleteAccDeclare {{
Fault * completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
@ -166,12 +166,12 @@ def template LoadStoreConstructor {{
def template EACompExecute {{
Fault *
Fault
%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -188,12 +188,12 @@ def template EACompExecute {{
}};
def template LoadMemAccExecute {{
Fault *
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -215,11 +215,11 @@ def template LoadMemAccExecute {{
def template LoadExecute {{
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
@ -241,11 +241,11 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
@ -262,11 +262,11 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault * %(class_name)s::completeAcc(uint8_t *data,
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault * fault = NoFault;
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_src_decl)s;
@ -288,12 +288,12 @@ def template LoadCompleteAcc {{
def template StoreMemAccExecute {{
Fault *
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@ -325,11 +325,11 @@ def template StoreMemAccExecute {{
def template StoreExecute {{
Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@ -360,11 +360,11 @@ def template StoreExecute {{
}};
def template StoreInitiateAcc {{
Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault * fault = NoFault;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@ -389,11 +389,11 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault * %(class_name)s::completeAcc(uint8_t *data,
Fault %(class_name)s::completeAcc(uint8_t *data,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault * fault = NoFault;
Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;

14
cpu/base_dyn_inst.cc
View file

@ -145,7 +145,7 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
fault = NoFault;
// note this is a local, not BaseDynInst::fault
Fault * trans_fault = xc->translateDataReadReq(req);
Fault trans_fault = xc->translateDataReadReq(req);
if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
// It's a valid address to cacheable space. Record key MemReq
@ -208,14 +208,14 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
* @todo Need to find a way to get the cache block size here.
*/
template <class Impl>
Fault *
Fault
BaseDynInst<Impl>::copySrcTranslate(Addr src)
{
MemReqPtr req = new MemReq(src, xc, 64);
req->asid = asid;
// translate to physical address
Fault * fault = xc->translateDataReadReq(req);
Fault fault = xc->translateDataReadReq(req);
if (fault == NoFault) {
xc->copySrcAddr = src;
@ -231,7 +231,7 @@ BaseDynInst<Impl>::copySrcTranslate(Addr src)
* @todo Need to find a way to get the cache block size here.
*/
template <class Impl>
Fault *
Fault
BaseDynInst<Impl>::copy(Addr dest)
{
uint8_t data[64];
@ -241,7 +241,7 @@ BaseDynInst<Impl>::copy(Addr dest)
req->asid = asid;
// translate to physical address
Fault * fault = xc->translateDataWriteReq(req);
Fault fault = xc->translateDataWriteReq(req);
if (fault == NoFault) {
Addr dest_addr = req->paddr;
@ -277,10 +277,10 @@ BaseDynInst<Impl>::dump(std::string &outstring)
#if 0
template <class Impl>
Fault *
Fault
BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
{
Fault * fault;
Fault fault;
// check alignments, even speculative this test should always pass
if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {

18
cpu/base_dyn_inst.hh
View file

@ -83,16 +83,16 @@ class BaseDynInst : public FastAlloc, public RefCounted
Trace::InstRecord *traceData;
template <class T>
Fault * read(Addr addr, T &data, unsigned flags);
Fault read(Addr addr, T &data, unsigned flags);
template <class T>
Fault * write(T data, Addr addr, unsigned flags,
Fault write(T data, Addr addr, unsigned flags,
uint64_t *res);
void prefetch(Addr addr, unsigned flags);
void writeHint(Addr addr, int size, unsigned flags);
Fault * copySrcTranslate(Addr src);
Fault * copy(Addr dest);
Fault copySrcTranslate(Addr src);
Fault copy(Addr dest);
/** @todo: Consider making this private. */
public:
@ -148,7 +148,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
ExecContext *xc;
/** The kind of fault this instruction has generated. */
Fault * fault;
Fault fault;
/** The effective virtual address (lds & stores only). */
Addr effAddr;
@ -219,7 +219,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
public:
void
trace_mem(Fault * fault, // last fault
trace_mem(Fault fault, // last fault
MemCmd cmd, // last command
Addr addr, // virtual address of access
void *p, // memory accessed
@ -232,7 +232,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
void dump(std::string &outstring);
/** Returns the fault type. */
Fault * getFault() { return fault; }
Fault getFault() { return fault; }
/** Checks whether or not this instruction has had its branch target
* calculated yet. For now it is not utilized and is hacked to be
@ -441,7 +441,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
template<class Impl>
template<class T>
inline Fault *
inline Fault
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
{
MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
@ -484,7 +484,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
template<class Impl>
template<class T>
inline Fault *
inline Fault
BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
if (traceData) {

2
cpu/exec_context.cc
View file

@ -221,7 +221,7 @@ ExecContext::regStats(const string &name)
}
void
ExecContext::trap(Fault * fault)
ExecContext::trap(Fault fault)
{
//TheISA::trap(fault); //One possible way to do it...

32
cpu/exec_context.hh
View file

@ -213,17 +213,17 @@ class ExecContext
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
Fault * translateInstReq(MemReqPtr &req)
Fault translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
Fault * translateDataReadReq(MemReqPtr &req)
Fault translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
Fault * translateDataWriteReq(MemReqPtr &req)
Fault translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
@ -238,7 +238,7 @@ class ExecContext
int getInstAsid() { return asid; }
int getDataAsid() { return asid; }
Fault * dummyTranslation(MemReqPtr &req)
Fault dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@ -249,15 +249,15 @@ class ExecContext
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
return NoFault;
}
Fault * translateInstReq(MemReqPtr &req)
Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault * translateDataReadReq(MemReqPtr &req)
Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault * translateDataWriteReq(MemReqPtr &req)
Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@ -265,7 +265,7 @@ class ExecContext
#endif
template <class T>
Fault * read(MemReqPtr &req, T &data)
Fault read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@ -275,14 +275,14 @@ class ExecContext
}
#endif
Fault * error;
Fault error;
error = mem->read(req, data);
data = LittleEndianGuest::gtoh(data);
return error;
}
template <class T>
Fault * write(MemReqPtr &req, T &data)
Fault write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@ -340,7 +340,7 @@ class ExecContext
inst = new_inst;
}
Fault * instRead(MemReqPtr &req)
Fault instRead(MemReqPtr &req)
{
return mem->read(req, inst);
}
@ -419,13 +419,13 @@ class ExecContext
}
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault * &fault);
Fault * setIpr(int idx, uint64_t val);
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
int readIntrFlag() { return regs.intrflag; }
void setIntrFlag(int val) { regs.intrflag = val; }
Fault * hwrei();
Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
void ev5_trap(Fault * fault);
void ev5_trap(Fault fault);
bool simPalCheck(int palFunc);
#endif
@ -435,7 +435,7 @@ class ExecContext
* @todo How to do this properly so it's dependent upon ISA only?
*/
void trap(Fault * fault);
void trap(Fault fault);
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)

34
cpu/o3/alpha_cpu.hh
View file

@ -63,23 +63,23 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// void clear_interrupt(int int_num, int index);
// void clear_interrupts();
Fault * translateInstReq(MemReqPtr &req)
Fault translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
Fault * translateDataReadReq(MemReqPtr &req)
Fault translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
Fault * translateDataWriteReq(MemReqPtr &req)
Fault translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
#else
Fault * dummyTranslation(MemReqPtr &req)
Fault dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@ -91,17 +91,17 @@ class AlphaFullCPU : public FullO3CPU<Impl>
return NoFault;
}
Fault * translateInstReq(MemReqPtr &req)
Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault * translateDataReadReq(MemReqPtr &req)
Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault * translateDataWriteReq(MemReqPtr &req)
Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@ -136,16 +136,16 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// look like.
#if FULL_SYSTEM
uint64_t *getIpr();
uint64_t readIpr(int idx, Fault * &fault);
Fault * setIpr(int idx, uint64_t val);
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
int readIntrFlag();
void setIntrFlag(int val);
Fault * hwrei();
Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
bool inPalMode(uint64_t PC)
{ return AlphaISA::PcPAL(PC); }
void trap(Fault * fault);
void trap(Fault fault);
bool simPalCheck(int palFunc);
void processInterrupts();
@ -198,7 +198,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
bool palShadowEnabled;
// Not sure this is used anywhere.
void intr_post(RegFile *regs, Fault * fault, Addr pc);
void intr_post(RegFile *regs, Fault fault, Addr pc);
// Actually used within exec files. Implement properly.
void swapPALShadow(bool use_shadow);
// Called by CPU constructor. Can implement as I please.
@ -211,7 +211,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
template <class T>
Fault * read(MemReqPtr &req, T &data)
Fault read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@ -221,20 +221,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
#endif
Fault * error;
Fault error;
error = this->mem->read(req, data);
data = gtoh(data);
return error;
}
template <class T>
Fault * read(MemReqPtr &req, T &data, int load_idx)
Fault read(MemReqPtr &req, T &data, int load_idx)
{
return this->iew.ldstQueue.read(req, data, load_idx);
}
template <class T>
Fault * write(MemReqPtr &req, T &data)
Fault write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@ -284,7 +284,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
template <class T>
Fault * write(MemReqPtr &req, T &data, int store_idx)
Fault write(MemReqPtr &req, T &data, int store_idx)
{
return this->iew.ldstQueue.write(req, data, store_idx);
}

8
cpu/o3/alpha_cpu_impl.hh
View file

@ -246,13 +246,13 @@ AlphaFullCPU<Impl>::getIpr()
template <class Impl>
uint64_t
AlphaFullCPU<Impl>::readIpr(int idx, Fault * &fault)
AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
{
return this->regFile.readIpr(idx, fault);
}
template <class Impl>
Fault *
Fault
AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
{
return this->regFile.setIpr(idx, val);
@ -274,7 +274,7 @@ AlphaFullCPU<Impl>::setIntrFlag(int val)
// Can force commit stage to squash and stuff.
template <class Impl>
Fault *
Fault
AlphaFullCPU<Impl>::hwrei()
{
uint64_t *ipr = getIpr();
@ -323,7 +323,7 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc)
// stage.
template <class Impl>
void
AlphaFullCPU<Impl>::trap(Fault * fault)
AlphaFullCPU<Impl>::trap(Fault fault)
{
// Keep in mind that a trap may be initiated by fetch if there's a TLB
// miss

14
cpu/o3/alpha_dyn_inst.hh
View file

@ -69,7 +69,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
AlphaDynInst(StaticInstPtr &_staticInst);
/** Executes the instruction.*/
Fault * execute()
Fault execute()
{
return this->fault = this->staticInst->execute(this, this->traceData);
}
@ -82,13 +82,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setFpcr(uint64_t val);
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault * &fault);
Fault * setIpr(int idx, uint64_t val);
Fault * hwrei();
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
Fault hwrei();
int readIntrFlag();
void setIntrFlag(int val);
bool inPalMode();
void trap(Fault * fault);
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
void syscall();
@ -215,12 +215,12 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
public:
Fault * calcEA()
Fault calcEA()
{
return this->staticInst->eaCompInst()->execute(this, this->traceData);
}
Fault * memAccess()
Fault memAccess()
{
return this->staticInst->memAccInst()->execute(this, this->traceData);
}

8
cpu/o3/alpha_dyn_inst_impl.hh
View file

@ -98,20 +98,20 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
#if FULL_SYSTEM
template <class Impl>
uint64_t
AlphaDynInst<Impl>::readIpr(int idx, Fault * &fault)
AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
{
return this->cpu->readIpr(idx, fault);
}
template <class Impl>
Fault *
Fault
AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
{
return this->cpu->setIpr(idx, val);
}
template <class Impl>
Fault *
Fault
AlphaDynInst<Impl>::hwrei()
{
return this->cpu->hwrei();
@ -140,7 +140,7 @@ AlphaDynInst<Impl>::inPalMode()
template <class Impl>
void
AlphaDynInst<Impl>::trap(Fault * fault)
AlphaDynInst<Impl>::trap(Fault fault)
{
this->cpu->trap(fault);
}

2
cpu/o3/commit_impl.hh
View file

@ -393,7 +393,7 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
}
// Check if the instruction caused a fault. If so, trap.
Fault * inst_fault = head_inst->getFault();
Fault inst_fault = head_inst->getFault();
if (inst_fault != NoFault) {
if (!head_inst->isNop()) {

2
cpu/o3/fetch.hh
View file

@ -122,7 +122,7 @@ class SimpleFetch
* @param fetch_PC The PC address that is being fetched from.
* @return Any fault that occured.
*/
Fault * fetchCacheLine(Addr fetch_PC);
Fault fetchCacheLine(Addr fetch_PC);
inline void doSquash(const Addr &new_PC);

6
cpu/o3/fetch_impl.hh
View file

@ -221,7 +221,7 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
}
template <class Impl>
Fault *
Fault
SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
{
// Check if the instruction exists within the cache.
@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
unsigned flags = 0;
#endif // FULL_SYSTEM
Fault * fault = NoFault;
Fault fault = NoFault;
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch()
Addr fetch_PC = cpu->readPC();
// Fault code for memory access.
Fault * fault = NoFault;
Fault fault = NoFault;
// If returning from the delay of a cache miss, then update the status
// to running, otherwise do the cache access. Possibly move this up

8
cpu/o3/regfile.hh
View file

@ -215,8 +215,8 @@ class PhysRegFile
}
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault * &fault);
Fault * setIpr(int idx, uint64_t val);
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
InternalProcReg *getIpr() { return ipr; }
int readIntrFlag() { return intrflag; }
void setIntrFlag(int val) { intrflag = val; }
@ -279,7 +279,7 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
//the DynInst level.
template <class Impl>
uint64_t
PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
{
uint64_t retval = 0; // return value, default 0
@ -387,7 +387,7 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
extern int break_ipl;
template <class Impl>
Fault *
Fault
PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
{
uint64_t old;

40
cpu/ozone/cpu.hh
View file

@ -285,17 +285,17 @@ class OoOCPU : public BaseCPU
int getInstAsid() { return xc->regs.instAsid(); }
int getDataAsid() { return xc->regs.dataAsid(); }
Fault * translateInstReq(MemReqPtr &req)
Fault translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
Fault * translateDataReadReq(MemReqPtr &req)
Fault translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
Fault * translateDataWriteReq(MemReqPtr &req)
Fault translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
@ -310,7 +310,7 @@ class OoOCPU : public BaseCPU
int getInstAsid() { return xc->asid; }
int getDataAsid() { return xc->asid; }
Fault * dummyTranslation(MemReqPtr &req)
Fault dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@ -321,15 +321,15 @@ class OoOCPU : public BaseCPU
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
return NoFault;
}
Fault * translateInstReq(MemReqPtr &req)
Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault * translateDataReadReq(MemReqPtr &req)
Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
Fault * translateDataWriteReq(MemReqPtr &req)
Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@ -337,10 +337,10 @@ class OoOCPU : public BaseCPU
#endif
template <class T>
Fault * read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
Fault read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
template <class T>
Fault * write(T data, Addr addr, unsigned flags,
Fault write(T data, Addr addr, unsigned flags,
uint64_t *res, DynInstPtr inst);
void prefetch(Addr addr, unsigned flags)
@ -353,9 +353,9 @@ class OoOCPU : public BaseCPU
// need to do this...
}
Fault * copySrcTranslate(Addr src);
Fault copySrcTranslate(Addr src);
Fault * copy(Addr dest);
Fault copy(Addr dest);
private:
bool executeInst(DynInstPtr &inst);
@ -368,7 +368,7 @@ class OoOCPU : public BaseCPU
bool getOneInst();
Fault * fetchCacheLine();
Fault fetchCacheLine();
InstSeqNum getAndIncrementInstSeq();
@ -511,13 +511,13 @@ class OoOCPU : public BaseCPU
void setFpcr(uint64_t val) { xc->setFpcr(val); }
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); }
Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault * hwrei() { return xc->hwrei(); }
uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault hwrei() { return xc->hwrei(); }
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
void ev5_trap(Fault * fault) { xc->ev5_trap(fault); }
void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }
@ -530,7 +530,7 @@ class OoOCPU : public BaseCPU
// precise architected memory state accessor macros
template <class Impl>
template <class T>
Fault *
Fault
OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
{
MemReqPtr readReq = new MemReq();
@ -541,7 +541,7 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
readReq->reset(addr, sizeof(T), flags);
// translate to physical address - This might be an ISA impl call
Fault * fault = translateDataReadReq(readReq);
Fault fault = translateDataReadReq(readReq);
// do functional access
if (fault == NoFault)
@ -575,7 +575,7 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
template <class Impl>
template <class T>
Fault *
Fault
OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
uint64_t *res, DynInstPtr inst)
{
@ -594,7 +594,7 @@ OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
writeReq->reset(addr, sizeof(T), flags);
// translate to physical address
Fault * fault = translateDataWriteReq(writeReq);
Fault fault = translateDataWriteReq(writeReq);
// do functional access
if (fault == NoFault)

48
cpu/simple/cpu.cc
View file

@ -312,7 +312,7 @@ change_thread_state(int thread_number, int activate, int priority)
{
}
Fault *
Fault
SimpleCPU::copySrcTranslate(Addr src)
{
static bool no_warn = true;
@ -332,7 +332,7 @@ SimpleCPU::copySrcTranslate(Addr src)
memReq->reset(src & ~(blk_size - 1), blk_size);
// translate to physical address
Fault * fault = xc->translateDataReadReq(memReq);
Fault fault = xc->translateDataReadReq(memReq);
assert(fault != AlignmentFault);
@ -346,7 +346,7 @@ SimpleCPU::copySrcTranslate(Addr src)
return fault;
}
Fault *
Fault
SimpleCPU::copy(Addr dest)
{
static bool no_warn = true;
@ -367,7 +367,7 @@ SimpleCPU::copy(Addr dest)
memReq->reset(dest & ~(blk_size -1), blk_size);
// translate to physical address
Fault * fault = xc->translateDataWriteReq(memReq);
Fault fault = xc->translateDataWriteReq(memReq);
assert(fault != AlignmentFault);
@ -394,11 +394,11 @@ SimpleCPU::copy(Addr dest)
// precise architected memory state accessor macros
template <class T>
Fault *
Fault
SimpleCPU::read(Addr addr, T &data, unsigned flags)
{
if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
Fault * fault = xc->read(memReq,data);
Fault fault = xc->read(memReq,data);
if (traceData) {
traceData->setAddr(addr);
@ -409,7 +409,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
Fault * fault = xc->translateDataReadReq(memReq);
Fault fault = xc->translateDataReadReq(memReq);
// if we have a cache, do cache access too
if (fault == NoFault && dcacheInterface) {
@ -447,32 +447,32 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
Fault *
Fault
SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
template
Fault *
Fault
SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
template
Fault *
Fault
SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
template
Fault *
Fault
SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
#endif //DOXYGEN_SHOULD_SKIP_THIS
template<>
Fault *
Fault
SimpleCPU::read(Addr addr, double &data, unsigned flags)
{
return read(addr, *(uint64_t*)&data, flags);
}
template<>
Fault *
Fault
SimpleCPU::read(Addr addr, float &data, unsigned flags)
{
return read(addr, *(uint32_t*)&data, flags);
@ -480,7 +480,7 @@ SimpleCPU::read(Addr addr, float &data, unsigned flags)
template<>
Fault *
Fault
SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
{
return read(addr, (uint32_t&)data, flags);
@ -488,13 +488,13 @@ SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
template <class T>
Fault *
Fault
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
memReq->reset(addr, sizeof(T), flags);
// translate to physical address
Fault * fault = xc->translateDataWriteReq(memReq);
Fault fault = xc->translateDataWriteReq(memReq);
// do functional access
if (fault == NoFault)
@ -531,32 +531,32 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
Fault *
Fault
SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
template
Fault *
Fault
SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
template
Fault *
Fault
SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
template
Fault *
Fault
SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
#endif //DOXYGEN_SHOULD_SKIP_THIS
template<>
Fault *
Fault
SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
{
return write(*(uint64_t*)&data, addr, flags, res);
}
template<>
Fault *
Fault
SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
{
return write(*(uint32_t*)&data, addr, flags, res);
@ -564,7 +564,7 @@ SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
template<>
Fault *
Fault
SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
{
return write((uint32_t)data, addr, flags, res);
@ -638,7 +638,7 @@ SimpleCPU::tick()
traceData = NULL;
Fault * fault = NoFault;
Fault fault = NoFault;
#if FULL_SYSTEM
if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&

16
cpu/simple/cpu.hh
View file

@ -236,10 +236,10 @@ class SimpleCPU : public BaseCPU
virtual void unserialize(Checkpoint *cp, const std::string &section);
template <class T>
Fault * read(Addr addr, T &data, unsigned flags);
Fault read(Addr addr, T &data, unsigned flags);
template <class T>
Fault * write(T data, Addr addr, unsigned flags, uint64_t *res);
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
@ -256,9 +256,9 @@ class SimpleCPU : public BaseCPU
// need to do this...
}
Fault * copySrcTranslate(Addr src);
Fault copySrcTranslate(Addr src);
Fault * copy(Addr dest);
Fault copy(Addr dest);
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural
@ -327,13 +327,13 @@ class SimpleCPU : public BaseCPU
void setFpcr(uint64_t val) { xc->setFpcr(val); }
#if FULL_SYSTEM
uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); }
Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault * hwrei() { return xc->hwrei(); }
uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
Fault hwrei() { return xc->hwrei(); }
int readIntrFlag() { return xc->readIntrFlag(); }
void setIntrFlag(int val) { xc->setIntrFlag(val); }
bool inPalMode() { return xc->inPalMode(); }
void ev5_trap(Fault * fault) { xc->ev5_trap(fault); }
void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
#else
void syscall() { xc->syscall(); }

4
dev/alpha_console.cc
View file

@ -100,7 +100,7 @@ AlphaConsole::startup()
alphaAccess->intrClockFrequency = platform->intrFrequency();
}
Fault *
Fault
AlphaConsole::read(MemReqPtr &req, uint8_t *data)
{
memset(data, 0, req->size);
@ -190,7 +190,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
Fault *
Fault
AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
{
uint64_t val;

4
dev/alpha_console.hh
View file

@ -110,8 +110,8 @@ class AlphaConsole : public PioDevice
/**
* memory mapped reads and writes
*/
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* standard serialization routines for checkpointing

4
dev/baddev.cc
View file

@ -62,7 +62,7 @@ BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
}
Fault *
Fault
BadDevice::read(MemReqPtr &req, uint8_t *data)
{
@ -70,7 +70,7 @@ BadDevice::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
Fault *
Fault
BadDevice::write(MemReqPtr &req, const uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);

4
dev/baddev.hh
View file

@ -71,7 +71,7 @@ class BadDevice : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* On a write event we just panic aand hopefully print a
@ -80,7 +80,7 @@ class BadDevice : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Return how long this access will take.

4
dev/ide_ctrl.cc
View file

@ -391,7 +391,7 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data)
}
}
Fault *
Fault
IdeController::read(MemReqPtr &req, uint8_t *data)
{
Addr offset;
@ -461,7 +461,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
Fault *
Fault
IdeController::write(MemReqPtr &req, const uint8_t *data)
{
Addr offset;

4
dev/ide_ctrl.hh
View file

@ -213,7 +213,7 @@ class IdeController : public PciDev
* @param data Return the field read.
* @return The fault condition of the access.
*/
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* Write to the mmapped I/O control registers.
@ -221,7 +221,7 @@ class IdeController : public PciDev
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Serialize this object to the given output stream.

4
dev/isa_fake.cc
View file

@ -60,7 +60,7 @@ IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
}
}
Fault *
Fault
IsaFake::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
@ -93,7 +93,7 @@ IsaFake::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
Fault *
Fault
IsaFake::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",

4
dev/isa_fake.hh
View file

@ -65,14 +65,14 @@ class IsaFake : public PioDevice
* @param req The memory request.
* @param data Where to put the data.
*/
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* All writes are simply ignored.
* @param req The memory request.
* @param data the data to not write.
*/
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Return how long this access will take.

4
dev/ns_gige.cc
View file

@ -557,7 +557,7 @@ NSGigE::writeConfig(int offset, int size, const uint8_t* data)
* This reads the device registers, which are detailed in the NS83820
* spec sheet
*/
Fault *
Fault
NSGigE::read(MemReqPtr &req, uint8_t *data)
{
assert(ioEnable);
@ -786,7 +786,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
Fault *
Fault
NSGigE::write(MemReqPtr &req, const uint8_t *data)
{
assert(ioEnable);

4
dev/ns_gige.hh
View file

@ -395,8 +395,8 @@ class NSGigE : public PciDev
virtual void writeConfig(int offset, int size, const uint8_t *data);
virtual void readConfig(int offset, int size, uint8_t *data);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }

4
dev/pciconfigall.cc
View file

@ -96,7 +96,7 @@ PciConfigAll::startup()
}
Fault *
Fault
PciConfigAll::read(MemReqPtr &req, uint8_t *data)
{
@ -144,7 +144,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
Fault *
Fault
PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));

4
dev/pciconfigall.hh
View file

@ -103,7 +103,7 @@ class PciConfigAll : public PioDevice
* @param data Return the field read.
* @return The fault condition of the access.
*/
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* Write to PCI config spcae. If the device does not exit the simulator
@ -114,7 +114,7 @@ class PciConfigAll : public PioDevice
* @return The fault condition of the access.
*/
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Start up function to check if more than one person is using an interrupt line

28
dev/pcidev.cc
View file

@ -70,59 +70,59 @@ PciDev::PciDev(Params *p)
p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
}
Fault *
Fault
PciDev::read(MemReqPtr &req, uint8_t *data)
{ return NoFault; }
Fault *
Fault
PciDev::write(MemReqPtr &req, const uint8_t *data)
{ return NoFault; }
Fault *
Fault
PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
Fault *
Fault
PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }

36
dev/pcidev.hh
View file

@ -189,37 +189,37 @@ class PciDev : public DmaDevice
*/
PciDev(Params *params);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
public:
/**
* Implement the read/write as BAR accesses
*/
Fault * readBar(MemReqPtr &req, uint8_t *data);
Fault * writeBar(MemReqPtr &req, const uint8_t *data);
Fault readBar(MemReqPtr &req, uint8_t *data);
Fault writeBar(MemReqPtr &req, const uint8_t *data);
public:
/**
* Read from a specific BAR
*/
virtual Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault * readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
public:
/**
* Write to a specific BAR
*/
virtual Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault * writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
public:
/**
@ -257,7 +257,7 @@ class PciDev : public DmaDevice
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
inline Fault *
inline Fault
PciDev::readBar(MemReqPtr &req, uint8_t *data)
{
if (isBAR(req->paddr, 0))
@ -275,7 +275,7 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
return MachineCheckFault;
}
inline Fault *
inline Fault
PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
{
if (isBAR(req->paddr, 0))

14
dev/sinic.cc
View file

@ -357,11 +357,11 @@ Device::prepareWrite(int cpu, int index)
/**
* I/O read of device register
*/
Fault *
Fault
Device::read(MemReqPtr &req, uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
Fault * fault = readBar(req, data);
Fault fault = readBar(req, data);
if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
@ -373,7 +373,7 @@ Device::read(MemReqPtr &req, uint8_t *data)
return fault;
}
Fault *
Fault
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
@ -423,7 +423,7 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
/**
* IPR read of device register
*/
Fault *
Fault
Device::iprRead(Addr daddr, int cpu, uint64_t &result)
{
if (!regValid(daddr))
@ -453,11 +453,11 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result)
/**
* I/O write of device register
*/
Fault *
Fault
Device::write(MemReqPtr &req, const uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
Fault * fault = writeBar(req, data);
Fault fault = writeBar(req, data);
if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
@ -469,7 +469,7 @@ Device::write(MemReqPtr &req, const uint8_t *data)
return fault;
}
Fault *
Fault
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;

10
dev/sinic.hh
View file

@ -271,15 +271,15 @@ class Device : public Base
* Memory Interface
*/
public:
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
void prepareIO(int cpu, int index);
void prepareRead(int cpu, int index);
void prepareWrite(int cpu, int index);
Fault * iprRead(Addr daddr, int cpu, uint64_t &result);
Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
Fault iprRead(Addr daddr, int cpu, uint64_t &result);
Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);

4
dev/tsunami_cchip.cc
View file

@ -78,7 +78,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
tsunami->cchip = this;
}
Fault *
Fault
TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
@ -192,7 +192,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
Fault *
Fault
TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",

4
dev/tsunami_cchip.hh
View file

@ -105,7 +105,7 @@ class TsunamiCChip : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
@ -114,7 +114,7 @@ class TsunamiCChip : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* post an RTC interrupt to the CPU

4
dev/tsunami_io.cc
View file

@ -446,7 +446,7 @@ TsunamiIO::frequency() const
return Clock::Frequency / clockInterval;
}
Fault *
Fault
TsunamiIO::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
@ -523,7 +523,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
Fault *
Fault
TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
{

4
dev/tsunami_io.hh
View file

@ -330,7 +330,7 @@ class TsunamiIO : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* Process a write to one of the devices we emulate.
@ -338,7 +338,7 @@ class TsunamiIO : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Post an PIC interrupt to the CPU via the CChip

4
dev/tsunami_pchip.cc
View file

@ -78,7 +78,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
tsunami->pchip = this;
}
Fault *
Fault
TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
@ -167,7 +167,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
Fault *
Fault
TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",

4
dev/tsunami_pchip.hh
View file

@ -99,7 +99,7 @@ class TsunamiPChip : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* Process a write to the PChip.
@ -107,7 +107,7 @@ class TsunamiPChip : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Serialize this object to the given output stream.

4
dev/uart.hh
View file

@ -57,8 +57,8 @@ class Uart : public PioDevice
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
Platform *p);
virtual Fault * read(MemReqPtr &req, uint8_t *data) = 0;
virtual Fault * write(MemReqPtr &req, const uint8_t *data) = 0;
virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
/**

4
dev/uart8250.cc
View file

@ -112,7 +112,7 @@ Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
}
Fault *
Fault
Uart8250::read(MemReqPtr &req, uint8_t *data)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@ -188,7 +188,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
}
Fault *
Fault
Uart8250::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);

4
dev/uart8250.hh
View file

@ -82,8 +82,8 @@ class Uart8250 : public Uart
Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
Platform *p);
virtual Fault * read(MemReqPtr &req, uint8_t *data);
virtual Fault * write(MemReqPtr &req, const uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**

3
kern/kernel_stats.hh
View file

@ -41,7 +41,6 @@ class ExecContext;
class FnEvent;
// What does kernel stats expect is included?
class System;
class Fault;
namespace Kernel {
@ -177,7 +176,7 @@ class Statistics : public Serializable
void ivlb() { _ivlb++; }
void ivle() { _ivle++; }
void hwrei() { _hwrei++; }
void fault(Fault * fault)
void fault(Fault fault)
{
if(fault == NoFault) _faults[0]++;
else if(fault == MachineCheckFault) _faults[2]++;

19
sim/faults.hh
View file

@ -29,30 +29,33 @@
#ifndef __FAULTS_HH__
#define __FAULTS_HH__
class Fault
class FaultBase;
typedef FaultBase * Fault;
class FaultBase
{
public:
Fault(char * newName, int newId = 0) : name(newName), id(newId) {;}
FaultBase(char * newName, int newId = 0) : name(newName), id(newId) {;}
const char * name;
int id;
};
extern class NoFaultType : public Fault
extern class NoFaultType : public FaultBase
{
public:
NoFaultType(char * newName) : Fault(newName) {;}
NoFaultType(char * newName) : FaultBase(newName) {;}
} * const NoFault;
extern class MachineCheckFaultType : public Fault
extern class MachineCheckFaultType : public FaultBase
{
public:
MachineCheckFaultType(char * newName) : Fault(newName) {;}
MachineCheckFaultType(char * newName) : FaultBase(newName) {;}
} * const MachineCheckFault;
extern class AlignmentFaultType : public Fault
extern class AlignmentFaultType : public FaultBase
{
public:
AlignmentFaultType(char * newName) : Fault(newName) {;}
AlignmentFaultType(char * newName) : FaultBase(newName) {;}
} * const AlignmentFault;