gem5/arch
Korey Sewell 19534176e0 load/store instruction format ... now generates load/store code
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.

arch/mips/isa/bitfields.isa:
    comment change
arch/mips/isa/decoder.isa:
    re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
    Define LoadMemory & Store Memory formats
    Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
    Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
    change shw->sh and uhw->uh

--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
2006-02-20 14:30:23 -05:00
..
alpha Reapplied changes which were undone by a pull 2006-02-19 04:00:05 -05:00
mips load/store instruction format ... now generates load/store code 2006-02-20 14:30:23 -05:00
sparc New files to fix building the SPARC_SE and MIPS_SE isa_parser.py generated files. 2006-02-14 20:13:08 -05:00
isa_parser.py Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 2006-02-19 03:20:05 -05:00
isa_specific.hh Changed the isa from a class to a namespace, untemplated StaticInst and StaticInstPtr, converted things to using TheISA, cleaned up some header file paths, and improved the system which pulls header files from the appropriate architecture. 2006-02-18 20:58:08 -05:00