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Fixes for detailed boot, made cttz and ctlz instructions more compact,

Browse source 
and started cleaning up config files.

arch/alpha/isa_desc:
    Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
    Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
    Cleaned up includes and changed device from FunctionalMemory to
    PioDevice for detailed boot
dev/ns_gige.cc:
    The ethernet dev uses two BARs, and the first bars size was being set
    incorrectly.
dev/tsunamireg.h:
    I don't know why we were using the superpage as the PCI memory addr.
    Changed and works correctly with detailed boot.

--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
This commit is contained in:
Ali Saidi 2004-06-10 13:30:58 -04:00
parent a20f44979a
commit 02f69b94c5
18 changed files with 247 additions and 130 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

81
arch/alpha/isa_desc
View file

@ -2119,65 +2119,30 @@ decode OPCODE default Unknown::unknown() {
0x1c: decode INTFUNC {
0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
0x32: ctlz({{
uint64_t count = 0;
uint64_t temp = Rb;
if (temp & ULL(0xffffffff00000000))
temp >>= 32;
else
count += 32;
if (temp & ULL(0xffff0000))
temp >>= 16;
else
count += 16;
if (temp & ULL(0xff00))
temp >>= 8;
else
count += 8;
if (temp & ULL(0xf0))
temp >>= 4;
else
count += 4;
if (temp & ULL(0xC))
temp >>= 2;
else
count += 2;
if (temp & ULL(0x2))
temp >>= 1;
else
count += 1;
if ((temp & ULL(0x1)) != 0x1)
count += 1;
Rc = count;
}}, IntAluOp);
0x32: ctlz({{
uint64_t count = 0;
uint64_t temp = Rb;
if (temp<63:32>) temp >>= 32; else count += 32;
if (temp<31:16>) temp >>= 16; else count += 16;
if (temp<15:8>) temp >>= 8; else count += 8;
if (temp<7:4>) temp >>= 4; else count += 4;
if (temp<3:2>) temp >>= 2; else count += 2;
if (temp<1:1>) temp >>= 1; else count += 1;
if ((temp<0:0>) != 0x1) count += 1;
Rc = count;
}}, IntAluOp);
0x33: cttz({{
uint64_t count = 0;
uint64_t temp = Rb;
if (!(temp & ULL(0x00000000ffffffff))) {
temp >>= 32;
count += 32;
}
if (!(temp & ULL(0x0000ffff))) {
temp >>= 16;
count += 16;
}
if (!(temp & ULL(0x00ff))) {
temp >>= 8;
count += 8;
}
if (!(temp & ULL(0x0f))) {
temp >>= 4;
count += 4;
}
if (!(temp & ULL(0x3))) {
temp >>= 2;
count += 2;
}
if (!(temp & ULL(0x1)))
count += 1;
Rc = count;
}}, IntAluOp);
0x33: cttz({{
uint64_t count = 0;
uint64_t temp = Rb;
if (!(temp<31:0>)) { temp >>= 32; count += 32; }
if (!(temp<15:0>)) { temp >>= 16; count += 16; }
if (!(temp<7:0>)) { temp >>= 8; count += 8; }
if (!(temp<3:0>)) { temp >>= 4; count += 4; }
if (!(temp<1:0>)) { temp >>= 2; count += 2; }
if (!(temp<0:0> & ULL(0x1))) count += 1;
Rc = count;
}}, IntAluOp);
format FailUnimpl {
0x30: ctpop();

7
base/remote_gdb.cc
View file

@ -344,6 +344,13 @@ RemoteGDB::acc(Addr va, size_t len)
}
}
/**
* This code says that all accesses to palcode (instruction and data)
* are valid since there isn't a va->pa mapping because palcode is
* accessed physically. At some point this should probably be cleaned up
* but there is no easy way to do it.
*/
if (PC_PAL(va) || va < 0x10000)
return true;

28
dev/baddev.cc
View file

@ -36,10 +36,10 @@
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "dev/scsi_ctrl.hh"
#include "dev/baddev.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional_mem/memory_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
@ -47,10 +47,17 @@
using namespace std;
BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
const string &devicename)
: FunctionalMemory(name), addr(a), devname(devicename)
HierParams *hier, Bus *bus, const string &devicename)
: PioDevice(name), addr(a), devname(devicename)
{
mmu->add_child(this, Range<Addr>(addr, addr + size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&BadDevice::cacheAccess);
pioInterface->addAddrRange(addr, addr + size - 1);
}
}
Fault
@ -68,11 +75,18 @@ BadDevice::write(MemReqPtr &req, const uint8_t *data)
return No_Fault;
}
Tick
BadDevice::cacheAccess(MemReqPtr &req)
{
return curTick + 1000;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<HierParams *> hier;
SimObjectParam<Bus*> io_bus;
Param<string> devicename;
END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
@ -81,13 +95,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM(devicename, "Name of device to error on")
END_INIT_SIM_OBJECT_PARAMS(BadDevice)
CREATE_SIM_OBJECT(BadDevice)
{
return new BadDevice(getInstanceName(), addr, mmu, devicename);
return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus, devicename);
}
REGISTER_SIM_OBJECT("BadDevice", BadDevice)

16
dev/baddev.hh
View file

@ -34,7 +34,8 @@
#ifndef __BADDEV_HH__
#define __BADDEV_HH__
#include "mem/functional_mem/functional_memory.hh"
#include "base/range.hh"
#include "dev/io_device.hh"
/**
* BadDevice
@ -42,7 +43,7 @@
* the user that the kernel they are running has unsupported
* options (i.e. frame buffer)
*/
class BadDevice : public FunctionalMemory
class BadDevice : public PioDevice
{
private:
Addr addr;
@ -56,10 +57,12 @@ class BadDevice : public FunctionalMemory
* @param name name of the object
* @param a base address of the write
* @param mmu the memory controller
* @param hier object to store parameters universal the device hierarchy
* @param bus The bus that this device is attached to
* @param devicename device that is not implemented
*/
BadDevice(const std::string &name, Addr a, MemoryController *mmu,
const std::string &devicename);
HierParams *hier, Bus *bus, const std::string &devicename);
/**
* On a read event we just panic aand hopefully print a
@ -79,7 +82,12 @@ class BadDevice : public FunctionalMemory
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/** @todo add serialize/unserialize */
/**
* Return how long this access will take.
* @param req the memory request to calcuate
* @return Tick when the request is done
*/
Tick cacheAccess(MemReqPtr &req);
};
#endif // __BADDEV_HH__

6
dev/ide_ctrl.cc
View file

@ -668,7 +668,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
SimObjectParam<Bus *> host_bus;
SimObjectParam<Bus *> io_bus;
SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
@ -684,7 +684,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(host_bus, "Host bus to attach to", NULL),
INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(IdeController)
@ -693,7 +693,7 @@ CREATE_SIM_OBJECT(IdeController)
{
return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
configspace, configdata, tsunami, pci_bus,
pci_dev, pci_func, host_bus, hier);
pci_dev, pci_func, io_bus, hier);
}
REGISTER_SIM_OBJECT("IdeController", IdeController)

12
dev/ide_ctrl.hh
View file

@ -198,12 +198,6 @@ class IdeController : public PciDev
*/
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Cache access timing specific to device
* @param req Memory request
*/
Tick cacheAccess(MemReqPtr &req);
/**
* Serialize this object to the given output stream.
* @param os The stream to serialize to.
@ -217,5 +211,11 @@ class IdeController : public PciDev
*/
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Return how long this access will take.
* @param req the memory request to calcuate
* @return Tick when the request is done
*/
Tick cacheAccess(MemReqPtr &req);
};
#endif // __IDE_CTRL_HH_

20
dev/ns_gige.cc
View file

@ -131,8 +131,8 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
pioInterface = newPioInterface(name, hier, payload_bus, this,
&NSGigE::cacheAccess);
dmaInterface = new DMAInterface<Bus>(name + ".dma",
payload_bus, payload_bus, 1);
dmaInterface = new DMAInterface<Bus>(name + ".dma", payload_bus,
payload_bus, 1);
}
@ -244,12 +244,22 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
switch (offset) {
case PCI0_BASE_ADDR0:
if (BARAddrs[0] != 0) {
addr = BARAddrs[0];
if (pioInterface)
pioInterface->addAddrRange(addr, addr + size - 1);
pioInterface->addAddrRange(BARAddrs[0], BARAddrs[0] + BARSize[0] - 1);
BARAddrs[0] &= PA_UNCACHED_MASK;
}
break;
case PCI0_BASE_ADDR1:
if (BARAddrs[1] != 0) {
if (pioInterface)
pioInterface->addAddrRange(BARAddrs[1], BARAddrs[1] + BARSize[1] - 1);
BARAddrs[1] &= PA_UNCACHED_MASK;
addr &= PA_UNCACHED_MASK;
}
break;
}

31
dev/pciconfigall.cc
View file

@ -35,22 +35,29 @@
#include <vector>
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "dev/scsi_ctrl.hh"
#include "dev/pciconfigall.hh"
#include "dev/pcidev.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional_mem/memory_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
PciConfigAll::PciConfigAll(const string &name, Addr a,
MemoryController *mmu)
: FunctionalMemory(name), addr(a)
PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus)
: PioDevice(name), addr(a)
{
mmu->add_child(this, Range<Addr>(addr, addr + size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&PciConfigAll::cacheAccess);
pioInterface->addAddrRange(addr, addr + size - 1);
}
// Make all the pointers to devices null
for(int x=0; x < MAX_PCI_DEV; x++)
for(int y=0; y < MAX_PCI_FUNC; y++)
@ -165,6 +172,12 @@ PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
*/
}
Tick
PciConfigAll::cacheAccess(MemReqPtr &req)
{
return curTick + 1000;
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
@ -172,6 +185,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
Param<Addr> mask;
SimObjectParam<Bus*> io_bus;
SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
@ -179,13 +194,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(mask, "Address Mask")
INIT_PARAM(mask, "Address Mask"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
CREATE_SIM_OBJECT(PciConfigAll)
{
return new PciConfigAll(getInstanceName(), addr, mmu);
return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus);
}
REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)

17
dev/pciconfigall.hh
View file

@ -34,8 +34,10 @@
#ifndef __PCICONFIGALL_HH__
#define __PCICONFIGALL_HH__
#include "mem/functional_mem/functional_memory.hh"
#include "dev/pcireg.h"
#include "base/range.hh"
#include "dev/io_device.hh"
static const uint32_t MAX_PCI_DEV = 32;
static const uint32_t MAX_PCI_FUNC = 8;
@ -49,7 +51,7 @@ class PciDev;
* space and passes the requests on to TsunamiPCIDev devices as
* appropriate.
*/
class PciConfigAll : public FunctionalMemory
class PciConfigAll : public PioDevice
{
private:
Addr addr;
@ -67,8 +69,11 @@ class PciConfigAll : public FunctionalMemory
* @param name name of the object
* @param a base address of the write
* @param mmu the memory controller
* @param hier object to store parameters universal the device hierarchy
* @param bus The bus that this device is attached to
*/
PciConfigAll(const std::string &name, Addr a, MemoryController *mmu);
PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus);
/**
@ -123,6 +128,12 @@ class PciConfigAll : public FunctionalMemory
*/
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Return how long this access will take.
* @param req the memory request to calcuate
* @return Tick when the request is done
*/
Tick cacheAccess(MemReqPtr &req);
};
#endif // __PCICONFIGALL_HH__

31
dev/tsunami_cchip.cc
View file

@ -35,21 +35,23 @@
#include <vector>
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "dev/console.hh"
#include "dev/tsunami_cchip.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "cpu/intr_control.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional_mem/memory_control.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu)
: FunctionalMemory(name), addr(a), tsunami(t)
MemoryController *mmu, HierParams *hier, Bus* bus)
: PioDevice(name), addr(a), tsunami(t)
{
mmu->add_child(this, Range<Addr>(addr, addr + size));
@ -61,6 +63,12 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
RTCInterrupting[i] = false;
}
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiCChip::cacheAccess);
pioInterface->addAddrRange(addr, addr + size - 1);
}
drir = 0;
misc = 0;
@ -373,6 +381,13 @@ TsunamiCChip::clearDRIR(uint32_t interrupt)
DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
}
Tick
TsunamiCChip::cacheAccess(MemReqPtr &req)
{
return curTick + 1000;
}
void
TsunamiCChip::serialize(std::ostream &os)
{
@ -402,6 +417,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
SimObjectParam<Tsunami *> tsunami;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<Bus*> io_bus;
SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
@ -409,13 +426,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
INIT_PARAM(tsunami, "Tsunami"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address")
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
CREATE_SIM_OBJECT(TsunamiCChip)
{
return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu);
return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus);
}
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)

16
dev/tsunami_cchip.hh
View file

@ -33,13 +33,14 @@
#ifndef __TSUNAMI_CCHIP_HH__
#define __TSUNAMI_CCHIP_HH__
#include "mem/functional_mem/functional_memory.hh"
#include "dev/tsunami.hh"
#include "base/range.hh"
#include "dev/io_device.hh"
/*
* Tsunami CChip
*/
class TsunamiCChip : public FunctionalMemory
class TsunamiCChip : public PioDevice
{
private:
/** The base address of this device */
@ -95,9 +96,11 @@ class TsunamiCChip : public FunctionalMemory
* @param t pointer back to the Tsunami object that we belong to.
* @param a address we are mapped at.
* @param mmu pointer to the memory controller that sends us events.
* @param hier object to store parameters universal the device hierarchy
* @param bus The bus that this device is attached to
*/
TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
MemoryController *mmu);
MemoryController *mmu, HierParams *hier, Bus *bus);
/**
* Process a read to the CChip.
@ -145,6 +148,13 @@ class TsunamiCChip : public FunctionalMemory
* @param section The section name of this object
*/
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Return how long this access will take.
* @param req the memory request to calcuate
* @return Tick when the request is done
*/
Tick cacheAccess(MemReqPtr &req);
};
#endif // __TSUNAMI_CCHIP_HH__

34
dev/tsunami_io.cc
View file

@ -37,15 +37,16 @@
#include <vector>
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "dev/console.hh"
#include "dev/tlaser_clock.hh"
#include "dev/tsunami_io.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/functional_mem/memory_control.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "sim/builder.hh"
#include "dev/tsunami_cchip.hh"
#include "dev/tsunamireg.h"
#include "mem/functional_mem/memory_control.hh"
using namespace std;
@ -122,11 +123,17 @@ TsunamiIO::ClockEvent::Status()
}
TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
Addr a, MemoryController *mmu)
: FunctionalMemory(name), addr(a), tsunami(t), rtc(t)
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus)
: PioDevice(name), addr(a), tsunami(t), rtc(t)
{
mmu->add_child(this, Range<Addr>(addr, addr + size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiIO::cacheAccess);
pioInterface->addAddrRange(addr, addr + size - 1);
}
// set the back pointer from tsunami to myself
tsunami->io = this;
@ -375,6 +382,12 @@ TsunamiIO::clearPIC(uint8_t bitvector)
}
}
Tick
TsunamiIO::cacheAccess(MemReqPtr &req)
{
return curTick + 1000;
}
void
TsunamiIO::serialize(std::ostream &os)
{
@ -425,6 +438,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
Param<time_t> time;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<Bus*> io_bus;
SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
@ -434,13 +449,16 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
INIT_PARAM_DFLT(time, "System time to use "
"(0 for actual time, default is 1/1/06", ULL(1136073600)),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address")
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
CREATE_SIM_OBJECT(TsunamiIO)
{
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu);
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu, hier,
io_bus);
}
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)

11
dev/tsunami_io.hh
View file

@ -33,7 +33,8 @@
#ifndef __TSUNAMI_DMA_HH__
#define __TSUNAMI_DMA_HH__
#include "mem/functional_mem/functional_memory.hh"
#include "dev/io_device.hh"
#include "base/range.hh"
#include "dev/tsunami.hh"
/** How often the RTC interrupts */
@ -43,7 +44,7 @@ static const int RTC_RATE = 1024;
* Tsunami I/O device is a catch all for all the south bridge stuff we care
* to implement.
*/
class TsunamiIO : public FunctionalMemory
class TsunamiIO : public PioDevice
{
private:
/** The base address of this device */
@ -134,6 +135,7 @@ class TsunamiIO : public FunctionalMemory
* @return a description
*/
virtual const char *description();
};
/** uip UpdateInProgess says that the rtc is updating, but we just fake it
@ -208,7 +210,7 @@ class TsunamiIO : public FunctionalMemory
* @param mmu pointer to the memory controller that sends us events.
*/
TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
Addr a, MemoryController *mmu);
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus);
/**
* Create the tm struct from seconds since 1970
@ -256,6 +258,9 @@ class TsunamiIO : public FunctionalMemory
* @param section The section name of this object
*/
virtual void unserialize(Checkpoint *cp, const std::string &section);
Tick cacheAccess(MemReqPtr &req);
};
#endif // __TSUNAMI_IO_HH__

34
dev/tsunami_pchip.cc
View file

@ -35,14 +35,12 @@
#include <vector>
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "dev/console.hh"
#include "dev/etherdev.hh"
#include "dev/scsi_ctrl.hh"
#include "dev/tlaser_clock.hh"
#include "dev/tsunami_pchip.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional_mem/memory_control.hh"
#include "mem/functional_mem/physical_memory.hh"
#include "sim/builder.hh"
@ -51,8 +49,9 @@
using namespace std;
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu)
: FunctionalMemory(name), addr(a), tsunami(t)
MemoryController *mmu, HierParams *hier,
Bus *bus)
: PioDevice(name), addr(a), tsunami(t)
{
mmu->add_child(this, Range<Addr>(addr, addr + size));
@ -62,6 +61,13 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
tba[i] = 0;
}
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiPChip::cacheAccess);
pioInterface->addAddrRange(addr, addr + size - 1);
}
// initialize pchip control register
pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
@ -342,11 +348,19 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_ARRAY(tba, 4);
}
Tick
TsunamiPChip::cacheAccess(MemReqPtr &req)
{
return curTick + 1000;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
SimObjectParam<Tsunami *> tsunami;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<Bus*> io_bus;
SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
@ -354,13 +368,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
INIT_PARAM(tsunami, "Tsunami"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address")
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
CREATE_SIM_OBJECT(TsunamiPChip)
{
return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu);
return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier, io_bus);
}
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)

16
dev/tsunami_pchip.hh
View file

@ -33,13 +33,14 @@
#ifndef __TSUNAMI_PCHIP_HH__
#define __TSUNAMI_PCHIP_HH__
#include "mem/functional_mem/functional_memory.hh"
#include "dev/tsunami.hh"
#include "base/range.hh"
#include "dev/io_device.hh"
/*
* Tsunami PChip
*/
class TsunamiPChip : public FunctionalMemory
class TsunamiPChip : public PioDevice
{
private:
/** The base address of this device */
@ -75,9 +76,11 @@ class TsunamiPChip : public FunctionalMemory
* @param t a pointer to the tsunami device
* @param a the address which we respond to
* @param mmu the mmu we are to register with
* @param hier object to store parameters universal the device hierarchy
* @param bus The bus that this device is attached to
*/
TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
MemoryController *mmu);
MemoryController *mmu, HierParams *hier, Bus *bus);
/**
* Translate a PCI bus address to a memory address for DMA.
@ -115,6 +118,13 @@ class TsunamiPChip : public FunctionalMemory
* @param section The section name of this object
*/
virtual void unserialize(Checkpoint *cp, const std::string &section);
/**
* Return how long this access will take.
* @param req the memory request to calcuate
* @return Tick when the request is done
*/
Tick cacheAccess(MemReqPtr &req);
};
#endif // __TSUNAMI_PCHIP_HH__

2
dev/tsunami_uart.cc
View file

@ -82,7 +82,7 @@ TsunamiUart::TsunamiUart(const string &name, SimConsole *c,
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiUart::cacheAccess);
pioInterface->addAddrRange(addr, addr + size - 1);
pioInterface->addAddrRange(addr, addr + size - 1);
}
IER = 0;

6
dev/tsunami_uart.hh
View file

@ -80,7 +80,11 @@ class TsunamiUart : public PioDevice
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
public:
/**
* Return how long this access will take.
* @param req the memory request to calcuate
* @return Tick when the request is done
*/
Tick cacheAccess(MemReqPtr &req);
};

9
dev/tsunamireg.h
View file

@ -132,10 +132,11 @@
#define RTC_CONTROL_REGISTERD 13 // control register D
#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
#define PCHIP_PCI0_MEMORY ULL(0x10000000000)
#define PCHIP_PCI0_IO ULL(0x101FC000000)
#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY
#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO
#define PCHIP_PCI0_MEMORY ULL(0x00000000000)
#define PCHIP_PCI0_IO ULL(0x001FC000000)
#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000)
#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY
#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
// UART Defines