Commit graph

4977 commits

Author SHA1 Message Date
Joel Hestness
d50aec8d9a Ruby: remove unused functions in CacheMemory: get/setMemoryValue 2011-06-24 15:47:35 -05:00
Deyaun Guo
5aaddc129e mips: fix nmsub and nmadd definitions
the -/+ signs were flipped for nmsub_s, nmsub_d, and nmadd_d
2011-06-22 23:35:21 -04:00
Gabe Black
efb9f7c2ae X86: Eliminate an unused argument for building store microops. 2011-06-21 19:28:14 -07:00
Gabe Black
affad29932 InOder: Fix a compile error. 2011-06-20 02:29:14 -07:00
Korey Sewell
477e7039b3 inorder: clear reg. dep entry after removing from list
this will safeguard future code from trying to remove
from the list twice. That code wouldnt break but would
waste time.
2011-06-19 21:43:42 -04:00
Korey Sewell
b963b339b9 inorder: se: squash after syscalls 2011-06-19 21:43:42 -04:00
Korey Sewell
eedd04e894 inorder: cleanup dprintfs in cache unit 2011-06-19 21:43:42 -04:00
Korey Sewell
078f914e69 inorder: SE mode TLB faults
handle them like we do in FS mode, by blocking the TLB until the fault
is handled by the fault->invoke()
2011-06-19 21:43:42 -04:00
Korey Sewell
3cb23bd3a2 inorder:tracing: fix fault tracing bug 2011-06-19 21:43:42 -04:00
Korey Sewell
fe3a2aa4a3 inorder: se compile fixes 2011-06-19 21:43:42 -04:00
Korey Sewell
e572c01120 inorder: add necessary debug flag header files 2011-06-19 21:43:41 -04:00
Korey Sewell
59686795e3 mips: mark unaligned access flag as true 2011-06-19 21:43:41 -04:00
Korey Sewell
91a88ae8ce inorder: clear fetchbuffer on traps
implement clearfetchbufferfunction
extend predecoder to use multiple threads and clear those on trap
2011-06-19 21:43:41 -04:00
Korey Sewell
2dae0e8735 inorder: use separate float-reg bits function in dyninst
this will make sure we get the correct view of a FP register
2011-06-19 21:43:41 -04:00
Korey Sewell
8c0def8d03 inorder: use trapPending flag to manage traps 2011-06-19 21:43:41 -04:00
Korey Sewell
5ef0b7a9db inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
2011-06-19 21:43:41 -04:00
Korey Sewell
716e447da8 inorder: handle serializing instructions
including IPR accesses and store-conditionals. These class of instructions will not
execute correctly in a superscalar machine
2011-06-19 21:43:41 -04:00
Korey Sewell
83a0fd24f7 alpha: fix warn_once for prefetches 2011-06-19 21:43:40 -04:00
Korey Sewell
33a6020f2e alpha: naming for dtb faults
Just "dfault" gets confusing while debugging. Why not
differentiate whether it's an access violation or page
fault
2011-06-19 21:43:40 -04:00
Korey Sewell
561c33f082 inorder: dont handle multiple faults on same cycle
if a faulting instruction reaches an execution unit,
then ignore it and pass it through the pipeline.

Once we recognize the fault in the graduation unit,
dont allow a second fault to creep in on the same cycle.
2011-06-19 21:43:40 -04:00
Korey Sewell
c4deabfb97 inorder: register ports for FS mode
handle "snoop" port registration as well as functional
port setup for FS mode
2011-06-19 21:43:40 -04:00
Korey Sewell
f1c3691356 inorder: check for interrupts each tick
use a dummy instruction to facilitate the squash after
the interrupts trap
2011-06-19 21:43:40 -04:00
Korey Sewell
0bfdf342da inorder: explicit fault check
Before graduating an instruction, explicitly check fault
by making the fault check it's own separate command
that can be put on an instruction schedule.
2011-06-19 21:43:40 -04:00
Korey Sewell
5f608dd2e9 inorder: squash and trap behind a tlb fault 2011-06-19 21:43:39 -04:00
Korey Sewell
e0e387c2a9 inorder: stall stores on store conditionals & compare/swaps 2011-06-19 21:43:39 -04:00
Korey Sewell
f268d7d004 alpha: make hwrei a control inst
this always changes the PC and is basically an impromptu branch instruction. why
not speculate on this instead of always be forced to mispredict/squash after the
hwrei gets resolved?

The InOrder model needs this marked as "isControl" so it knows to update the PC
after the ALU executes it. If this isnt marked as control, then it's going to
force the model to check the PC of every instruction at commit (what O3 does?),
and that would be a wasteful check for a very high percentage of instructions.
2011-06-19 21:43:39 -04:00
Korey Sewell
e8b7df072b inorder: make InOrder CPU FS compilable/visible
make syscall a SE mode only functionality
copy over basic FS functions (hwrei) to make FS compile
2011-06-19 21:43:39 -04:00
Korey Sewell
d71b95d84d inorder: remove memdep tracking for default pipeline
speculative load/store pipelines can reenable this
2011-06-19 21:43:39 -04:00
Korey Sewell
b72bdcf4f8 inorder: fetchBuffer tracking
calculate blocks in use for the fetch buffer to figure out how many total blocks
are pending
2011-06-19 21:43:39 -04:00
Korey Sewell
4d4c7d79d0 inorder: redefine DynInst FP result type
Sharing the FP value w/the integer values was giving inconsistent results esp. when
their is a 32-bit integer register matched w/a 64-bit float value
2011-06-19 21:43:38 -04:00
Korey Sewell
db8b1e4b78 inorder: treat SE mode syscalls as a trapping instruction
define a syscallContext to schedule the syscall and then use syscall() to actually perform the action
2011-06-19 21:43:38 -04:00
Korey Sewell
c95fe261ab inorder: bug in mdu
segfault was caused by squashed multiply thats in the process of an event.
use isProcessing flag to handle this and cleanup the MDU code
2011-06-19 21:43:38 -04:00
Korey Sewell
4c979f9325 inorder: optionally track faulting instructions 2011-06-19 21:43:38 -04:00
Korey Sewell
22ba1718c4 inorder: cleanup events in resource pool
remove events in the resource pool that can be called from the CPU event, since the CPU
event is scheduled at the same time at the resource pool event.
----
Also, match the resPool event function names to the cpu event function names
----
2011-06-19 21:43:38 -04:00
Korey Sewell
e8082a28c8 inorder: don't stall after stores
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
2011-06-19 21:43:38 -04:00
Korey Sewell
379c23199e inorder: don't stall after stores
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
2011-06-19 21:43:37 -04:00
Korey Sewell
4c9ad53cc5 inorder: remove decode squash
also, cleanup comments for gem5.fast compilation
2011-06-19 21:43:37 -04:00
Korey Sewell
a444133e73 inorder: support for compare and swap insts
dont treat read() and write() fields as mut. exclusive
2011-06-19 21:43:37 -04:00
Korey Sewell
89d0f95bf0 inorder: branch predictor update
only update BTB on a taken branch and update branch predictor w/pcstate from instruction
---
only pay attention to branch predictor updates if the the inst. is in fact a branch
2011-06-19 21:43:37 -04:00
Korey Sewell
479195d4cf inorder: priority for grad/squash events
define separate priority resource pool squash and graduate events
2011-06-19 21:43:37 -04:00
Korey Sewell
71018f5e8b inorder: remove stalls on trap squash 2011-06-19 21:43:37 -04:00
Korey Sewell
34b2500f09 inorder: no dep. tracking for zero reg
this causes forwarding a bad value register value
2011-06-19 21:43:37 -04:00
Korey Sewell
d02fa0f6b6 imported patch recoverPCfromTrap 2011-06-19 21:43:37 -04:00
Korey Sewell
264e8178ff imported patch squash_from_next_stage 2011-06-19 21:43:36 -04:00
Korey Sewell
f0f33ae2b9 inorder: add flatDestReg member to dyninst
use it in reg. dep. tracking
2011-06-19 21:43:36 -04:00
Korey Sewell
555bd4d842 inorder: update event priorities
dont use offset to calculate this but rather an enum
that can be updated
2011-06-19 21:43:36 -04:00
Korey Sewell
7dea79535c inorder: implement trap handling 2011-06-19 21:43:36 -04:00
Korey Sewell
061b369d28 inorder: cleanup intercomm. structs/squash info 2011-06-19 21:43:35 -04:00
Korey Sewell
b195da9345 inorder: use setupSquash for misspeculation
implement a clean interface to handle branch misprediction and eventually all pipeline
flushing
2011-06-19 21:43:35 -04:00
Korey Sewell
d5d4e47f76 sparc: init. cache state in TLB
valgrind complains and its a potential source of instability, so go ahead
and set it to 0 to start
2011-06-19 21:43:35 -04:00
Korey Sewell
73cfab8b23 inorder: DynInst handling of stores for big-endian ISAs
The DynInst was not performing the host-to-guest translation
which ended up breaking stores for SPARC
2011-06-19 21:43:35 -04:00
Korey Sewell
4f34bc8b7b inorder: make marking of dest. regs an explicit request
formerly, this was implicit when you accessed the execution unit
or the use-def unit but it's better that this just be something
that a user can specify.
2011-06-19 21:43:35 -04:00
Korey Sewell
946b0ed4f4 inorder: simplify handling of split accesses 2011-06-19 21:43:35 -04:00
Korey Sewell
1a6d25dc47 inorder: addtl functionaly for inst. skeds
add find and end functions for inst. schedules
that can search by stage number
2011-06-19 21:43:35 -04:00
Korey Sewell
8b54858831 inorder: register file stats
keep stats for int/float reg file usage instead
of aggregating across reg file types
2011-06-19 21:43:34 -04:00
Korey Sewell
085f30ff9c inorder: scheduling for nonspec insts
make handling of speculative and nonspeculative insts
more explicit
2011-06-19 21:43:34 -04:00
Korey Sewell
3c417ea23a inorder: find register dependencies "lazily"
Architectures like SPARC need to read the window pointer
in order to figure out it's register dependence. However,
this may not get updated until after an instruction gets
executed, so now we lazily detect the register dependence
in the EXE stage (execution unit or use_def). This
makes sure we get the mapping after the most current change.
2011-06-19 21:43:34 -04:00
Korey Sewell
bd67ee9852 inorder: assert on macro-ops
provide a sanity check for someone coding
a new architecture
2011-06-19 21:43:34 -04:00
Korey Sewell
ee7062d94d inorder: handle faults at writeback stage
call trap function when a fault is received
2011-06-19 21:43:34 -04:00
Korey Sewell
17f5749dbb inorder: ISA-zero reg handling
ignore writes to the ISA zero register
2011-06-19 21:43:34 -04:00
Korey Sewell
2a59fcfbe9 inorder: update support for branch delay slots 2011-06-19 21:43:34 -04:00
Korey Sewell
d4b4ef1324 inorder: inst. iterator cleanup
get rid of accessing iterators (for instructions) by reference
2011-06-19 21:43:34 -04:00
Korey Sewell
b43eeaf2e2 cpus/isa: add a != operator for pcstate 2011-06-19 21:43:33 -04:00
Korey Sewell
e2f9266dbf inorder: update bpred code
clean up control flow to make it easier to understand
2011-06-19 21:43:33 -04:00
Korey Sewell
6df6365095 inorder: add types for dependency checks 2011-06-19 21:43:33 -04:00
Korey Sewell
19e3eb2915 inorder: use flattenIdx for reg indexing
- also use "threadId()" instead of readTid() everywhere
- this will help support more complex ISA indexing
2011-06-19 21:43:33 -04:00
Korey Sewell
b2e5152e16 simple-thread: give a name() function for debugging w/the SimpleThread object 2011-06-19 21:43:33 -04:00
Korey Sewell
76c60c5f93 inorder: use m5_hash_map for skedCache
since we dont care about if the cache of instruction schedules is sorted or not,
then the hash map should be faster
2011-06-19 21:43:33 -04:00
Gedare Bloom
3f1f16703d ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. 2011-06-17 12:20:10 -05:00
Ali Saidi
8b4307f8d8 ARM: Handle case where new TLB size is different from previous TLB size.
After a checkpoint we need to make sure that we restore the right
number of entries.
2011-06-16 15:08:12 -05:00
Chander Sudanthi
9fe3610b32 ARM: Fix memset on TLB flush and initialization
Instead of clearing the entire TLB on initialization and flush, the code was
clearing only one element.  This patch corrects the memsets in the init and
flush routines.
2011-06-16 15:08:11 -05:00
Nilay Vaish
8bf92329ee Ruby: Correct set LONG_BITS and INDEX_SHIFT in class Set.
The code for Set class was written under the assumption that
std::numeric_limits<long>::digits returns the number of bits used for
data type long, which was presumed to be either 32 or 64. But return value
is actually one less, that is, it is either 31 or 63. The value is now
being incremented by 1 so as to correctly set it.
2011-06-14 19:51:44 -05:00
Gabe Black
91622602c2 Loader: Handle bad section names when loading an ELF file.
If there's a problem when reading the section names from a supposed ELF file,
this change makes gem5 print an error message as returned by libelf and die.
Previously these sorts of errors would make gem5 segfault when it tried to
access the section name through a NULL pointer.
2011-06-12 23:52:21 -07:00
Korey Sewell
c8b43641fd o3: missing newlines on some dprintfs 2011-06-10 22:15:32 -04:00
Korey Sewell
4229bce89d sparc: don't use directcntrl branch flag
this flag is only used for early branch resolution in the O3 model (of pc-relative branches)
but this isnt cleanly working even when the branch target code is added for sparc. For now,
we'll ignore this optimization and add a todo in the SPARC ISA for future developers
2011-06-10 22:15:32 -04:00
Korey Sewell
1a451cd2c5 sparc: compilation fixes for inorder
Add a few constants and functions that the InOrder model wants for SPARC.
* * *
sparc: add eaComp function
InOrder separates the address generation from the actual access so give
Sparc that functionality
* * *
sparc: add control flags for branches
branch predictors and other cpu model functions need to know specific information
about branches, so add the necessary flags here
2011-06-09 01:34:06 -04:00
Nilay Vaish
67bb307003 Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set correctly.
This is because pointers are not used for handling directory entries.
function. get and set functions for access permissions have been added to the
Controller state machine. The changePermission() function provided by the
AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC
code once again. The set_permission() functionality has been removed.

NOTE: Each protocol will have to define these get and set functions in order
to compile successfully.
2011-06-08 11:58:09 -05:00
Gabe Black
1f7a627401 Mem: Use sysconf to get the page size instead of the PAGE_SIZE macro. 2011-06-08 00:57:50 -07:00
Gabe Black
ab3704170e ISA parser: Loosen the regular expressions matching filenames.
The regular expressions matching filenames in the ##include directives and the
internally generated ##newfile directives where only looking for filenames
composed of alpha numeric characters, periods, and dashes. In Unix/Linux, the
rules for what characters can be in a filename are much looser than that. This
change replaces those expressions with ones that look for anything other than
a quote character. Technically quote characters are allowed as well so we
should allow escaping them somehow, but the additional complexity probably
isn't worth it.
2011-06-07 00:46:54 -07:00
Gabe Black
a59a143a25 gcc 4.0: Add some virtual destructors to make gcc 4.0 happy. 2011-06-07 00:24:49 -07:00
Nilay Vaish
3a083edc30 SLICC: Remove machine name as prefix to functions
Currently, the machine name is appended before any of the functions
defined with in the sm files. This is not necessary and it also
means that these functions cannot be used outside the sm files.
This patch does away with the prefixes. Note that the generated
C++ files in which the code for these functions is present are
still named such that the machine name is the prefix.
2011-06-03 13:52:18 -05:00
Nathan Binkert
2b1aa35e20 scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00
Nathan Binkert
f49f384fe4 scons: rename some things from m5 to gem5
The default generated binary is now gem5.<type> instead of m5.<type>.
The latter does still work but gem5.<type> will be generated first and
then m5.<type> will be hard linked to it.
2011-06-02 17:36:18 -07:00
Nathan Binkert
0c424344fa copyright: Add code for finding all copyright blocks and create a COPYING file
The end of the COPYING file was generated with:
% python ./util/find_copyrights.py configs src system tests util

Update -C command line option to spit out COPYING file
2011-06-02 17:36:07 -07:00
Nathan Binkert
f656787edb copyright: clean up copyright blocks 2011-06-02 14:36:35 -07:00
Steve Reinhardt
6a1be32a72 SimObject: allow modules in subclass definitions
In particular, this avoids crashing when you do
an import (like "import pdb") inside a SimObject
subclass definition.
2011-06-01 21:43:13 -07:00
Tushar Krishna
07e5b15953 orion: bug fix in link power, and some reorg 2011-05-31 02:56:22 -04:00
Tushar Krishna
36899dc197 garnet: added network ptr to links to be used by orion 2011-05-31 02:55:14 -04:00
Gabe Black
8dcbe8adb5 Misc: Remove the URL from warnings, fatals, panics, etc. 2011-05-29 21:48:58 -07:00
Gabe Black
96138a79cd Name: Replace M5 with gem5 in a few places it's printed on startup. 2011-05-25 01:32:07 -07:00
Steve Reinhardt
0cbbedcc33 sim: style fixes in sim/process.hh 2011-05-23 14:29:23 -07:00
Steve Reinhardt
8d29bda742 syscall emul: fix Power Linux mmap constant, plus other cleanup
We were getting a spurious warning in the regressions that turned
out to be due to having the wrong value for TGT_MAP_ANONYMOUS for
Power Linux, but in the process of tracking it down I ended up
doing some cleanup of the mmap handling in general.
2011-05-23 14:29:23 -07:00
Steve Reinhardt
19bb896bfe config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams()
is the practice of appending to SimObjectVectors which have
already been assigned as children.  This practice sidesteps the
assignment operation for those appended SimObjects, which is
where parent/child relationships are typically established.

This patch reworks the config scripts that use append() on
SimObjectVectors, which all happen to be in the x86 system
configuration.  At some point in the future, I hope to make
SimObjectVectors immutable (by deriving from tuple rather than
list), at which time this patch will be necessary for correct
operation.  For now, it just avoids some of the warning
messages that get printed in adoptOrphanParams().
2011-05-23 14:29:23 -07:00
Steve Reinhardt
8a652f9871 config: tweak ruby configs to clean up hierarchy
Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings.  This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
   caches children of the sequencer rather than the controller; these
   config ciles are rewritten to assign the L1 caches to the
   controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
   causes the sequencers to be children of system.ruby, generating
   warnings because they are already parented to their respective
   controllers.  Changing this attribute to _cpu_ruby_ports fixes this
   because the leading underscore means this is now treated as a plain
   Python attribute rather than a child assignment. As a result, the
   configuration hierarchy changes such that, e.g.,
   system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
   internal link node rather than direct children of the topology.
   The topology classes are rewritten to assign the routers to the
   topology object first.
2011-05-23 14:29:23 -07:00
Steve Reinhardt
41fc9bbab5 config: reinstate implicit parenting on parameter assignment
Last summer's big rewrite of the initialization code (in
particular cset 6efc3672733b) got rid of the implicit parenting
that used to occur when an unparented SimObject was assigned as
a parameter value to another SimObject.  The idea was that the
new adoptOrphanParams() step would catch these anyway so it was
unnecessary.

Unfortunately it turns out that adoptOrphanParams() has some
inherent instability in that the parent that does the adoption
depends on the config tree traversal order.  Even making this
order deterministic (e.g., by traversing children in
alphabetical order) can introduce unwanted and unexpected
hierarchy changes between similar configs (e.g., when adding a
switch_cpu in place of a cpu), causing problems when trying to
restore checkpoints across similar configs.  The hierarchy
created by implicit parenting is more stable and more
controllable, so this patch turns that behavior back on.

This patch also cleans up some long-standing holes regarding
parenting of SimObjects that are created in class definitions
(either in the body of the class, or as default parameters).

To avoid breaking some existing config files, this necessitated
changing the error on reparenting children to a warning.  This
change fixes another bug where attempting to print the prior
error message would fail on reparenting SimObjectVectors
because they lack a _parent attribute.  Some further issues
with SimObjectVectors were cleaned up by getting rid of the
get_parent() call (which could cause errors with some
SimObjectVectors where there was no single parent to return)
with has_parent() (since all the uses of get_parent() were just
boolean tests anyway).

Finally, since the adoptOrphanParam() step turned out to be so
problematic, we now issue a warning when it actually has to do
an adoption.  Future cleanup of config files will get rid of
current warnings.
2011-05-23 14:29:08 -07:00
Steve Reinhardt
ccbecb9e8f sim: add some DPRINTFs for debugging unserialization
Also got rid of unused C++ unserializeAll() method
(this is now handled in Python)
2011-05-23 14:27:20 -07:00
Geoffrey Blake
d0b0a55515 O3: Fix offset calculation into storeQueue buffer for store->load forwarding
Calculation of offset to copy from storeQueue[idx].data structure for load to
store forwarding fixed to be difference in bytes between store and load virtual
addresses.  Previous method would induce bug where a load would index into
buffer at the wrong location.
2011-05-23 10:40:21 -05:00
Geoffrey Blake
c223b887fe O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.
If a split load fails on a blocked cache wbOutstanding can be decremented
twice if the first part of the split load succeeds and the second part fails.
Condition the decrementing on not having completed the first part of the load.
2011-05-23 10:40:19 -05:00
Geoffrey Blake
6dd996aabb O3: Fix issue with interrupts/faults occuring in the middle of a macro-op
This patch fixes two problems with the O3 cpu model. The first is an issue
with an instruction fetch causing a fault on the next address while the
current macro-op is being issued. This happens when the micro-ops exceed
the fetch bandwdith and then on the next cycle the fetch stage attempts
to issue a request to the next line while it still has micro-ops to issue
if the next line faults a fault is attached to a micro-op in the currently
executing macro-op rather than a "nop" from the next instruction block.
This leads to an instruction incorrectly faulting when on fetch when
it had no reason to fault.

A similar problem occurs with interrupts. When an interrupt occurs the
fetch stage nominally stops issuing instructions immediately. This is incorrect
in the case of a macro-op as the current location might not be interruptable.
2011-05-23 10:40:18 -05:00
Tushar Krishna
fc1d2d9679 garnet: use vnet_type from protocol to decide buffer depths
The virtual channels within "response" vnets are made buffers_per_data_vc
deep (default=4), while virtual channels within other vnets are made
buffers_per_ctrl_vc deep (default = 1). This is for accurate power estimates.
2011-05-21 00:40:57 -04:00
Tushar Krishna
3d06ffa7d5 slicc: added vnet_type to MI_example
Forgot to add this to MI_example in my previous patch.
2011-05-20 05:06:43 -04:00
Nathan Binkert
22263f5091 gcc: fix an uninitialized variable warning from G++ 4.5 2011-05-18 11:06:23 -07:00
Tushar Krishna
3ed048e4f5 slicc: added vnet_type field to identify response vnets from others
Identifying response vnets versus other vnets will allow garnet to
determine which vnets will carry data packets, and which will carry
ctrl packets, and use appropriate buffer sizes (since data packets are larger
than ctrl packets). This in turn allows the orion power model to accurately
estimate buffer power.
2011-05-18 03:06:07 -04:00
Tushar Krishna
26eaba4cb5 garnet: rename and rearrange config parameters.
Renamed (message) class to vnet for consistency with rest of ruby.
Moved some parameters specific to fixed/flexible garnet networks into their
corresponding py files.
2011-05-18 03:04:14 -04:00
Ali Saidi
b5160ba2c3 ARM: Generate condition code setting code based on which codes are set.
This change further eliminates cases where condition codes were being read
just so they could be written without change because the instruction in
question was supposed to preserve them. This is done by creating the condition
code code based on the input rather than just doing a simple substitution.
2011-05-13 17:27:02 -05:00
Ali Saidi
05866c82f9 ARM: Construct the predicate test register for more instruction programatically.
If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.
2011-05-13 17:27:02 -05:00
Ali Saidi
401165c778 ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
2011-05-13 17:27:01 -05:00
Ali Saidi
e097c4fb18 ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
2011-05-13 17:27:01 -05:00
Ali Saidi
2178859b76 ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
2011-05-13 17:27:01 -05:00
Chander Sudanthi
4bf48a11ef Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.
Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
ExecKernel are set by default when Exec is specified.  Use minus
sign with ExecUser or ExecKernel to remove user or kernel tracing
respectively.
2011-05-13 17:27:00 -05:00
Chander Sudanthi
5299c75e62 ARM: Better RealView/Versatile EB platform support.
Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
2011-05-13 17:27:00 -05:00
Geoffrey Blake
b79650ceaa O3: Fix an issue with a load & branch instruction and mem dep squashing
Instructions that load an address and are control instructions can
execute down the wrong path if they were predicted correctly and then
instructions following them are squashed. If an instruction is a
memory and control op use the predicted address for the next PC instead
of just advancing the PC. Without this change NPC is used for the next
instruction, but predPC is used to verify that the branch was successful
so the wrong path is silently executed.
2011-05-13 17:27:00 -05:00
Nathan Binkert
f7b3900c13 stats: delete mysql support
we can add it back within python in some future changeset
2011-05-12 11:19:35 -07:00
Nathan Binkert
1177e7a3c8 stats: move code that loops over all stats into python 2011-05-12 11:19:35 -07:00
Nathan Binkert
35b0c1d391 stats: better expose statistics to python.
Build a python list and dict of all stats and expose flags properly.

--HG--
rename : src/python/m5/stats.py => src/python/m5/stats/__init__.py
2011-05-12 11:19:32 -07:00
Nathan Binkert
9c4c1419a7 work around gcc 4.5 warning 2011-05-09 16:34:11 -04:00
Tushar Krishna
1267ff5949 NetworkTest: added sim_cycles parameter to the network tester.
The network tester terminates after injecting for sim_cycles
(default=1000), instead of having to explicitly pass --maxticks from the
command line as before. If fixed_pkts is enabled, the tester only
injects maxpackets number of packets, else it keeps injecting till sim_cycles.
The tester also works with zero command line arguments now.
2011-05-07 17:43:30 -04:00
Tushar Krishna
770f2ce330 network: added Torus and Pt2Pt topologies 2011-05-07 17:28:15 -04:00
Nilay Vaish
ffaef14466 Trace: Remove the options trace-help and trace-flags
The options trace-help and trace-flags are no longer required. In there place,
the options debug-help and debug-flags have been provided.
2011-05-07 07:38:36 -05:00
Gabe Black
b8889a96b3 X86: Fix the Lldt instructions so they load the ldtr and not the tr. 2011-05-06 01:00:32 -07:00
Korey Sewell
a0415f2b24 ruby: use RubyMemory flag & remove setDebug() functionality
The RubyMemory flag wasnt used in the code, creating large gaps in trace output. Replace cprintfs w/dprintfs
using RubyMemory in memory controller. DPRINTF also deprecate the usage of the setDebug() pure virtual
function in the AbstractMemoryOrCache Class as well the m_debug/cprintf functions in MemoryControl.hh/cc
2011-05-05 02:20:31 -04:00
Ali Saidi
42e7888855 ARM: Add support for loading the a bootloader and configuring parameters for it 2011-05-04 20:38:28 -05:00
Prakash Ramrakhyani
1b505f5291 ARM: Implement WFE/WFI/SEV semantics. 2011-05-04 20:38:28 -05:00
Ali Saidi
ba8d64520e ARM: Add support for MP misc regs and broadcast flushes. 2011-05-04 20:38:28 -05:00
Prakash Ramrakhyani
13574d8b4e ARM: Make GIC handle IPIs and multiple processors. 2011-05-04 20:38:27 -05:00
Ali Saidi
5f73d4ac97 ARM: Add snoop control unit device. 2011-05-04 20:38:27 -05:00
Ali Saidi
afd08879d7 ARM: Add support for some more registers in the real view controller. 2011-05-04 20:38:27 -05:00
Ali Saidi
8aff996db1 Debug: Add a function to cause the simulator to create a checkpoint from GDB. 2011-05-04 20:38:27 -05:00
Ali Saidi
77bea2fb42 CPU: Add some useful debug message to the timing simple cpu. 2011-05-04 20:38:27 -05:00
Ali Saidi
6e634beb8a CPU: Fix a case where timing simple cpu faults can nest.
If we fault, change the state to faulting so that we don't fault again in the same cycle.
2011-05-04 20:38:27 -05:00
Ali Saidi
89e7bcca82 O3: Remove assertion for case that is actually handled in code.
If an nonspeculative instruction has a fault it might not be in the
nonSpecInsts map.
2011-05-04 20:38:27 -05:00
Ali Saidi
974a776b31 Core: Add some documentation about the sim clocks. 2011-05-04 20:38:27 -05:00
Chris Emmons
8dcbf8576e RealView: Fix the 24 and 100MHz clocks which were providing incorrect values. 2011-05-04 20:38:26 -05:00
Ali Saidi
09a2be0c39 O3: Fix a small corner case with the lsq hazard detection logic. 2011-05-04 20:38:26 -05:00
Ali Saidi
48f7fda706 ARM: Add vfpv3 support to native trace. 2011-05-04 20:38:26 -05:00
Ali Saidi
632cf8dd80 ARM: Fix small bug with vcvt instruction 2011-05-04 20:38:26 -05:00
Nathan Binkert
0dffd35741 debug: fix help output 2011-05-04 10:08:08 -04:00
Korey Sewell
dd95bc4d44 ruby: dbg: use system ticks instead of cycles 2011-05-02 00:16:14 -04:00
Brad Beckmann
93a50fc318 network: set the ExtLink bw to 16 bytes
Therefore all links by default are 16 bytes wide and thus work with Garnet's
uniform link bandwidth assumption.
2011-04-28 17:18:14 -07:00
Brad Beckmann
6c7429dbe3 garnet: removed flit_width from Routers 2011-04-28 17:18:14 -07:00
Brad Beckmann
651cfbab03 network: adjusted default endpoint bandwidth
The simple network's endpoint bandwidth value is used to adjust the overall
bandwidth of the network.  Specifically, the ration between endpoint bandwidth
and the MESSAGE_SIZE_MULTIPLIER determines the increase.  By setting the value
to 1000, that means the bandwdith factor specified in the links translates to
the link bandwidth in bytes.  Previously, it was increasing that value by 10.

This patch will likely require a reset of the ruby regression tester stats.
2011-04-28 17:18:14 -07:00
Brad Beckmann
887e2df5a3 network: removed the unused network-wide latency param 2011-04-28 17:18:14 -07:00
Brad Beckmann
491cc1a9f4 network: moved network config params
Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of
the top-level parent network object and to only those networks that actually
use those parameters.
2011-04-28 17:18:14 -07:00
Brad Beckmann
8733ed4b7d network: basic link bw for garnet and simple networks
This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology.  To do so, the patch generalizes the specification
of bw for basic links.  This value is then translated to the specific value
used by the simple and Garnet networks.  Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

--HG--
rename : src/mem/ruby/network/BasicLink.cc => src/mem/ruby/network/simple/SimpleLink.cc
rename : src/mem/ruby/network/BasicLink.hh => src/mem/ruby/network/simple/SimpleLink.hh
rename : src/mem/ruby/network/BasicLink.py => src/mem/ruby/network/simple/SimpleLink.py
2011-04-28 17:18:14 -07:00
Brad Beckmann
40bcbf4253 network: convert links & switches to first class C++ SimObjects
This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes.  This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.

--HG--
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
2011-04-28 17:18:14 -07:00
Brad Beckmann
bc5eb59605 garnet: cleaned up flexible network header file 2011-04-28 17:18:12 -07:00
Brad Beckmann
cf9ce2cf28 ruby: moved topology to the top network directory
Moved the Topology class to the top network directory because it is shared by
both the simple and Garnet networks.

--HG--
rename : src/mem/ruby/network/simple/Topology.cc => src/mem/ruby/network/Topology.cc
rename : src/mem/ruby/network/simple/Topology.hh => src/mem/ruby/network/Topology.hh
2011-04-28 17:18:12 -07:00
Brad Beckmann
7adb8fa94b ruby: removed dated comment in SimpleNetwork 2011-04-28 17:18:12 -07:00
Nathan Binkert
3e319d6e94 event: fix PythonEvent
order of %includes since they matter for this case
2011-04-28 16:45:17 -07:00
Nilay Vaish
9e3cdbf516 base: include types.hh in base/stats/mysql.hh
Due to certain changes made via changeset 8229, the compilation was failing
in certain cases. The compiler pointed to base/stats/mysql.hh for not naming
a certain types like uint64_t. To rectify this, base/types.hh is being
included in base/stats/mysql.hh.
2011-04-25 12:23:37 -05:00
Gabe Black
0554885eb9 X86: When decoding a memory only inst, fault on reg encodings, don't assert.
This change makes the decoder figure out if an instruction that only supports
memory is using a register encoding and decodes directly to "Unknown" which will
behave appropriately. This prevents other parts of the instruction creation
process from seeing the mismatch and asserting.
2011-04-23 15:02:29 -07:00
Nathan Binkert
2342aa2ebb stats: ensure that stat names are valid 2011-04-20 19:07:46 -07:00
Nathan Binkert
6e9143d36d stats: one more name violation 2011-04-20 19:07:45 -07:00
Nathan Binkert
99fbd18ea5 fix some build problems from prior changesets 2011-04-20 18:45:03 -07:00
Brad Danofsky
46a538ceab stats: add user settable separator string for arrayed stats
Default is '::', so no visible change unless it is overridden
2011-04-20 11:14:52 -07:00
Brad Danofsky
dd38b4b83e scons: Allow the build directory live under an EXTRAS directory 2011-04-20 11:14:51 -07:00
Nathan Binkert
63371c8664 stats: rename stats so they can be used as python expressions 2011-04-19 18:45:21 -07:00
Nathan Binkert
615c5e0eaa python: different import for dealing with demandimport 2011-04-19 11:13:01 -07:00
Nathan Binkert
915f49ae92 unittest: Make unit tests capable of using swig and python, convert stattest 2011-04-15 10:45:11 -07:00
Nathan Binkert
8c97726266 python: cleanup python code so stuff doesn't automatically happen at startup
this allows things to be overridden at startup (e.g. for tests)
2011-04-15 10:44:59 -07:00
Nathan Binkert
3182913e94 scons: make a flexible system for guarding source files
This is similar to guards on mercurial queues and they're used for selecting
which files are compiled into some given object.  We already do something
similar, but it's mostly hard coded for the m5 binary and the m5 library
and I'd like to make it more flexible to better support the unittests
2011-04-15 10:44:44 -07:00
Nathan Binkert
eddac53ff6 trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing.  This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15 10:44:32 -07:00
Nathan Binkert
f946d7bcdb debug: create a Debug namespace 2011-04-15 10:44:15 -07:00
Nathan Binkert
bbb1392c08 includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
Nathan Binkert
39a055645f includes: sort all includes 2011-04-15 10:44:06 -07:00
Nathan Binkert
07815c3379 region: add a utility class for keeping track of regions of some range
This is basically like the range_map stuff in src/base (range already
exists in Python).  This code is like a set of ranges.  I'm using it
to keep track of changed lines in source code, but it could be use to
keep track of memory ranges and holes in memory regions.  It could
also be used in memory allocation type stuff.  (Though it's not at all
optimized.)
2011-04-15 10:42:32 -07:00
Nathan Binkert
12446e9659 SortedDict: add functions for getting ranges of keys, values, items 2011-04-15 10:38:02 -07:00
Nathan Binkert
1f7f79781e python: figure out if the m5.internal package exists even with demandimport 2011-04-15 10:37:28 -07:00
Nathan Binkert
3c78005c1e refcnt: Update doxygen comments 2011-04-13 09:32:19 -07:00
Nathan Binkert
e748d921fd refcnt: Inline comparison functions 2011-04-13 09:32:18 -07:00
Nathan Binkert
9d94d48a7d main: separate out interact() so it can be used by other functions 2011-04-13 09:32:18 -07:00
Ali Saidi
4b61abe8da ARM: Fix checkpoint restoration in ARM_SE. 2011-04-10 21:02:28 -04:00
Ali Saidi
b9dc954d89 ARM: Get rid of some comments/todos that no longer apply. 2011-04-10 21:02:28 -04:00
Brad Beckmann
95faf1904b ruby: fixes to support more types of RubyRequests 2011-04-06 14:41:41 -07:00
Ali Saidi
d6289507d8 ARM: Include IDE/CF controller by default in PBX model.
Frame buffer and boot linux:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit
Linux from a CF card:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit
Run Android
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android
Run MP
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
2011-04-04 11:42:31 -05:00
Ali Saidi
8af1eeec6f ARM: Use CPU local lock before sending load to mem system.
This change uses the locked_mem.hh header to handle implementing CLREX. It
simplifies the current implementation greatly.
2011-04-04 11:42:29 -05:00
Ali Saidi
6b69890493 ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.
This change fixes a small bug in the arm copyRegs() code where some registers
wouldn't be copied if the processor was in a mode other than MODE_USER.
Additionally, this change simplifies the way the O3 switchCpu code works by
utilizing TheISA::copyRegs() to copy the required context information
rather than the adhoc copying that goes on in the CPU model. The current code
makes assumptions about the visibility of int and float registers that aren't
true for all architectures in FS mode.
2011-04-04 11:42:28 -05:00
Ali Saidi
f926fa7711 ARM: Fix bug in MicroLdrNeon templates for initiateAcc(). 2011-04-04 11:42:28 -05:00
William Wang
16fcad3907 ARM: Cleanup and small fixes to some NEON ops to match the spec.
Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
2011-04-04 11:42:28 -05:00
Ali Saidi
a679cd917a ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
2011-04-04 11:42:28 -05:00
Ali Saidi
ac650199ee ARM: Fix m5op parameters bug.
All the m5op parameters are 64 bits, but we were only sending 32 bits;
and the static register indexes were incorrectly specified.
2011-04-04 11:42:28 -05:00
Ali Saidi
be096f91b9 ARM: Tag appropriate instructions as IsReturn 2011-04-04 11:42:27 -05:00
Ali Saidi
55920a5ca7 ARM: Fix table walk going on while ASID changes error 2011-04-04 11:42:27 -05:00
Ali Saidi
5962fecc1d CPU: Remove references to memory copy operations 2011-04-04 11:42:26 -05:00
Ali Saidi
7dde557fdc O3: Tighten memory order violation checking to 16 bytes.
The comment in the code suggests that the checking granularity should be 16
bytes, however in reality the shift by 8 is 256 bytes which seems much
larger than required.
2011-04-04 11:42:23 -05:00
Ali Saidi
ee489a541a IDE: Support x86, Alpha, and ARM use of the IDE controller. 2011-04-04 11:42:23 -05:00
Ali Saidi
c56eb8fb3c ARM: Fix checkpointing case where PL111 is powered off. 2011-04-04 11:42:23 -05:00
Ali Saidi
6fd271ffb3 ARM: Remove debugging warn that was accidently left in. 2011-04-04 11:42:23 -05:00
Ali Saidi
dfdabbd751 ARM: Fix multiplication error in udelay 2011-04-04 11:42:23 -05:00
Brad Beckmann
0788ea7b3b hammer: fixed dma uniproc error
Fixed an error reguarding DMA for uninprocessor systems.  Basically removed an
overly agressive optimization that lead to inconsistent state between the
cache and the directory.
2011-04-01 15:50:23 -07:00
Lisa Hsu
01fc529bb2 CacheMemory: add allocateVoid() that is == allocate() but no return value.
This function duplicates the functionality of allocate() exactly, except that it does not return
a return value.  In protocols where you just want to allocate a block
but do not want that block to be your implicitly passed cache_entry, use this function.
Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(),
and if you do a dummy assignment Entry foo := cache.allocate(address), the C++
compiler will complain of an unused variable.  This is kind of a hack to get around
those issues, but suggestions welcome.
2011-03-31 18:20:12 -07:00
Lisa Hsu
d857105b5a Ruby: Simplify SLICC and Entry/TBE handling.
Before this changeset, all local variables of type Entry and TBE were considered
to be pointers, but an immediate use of said variables would not be automatically
deferenced in SLICC-generated code.  Instead, deferences occurred when such
variables were passed to functions, and were automatically dereferenced in
the bodies of the functions (e.g. the implicitly passed cache_entry).

This is a more general way to do it, which leaves in place the
assumption that parameters to functions and local variables of type AbstractCacheEntry
and TBE are always pointers, but instead of dereferencing to access member variables
on a contextual basis, the dereferencing automatically occurs on a type basis at the
moment a member is being accessed.  So, now, things you can do that you couldn't before
include:

Entry foo := getCacheEntry(address);
cache_entry.DataBlk := foo.DataBlk;

or

cache_entry.DataBlk := getCacheEntry(address).DataBlk;

or even

cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk;
2011-03-31 17:18:00 -07:00
Lisa Hsu
322b9ca2c5 Ruby: Add new object called WireBuffer to mimic a Wire.
This is a substitute for MessageBuffers between controllers where you don't
want messages to actually go through the Network, because requests/responses can
always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered)
because you are, after all, going through a network with contention. For systems where you model
multiple controllers that are very tightly coupled and do not actually go through a network,
it is a pain to have to write a coherence protocol to account for mixed up request/response orderings
despite the fact that it's completely unrealistic.  This is *not* meant as a substitute for real
MessageBuffers when messages do in fact go over a network.
2011-03-31 17:17:57 -07:00
Lisa Hsu
06fcaf9104 Ruby: have the rubytester pass contextId to Ruby. 2011-03-31 17:17:51 -07:00
Lisa Hsu
c9621cc69b Ruby: enable multiple sequencers in one controller. 2011-03-31 17:17:49 -07:00
Lisa Hsu
225e67f531 Ruby: pass Packet->Req->contextId() to Ruby.
It is useful for Ruby to understand from whence request packets came.
This has all request packets going into Ruby pass the contextId value, if
it exists.  This supplants the old libruby proc_id value passed around in
all the Messages, so I've also removed the unused unsigned proc_id; member
generated by SLICC for all Message types.
2011-03-31 17:17:47 -07:00
Lisa Hsu
f6a0b63d7b Ruby: Bug in SLICC forgot semicolon at end of code. 2011-03-31 12:20:16 -07:00
Korey Sewell
473bc21977 sim: typecast Tick to UTick for eventQ assert 2011-03-29 19:36:36 -04:00
Gabe Black
ccc8ba2033 Power: Fix compilation. 2011-03-29 13:04:19 -04:00
Somayeh Sardashti
c8bbfed937 This patch supports cache flushing in MOESI_hammer 2011-03-28 10:49:45 -05:00