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inorder: branch predictor update

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only update BTB on a taken branch and update branch predictor w/pcstate from instruction
---
only pay attention to branch predictor updates if the the inst. is in fact a branch
This commit is contained in:
Korey Sewell 2011-06-19 21:43:37 -04:00
parent 479195d4cf
commit 89d0f95bf0
5 changed files with 17 additions and 8 deletions
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3
src/cpu/inorder/cpu.cc
View file

@ -506,6 +506,9 @@ InOrderCPU::createBackEndSked(DynInstPtr inst)
W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
}
if (inst->isControl())
W.needs(BPred, BranchPredictor::UpdatePredictor);
// Insert Back Schedule into our cache of
// resource schedules
addToSkedCache(inst, res_sked);

2
src/cpu/inorder/pipeline_stage.cc
View file

@ -420,7 +420,7 @@ PipelineStage::squash(InstSeqNum squash_seq_num, ThreadID tid)
while (cur_it != end_it) {
if ((*cur_it)->seqNum <= squash_seq_num) {
DPRINTF(InOrderStage, "[tid:%i]: Cannot remove skidBuffer "
"instructions (starting w/[sn:%i]) before delay slot "
"instructions (starting w/[sn:%i]) before "
"[sn:%i]. %i insts left.\n", tid,
(*cur_it)->seqNum, squash_seq_num,
skidBuffer[tid].size());

6
src/cpu/inorder/resources/bpred_unit.cc
View file

@ -250,7 +250,7 @@ BPredUnit::predict(DynInstPtr &inst, TheISA::PCState &predPC, ThreadID tid)
tid, asid, inst->pcState(), target);
} else {
DPRINTF(InOrderBPred, "[tid:%i]: BTB doesn't have a "
"valid entry.\n",tid);
"valid entry, predicting false.\n",tid);
pred_taken = false;
}
}
@ -369,7 +369,9 @@ BPredUnit::squash(const InstSeqNum &squashed_sn,
BPUpdate((*hist_it).pc.instAddr(), actually_taken,
pred_hist.front().bpHistory);
BTB.update((*hist_it).pc.instAddr(), corrTarget, asid);
// only update BTB on branch taken right???
if (actually_taken)
BTB.update((*hist_it).pc.instAddr(), corrTarget, asid);
DPRINTF(InOrderBPred, "[tid:%i]: Removing history for [sn:%i] "
"PC %s.\n", tid, (*hist_it).seqNum, (*hist_it).pc);

8
src/cpu/inorder/resources/branch_predictor.cc
View file

@ -152,10 +152,14 @@ BranchPredictor::squash(DynInstPtr inst, int squash_stage,
DPRINTF(InOrderBPred, "[tid:%i][sn:%i] Squashing...\n", tid,
bpred_squash_num);
// update due to branch resolution
if (squash_stage >= ThePipeline::BackEndStartStage) {
bool taken = inst->predTaken();
branchPred.squash(bpred_squash_num, inst->readPredTarg(), taken, tid);
branchPred.squash(bpred_squash_num,
inst->pcState(),
inst->pcState().branching(),
tid);
} else {
// update due to predicted taken branch
branchPred.squash(bpred_squash_num, tid);
}
}

6
src/cpu/inorder/resources/fetch_seq_unit.cc
View file

@ -79,13 +79,13 @@ FetchSeqUnit::execute(int slot_num)
ThreadID tid = inst->readTid();
int stage_num = fs_req->getStageNum();
DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
pc[tid]);
switch (fs_req->cmd)
{
case AssignNextPC:
{
DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
pc[tid]);
if (pcValid[tid]) {
inst->pcState(pc[tid]);
inst->setMemAddr(pc[tid].instAddr());