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inorder: no dep. tracking for zero reg

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this causes forwarding a bad value register value
This commit is contained in:
Korey Sewell 2011-06-19 21:43:37 -04:00
parent d02fa0f6b6
commit 34b2500f09
5 changed files with 41 additions and 7 deletions
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1
src/cpu/inorder/cpu.cc
View file

@ -1312,7 +1312,6 @@ InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
lastCommittedPC[tid] = comm_pc;
TheISA::advancePC(comm_pc, inst->staticInst);
pcState(comm_pc, tid);
DPRINTF(InOrderGraduation, "Precise State PC = %s\n", pcState(tid));
//@todo: may be unnecessary with new-ISA-specific branch handling code
if (inst->isControl()) {

19
src/cpu/inorder/reg_dep_map.cc
View file

@ -103,6 +103,14 @@ RegDepMap::insert(DynInstPtr inst)
inst->seqNum, i, raw_idx, flat_idx);
inst->flattenDestReg(i, flat_idx);
if (flat_idx == TheISA::ZeroReg) {
DPRINTF(IntRegs, "[sn:%i]: Ignoring Insert-Dependency tracking for "
"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
flat_idx);
continue;
}
insert(reg_type, flat_idx, inst);
}
}
@ -134,8 +142,17 @@ RegDepMap::remove(DynInstPtr inst)
for (int i = 0; i < dest_regs; i++) {
RegIndex flat_idx = inst->flattenedDestRegIdx(i);
if (flat_idx == TheISA::ZeroReg) {
DPRINTF(IntRegs, "[sn:%i]: Ignoring Remove-Dependency tracking for "
"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
flat_idx);
continue;
}
InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
remove(reg_type, inst->flattenedDestRegIdx(i), inst);
remove(reg_type, flat_idx, inst);
}
}
}

4
src/cpu/inorder/resources/decode_unit.cc
View file

@ -62,6 +62,10 @@ DecodeUnit::execute(int slot_num)
{
assert(!inst->staticInst->isMacroop());
DPRINTF(Decode,"Decoded instruction [sn:%i]: %s : 0x%x\n",
inst->seqNum, inst->instName(),
inst->staticInst->machInst);
inst->setBackSked(cpu->createBackEndSked(inst));
if (inst->backSked != NULL) {

4
src/cpu/inorder/resources/graduation_unit.cc
View file

@ -78,8 +78,8 @@ GraduationUnit::execute(int slot_num)
}
DPRINTF(InOrderGraduation,
"[tid:%i] Graduating instruction %s [sn:%i].\n",
tid, inst->instName(), inst->seqNum);
"[tid:%i]:[sn:%i]: Graduating instruction %s.\n",
tid, inst->seqNum, inst->instName());
// Release Non-Speculative "Block" on instructions that could not
// execute because there was a non-speculative inst. active.

20
src/cpu/inorder/resources/use_def.cc
View file

@ -181,9 +181,16 @@ UseDefUnit::execute(int slot_idx)
RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
inst->flattenSrcReg(ud_idx, flat_idx);
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Attempting to read source "
"register idx %i (reg #%i, flat#%i).\n",
tid, seq_num, ud_idx, reg_idx, flat_idx);
if (flat_idx == TheISA::ZeroReg) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Ignoring Reading of ISA-ZeroReg "
"(Int. Reg %i).\n", tid, inst->seqNum, flat_idx);
ud_req->done();
return;
} else {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Attempting to read source "
"register idx %i (reg #%i, flat#%i).\n",
tid, seq_num, ud_idx, reg_idx, flat_idx);
}
if (regDepMap[tid]->canRead(reg_type, flat_idx, inst)) {
switch (reg_type)
@ -324,6 +331,13 @@ UseDefUnit::execute(int slot_idx)
RegIndex reg_idx = inst->_destRegIdx[ud_idx];
RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
if (flat_idx == TheISA::ZeroReg) {
DPRINTF(IntRegs, "[tid:%i]: Ignoring Writing of ISA-ZeroReg "
"(Int. Reg %i)\n", tid, flat_idx);
ud_req->done();
return;
}
if (regDepMap[tid]->canWrite(reg_type, flat_idx, inst)) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Flattening register idx %i "
"(%i) and Attempting to write to Register File.\n",