inorder: stall stores on store conditionals & compare/swaps
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f268d7d004
commit
e0e387c2a9
2 changed files with 38 additions and 32 deletions
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@ -61,7 +61,7 @@ if 'InOrderCPU' in env['CPU_MODELS']:
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'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
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'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef',
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'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource',
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'ThreadModel', 'AddrDep'])
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'InOrderStall','ThreadModel', 'AddrDep'])
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Source('inorder_dyn_inst.cc')
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Source('inorder_cpu_builder.cc')
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@ -338,7 +338,7 @@ CacheUnit::requestAgain(DynInstPtr inst, bool &service_request)
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cache_req->cmd = inst->curSkedEntry->cmd;
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Updating the command for this "
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"instruction\n ", inst->readTid(), inst->seqNum);
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"instruction\n", inst->readTid(), inst->seqNum);
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service_request = true;
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} else if (inst->curSkedEntry->idx != CacheUnit::InitSecondSplitRead &&
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@ -725,40 +725,46 @@ CacheUnit::execute(int slot_num)
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break;
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case CompleteWriteData:
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Trying to Complete Data Write Access\n",
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tid, inst->seqNum);
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: cSwap:%i LLSC:%i isSwap:%i isCond:%i\n",
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tid, inst->seqNum,
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cache_req->memReq->isCondSwap(),
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cache_req->memReq->isLLSC(),
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cache_req->memReq->isSwap(),
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inst->isStoreConditional());
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{
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: Trying to Complete Data Write Access\n",
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tid, inst->seqNum);
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//@todo: check that timing translation is finished here
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if (cache_req->dataPkt->isRead()) {
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assert(cache_req->memReq->isCondSwap() ||
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cache_req->memReq->isLLSC() ||
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cache_req->memReq->isSwap());
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//@todo: check that timing translation is finished here
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RequestPtr mem_req = cache_req->memReq;
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: cSwap:%i LLSC:%i isSwap:%i isCond:%i\n",
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tid, inst->seqNum,
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mem_req->isCondSwap(),
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mem_req->isLLSC(),
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mem_req->isSwap(),
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inst->isStoreConditional());
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if (!cache_req->isMemAccComplete()) {
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DPRINTF(InOrderStall, "STALL: [tid:%i]: Data miss from %08p\n",
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tid, cache_req->inst->getMemAddr());
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cache_req->setCompleted(false);
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cache_req->setMemStall(true);
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return;
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if (mem_req->isCondSwap() || mem_req->isLLSC() || mem_req->isSwap()) {
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DPRINTF(InOrderCachePort, "Detected Conditional Store Inst.\n");
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if (!cache_req->isMemAccComplete()) {
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DPRINTF(InOrderStall, "STALL: [tid:%i]: Data miss from %08p\n",
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tid, cache_req->inst->getMemAddr());
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cache_req->setCompleted(false);
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cache_req->setMemStall(true);
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return;
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} else {
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DPRINTF(InOrderStall, "Mem Acc Completed\n");
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}
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}
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if (cache_req->isMemAccPending()) {
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DPRINTF(InOrderCachePort, "Store Instruction Pending Completion.\n");
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cache_req->dataPkt->reqData = cache_req->reqData;
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cache_req->dataPkt->memReq = cache_req->memReq;
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} else
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DPRINTF(InOrderCachePort, "Store Instruction Finished Completion.\n");
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//@todo: if split inst save data
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finishCacheUnitReq(inst, cache_req);
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}
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if (cache_req->isMemAccPending()) {
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cache_req->dataPkt->reqData = cache_req->reqData;
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cache_req->dataPkt->memReq = cache_req->memReq;
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}
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//@todo: if split inst save data
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finishCacheUnitReq(inst, cache_req);
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break;
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case CompleteSecondSplitRead:
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