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inorder: redefine DynInst FP result type

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Sharing the FP value w/the integer values was giving inconsistent results esp. when
their is a 32-bit integer register matched w/a 64-bit float value
This commit is contained in:
Korey Sewell 2011-06-19 21:43:38 -04:00
parent db8b1e4b78
commit 4d4c7d79d0
7 changed files with 116 additions and 67 deletions
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28
src/cpu/inorder/cpu.cc
View file

@ -195,6 +195,7 @@ InOrderCPU::InOrderCPU(Params *params)
timeBuffer(2 , 2),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
stCondFails(0),
#if FULL_SYSTEM
system(params->system),
physmem(system->physmem),
@ -206,6 +207,7 @@ InOrderCPU::InOrderCPU(Params *params)
switchCount(0),
deferRegistration(false/*params->deferRegistration*/),
stageTracing(params->stageTracing),
lastRunningCycle(0),
instsPerSwitch(0)
{
ThreadID active_threads;
@ -258,6 +260,9 @@ InOrderCPU::InOrderCPU(Params *params)
}
for (ThreadID tid = 0; tid < numThreads; ++tid) {
pc[tid].set(0);
lastCommittedPC[tid].set(0);
#if FULL_SYSTEM
// SMT is not supported in FS mode yet.
assert(numThreads == 1);
@ -1170,12 +1175,18 @@ InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
FloatReg
InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
{
DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
return floatRegs.f[tid][reg_idx];
}
FloatRegBits
InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
{;
{
DPRINTF(FloatRegs, "[tid:%i]: Reading Float Reg %i as %x, %08f\n",
tid, reg_idx, floatRegs.i[tid][reg_idx], floatRegs.f[tid][reg_idx]);
return floatRegs.i[tid][reg_idx];
}
@ -1199,6 +1210,11 @@ void
InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
{
floatRegs.f[tid][reg_idx] = val;
DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
"%x, %08f\n",
tid, reg_idx,
floatRegs.i[tid][reg_idx],
floatRegs.f[tid][reg_idx]);
}
@ -1206,6 +1222,11 @@ void
InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
{
floatRegs.i[tid][reg_idx] = val;
DPRINTF(FloatRegs, "[tid:%i]: Setting Float. Reg %i bits to "
"%x, %08f\n",
tid, reg_idx,
floatRegs.i[tid][reg_idx],
floatRegs.f[tid][reg_idx]);
}
uint64_t
@ -1257,6 +1278,11 @@ InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
MiscReg
InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
{
DPRINTF(InOrderCPU, "MiscReg: %i\n", misc_reg);
DPRINTF(InOrderCPU, "tid: %i\n", tid);
DPRINTF(InOrderCPU, "tcBase: %x\n", tcBase(tid));
DPRINTF(InOrderCPU, "isa-tid: %x\n", &isa[tid]);
return isa[tid].readMiscReg(misc_reg, tcBase(tid));
}

6
src/cpu/inorder/cpu.hh
View file

@ -262,17 +262,11 @@ class InOrderCPU : public BaseCPU
*/
unsigned fetchPortIdx;
/** Identifies the resource id that identifies a ITB */
unsigned itbIdx;
/** Identifies the resource id that identifies a data
* access unit.
*/
unsigned dataPortIdx;
/** Identifies the resource id that identifies a DTB */
unsigned dtbIdx;
/** The Pipeline Stages for the CPU */
PipelineStage *pipelineStage[ThePipeline::NumStages];

57
src/cpu/inorder/inorder_dyn_inst.cc
View file

@ -69,8 +69,6 @@ InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
lqIdx(0), sqIdx(0), instListIt(NULL), onInstList(false)
{
for(int i = 0; i < MaxInstSrcRegs; i++) {
instSrc[i].integer = 0;
instSrc[i].dbl = 0;
_readySrcRegIdx[i] = false;
_srcRegIdx[i] = 0;
}
@ -124,9 +122,6 @@ InOrderDynInst::initVars()
nextStage = 0;
for(int i = 0; i < MaxInstDestRegs; i++)
instResult[i].val.integer = 0;
status.reset();
memAddrReady = false;
@ -355,39 +350,48 @@ InOrderDynInst::releaseReq(ResourceRequest* req)
void
InOrderDynInst::setIntSrc(int idx, uint64_t val)
{
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i being set "
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] Int being set "
"to %#x.\n", threadNumber, seqNum, idx, val);
instSrc[idx].integer = val;
instSrc[idx].intVal = val;
}
/** Records an fp register being set to a value. */
void
InOrderDynInst::setFloatSrc(int idx, FloatReg val)
{
instSrc[idx].dbl = val;
instSrc[idx].fpVal.f = val;
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FP being set "
"to %x, %08f...%08f\n", threadNumber, seqNum, idx,
instSrc[idx].fpVal.i, instSrc[idx].fpVal.f, val);
}
/** Records an fp register being set to an integer value. */
void
InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
InOrderDynInst::setFloatRegBitsSrc(int idx, FloatRegBits val)
{
instSrc[idx].integer = val;
instSrc[idx].fpVal.i = val;
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FPBits being set "
"to %x, %08f...%x\n", threadNumber, seqNum, idx,
instSrc[idx].fpVal.i, instSrc[idx].fpVal.f, val);
}
/** Reads a integer register. */
IntReg
InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
{
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
threadNumber, seqNum, idx, instSrc[idx].integer);
return instSrc[idx].integer;
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] IntVal read as %#x.\n",
threadNumber, seqNum, idx, instSrc[idx].intVal);
return instSrc[idx].intVal;
}
/** Reads a FP register. */
FloatReg
InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
{
return instSrc[idx].dbl;
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FPVal being read "
"as %x, %08f.\n", threadNumber, seqNum, idx,
instSrc[idx].fpVal.i, instSrc[idx].fpVal.f);
return instSrc[idx].fpVal.f;
}
@ -395,7 +399,10 @@ InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx)
FloatRegBits
InOrderDynInst::readFloatRegOperandBits(const StaticInst *si, int idx)
{
return instSrc[idx].integer;
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] [src:%i] FPBits being read "
"as %x, %08f.\n", threadNumber, seqNum, idx,
instSrc[idx].fpVal.i, instSrc[idx].fpVal.f);
return instSrc[idx].fpVal.i;
}
/** Reads a miscellaneous register. */
@ -414,8 +421,8 @@ InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
{
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
" read as %#x.\n", threadNumber, seqNum, idx,
instSrc[idx].integer);
return instSrc[idx].integer;
instSrc[idx].intVal);
return instSrc[idx].intVal;
}
@ -427,7 +434,7 @@ InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val)
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].res.intVal = val;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
@ -457,7 +464,7 @@ void
InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].res.intVal = val;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
@ -469,13 +476,13 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
void
InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
instResult[idx].val.dbl = val;
instResult[idx].res.fpVal.f = val;
instResult[idx].type = Float;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
"being set to %#x (result-tick:%i).\n",
threadNumber, seqNum, idx, val, instResult[idx].tick);
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Result Float Reg. %i "
"being set to %#x, %08f (result-tick:%i).\n",
threadNumber, seqNum, idx, val, val, instResult[idx].tick);
}
/** Sets a FP register as a integer. */
@ -484,10 +491,10 @@ InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val)
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].res.fpVal.i = val;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Result Float Reg. Bits %i "
"being set to %#x (result-tick:%i).\n",
threadNumber, seqNum, idx, val, instResult[idx].tick);
}

45
src/cpu/inorder/inorder_dyn_inst.hh
View file

@ -89,6 +89,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
// Floating point register type.
typedef TheISA::FloatReg FloatReg;
// Floating point register type.
typedef TheISA::FloatRegBits FloatRegBits;
// Floating point register type.
typedef TheISA::MiscReg MiscReg;
typedef short int PhysRegIndex;
@ -207,13 +209,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
/** How many source registers are ready. */
unsigned readyRegs;
/** An instruction src/dest has to be one of these types */
union InstValue {
uint64_t integer;
double dbl;
};
//@TODO: Naming Convention for Enums?
enum ResultType {
None,
Integer,
@ -221,19 +216,30 @@ class InOrderDynInst : public FastAlloc, public RefCounted
Double
};
/** An instruction src/dest has to be one of these types */
struct InstValue {
IntReg intVal;
union {
FloatReg f;
FloatRegBits i;
} fpVal;
InstValue()
{
intVal = 0;
fpVal.i = 0;
}
};
/** Result of an instruction execution */
struct InstResult {
ResultType type;
InstValue val;
InstValue res;
Tick tick;
InstResult()
: type(None), tick(0)
{
val.integer = 0;
val.dbl = 0;
}
{ }
};
/** The source of the instruction; assumes for now that there's only one
@ -852,10 +858,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted
* source register to a value. */
void setIntSrc(int idx, uint64_t val);
void setFloatSrc(int idx, FloatReg val);
void setFloatRegBitsSrc(int idx, uint64_t val);
void setFloatRegBitsSrc(int idx, TheISA::FloatRegBits val);
uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].integer; }
uint64_t readIntSrc(int idx) { return instSrc[idx].integer; }
uint64_t* getIntSrcPtr(int idx) { return &instSrc[idx].intVal; }
uint64_t readIntSrc(int idx) { return instSrc[idx].intVal; }
/** These Instructions read a integer/float/misc. source register
* value in the instruction. The instruction's execute function will
@ -879,18 +885,17 @@ class InOrderDynInst : public FastAlloc, public RefCounted
uint64_t readIntResult(int idx)
{
return instResult[idx].val.integer;
return instResult[idx].res.intVal;
}
/** Depending on type, return Float or Double */
double readFloatResult(int idx)
FloatReg readFloatResult(int idx)
{
return instResult[idx].val.dbl;
return instResult[idx].res.fpVal.f;
}
Tick readResultTime(int idx) { return instResult[idx].tick; }
uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
uint64_t* getIntResultPtr(int idx) { return &instResult[idx].res.intVal; }
/** This is the interface that an instruction will use to write
* it's destination register.

11
src/cpu/inorder/reg_dep_map.cc
View file

@ -104,7 +104,7 @@ RegDepMap::insert(DynInstPtr inst)
inst->flattenDestReg(i, flat_idx);
if (flat_idx == TheISA::ZeroReg) {
if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
DPRINTF(RegDepMap, "[sn:%i]: Ignoring Insert-Dependency tracking for "
"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
flat_idx);
@ -143,15 +143,18 @@ RegDepMap::remove(DynInstPtr inst)
for (int i = 0; i < dest_regs; i++) {
RegIndex flat_idx = inst->flattenedDestRegIdx(i);
InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
if (flat_idx == TheISA::ZeroReg) {
// Merge Dyn Inst & CPU Result Types
if (flat_idx == TheISA::ZeroReg &&
reg_type == InOrderCPU::IntType) {
DPRINTF(RegDepMap, "[sn:%i]: Ignoring Remove-Dependency tracking for "
"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
flat_idx);
continue;
}
InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
remove(reg_type, flat_idx, inst);
}
}
@ -174,7 +177,7 @@ RegDepMap::remove(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
}
list_it++;
}
panic("[sn:%i] Did not find entry for %i ", inst->seqNum, idx);
panic("[sn:%i] Did not find entry for %i, type:%i\n", inst->seqNum, idx, reg_type);
}
void

21
src/cpu/inorder/resources/execution_unit.cc
View file

@ -142,6 +142,9 @@ ExecutionUnit::execute(int slot_num)
// Evaluate Branch
fault = inst->execute();
// Should unconditional control , pc relative count as an
// execution??? Probably not.
executions++;
if (fault == NoFault) {
@ -204,11 +207,19 @@ ExecutionUnit::execute(int slot_num)
if (fault == NoFault) {
inst->setExecuted();
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result "
"of execution is 0x%x.\n", inst->readTid(),
seq_num,
(inst->resultType(0) == InOrderDynInst::Float) ?
inst->readFloatResult(0) : inst->readIntResult(0));
#if TRACING_ON
for (int didx = 0; didx < inst->numDestRegs(); didx++)
if (inst->resultType(didx) == InOrderDynInst::Float ||
inst->resultType(didx) == InOrderDynInst::Double)
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
"of FP execution is %08f (%x).\n", inst->readTid(),
seq_num, didx, inst->readFloatResult(didx),
inst->readIntResult(didx));
else
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
"of Int execution is 0x%x.\n", inst->readTid(),
seq_num, didx, inst->readIntResult(didx));
#endif
#if !FULL_SYSTEM
// The Syscall might change the PC, so conservatively

15
src/cpu/inorder/resources/use_def.cc
View file

@ -181,7 +181,7 @@ UseDefUnit::execute(int slot_idx)
RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
inst->flattenSrcReg(ud_idx, flat_idx);
if (flat_idx == TheISA::ZeroReg) {
if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Ignoring Reading of ISA-ZeroReg "
"(Int. Reg %i).\n", tid, inst->seqNum, flat_idx);
ud_req->done();
@ -226,6 +226,9 @@ UseDefUnit::execute(int slot_idx)
inst->setFloatSrc(ud_idx,
cpu->readFloatReg(flat_idx,
inst->readTid()));
inst->setFloatRegBitsSrc(ud_idx,
cpu->readFloatRegBits(flat_idx,
inst->readTid()));
floatRegFileReads++;
}
break;
@ -238,7 +241,7 @@ UseDefUnit::execute(int slot_idx)
tid, seq_num,
reg_idx - Ctrl_Base_DepTag, flat_idx,
cpu->readMiscReg(flat_idx,
inst->readTid()));
inst->readTid()));
inst->setIntSrc(ud_idx,
cpu->readMiscReg(flat_idx,
inst->readTid()));
@ -331,7 +334,7 @@ UseDefUnit::execute(int slot_idx)
RegIndex reg_idx = inst->_destRegIdx[ud_idx];
RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
if (flat_idx == TheISA::ZeroReg) {
if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
DPRINTF(IntRegs, "[tid:%i]: Ignoring Writing of ISA-ZeroReg "
"(Int. Reg %i)\n", tid, flat_idx);
ud_req->done();
@ -374,7 +377,7 @@ UseDefUnit::execute(int slot_idx)
if (inst->resultType(ud_idx) ==
InOrderDynInst::Integer) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing FP-Bits "
"Result 0x%x (bits:0x%x) to register "
"Result %08f (bits:0x%x) to register "
"idx %i (%i).\n",
tid, seq_num,
inst->readFloatResult(ud_idx),
@ -388,7 +391,7 @@ UseDefUnit::execute(int slot_idx)
} else if (inst->resultType(ud_idx) ==
InOrderDynInst::Float) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing Float "
"Result 0x%x (bits:0x%x) to register "
"Result %08f (bits:0x%x) to register "
"idx %i (%i).\n",
tid, seq_num, inst->readFloatResult(ud_idx),
inst->readIntResult(ud_idx),
@ -400,7 +403,7 @@ UseDefUnit::execute(int slot_idx)
} else if (inst->resultType(ud_idx) ==
InOrderDynInst::Double) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing Double "
"Result 0x%x (bits:0x%x) to register "
"Result %08f (bits:0x%x) to register "
"idx %i (%i).\n",
tid, seq_num,
inst->readFloatResult(ud_idx),