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gem5/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini

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Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[root]
type=Root
children=system
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
full_system=false
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system]
type=System
children=cpu membus physmem
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
boot_osflags=a
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
clock=1000
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
init_param=0
kernel=
load_addr_mask=1099511627775
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
mem_mode=timing
mem_ranges=
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
memories=system.physmem
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
num_work_ids=16
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
readfile=
symbolfile=
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system_port=system.membus.slave[0]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system.cpu]
type=DerivO3CPU
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
LFSTSize=1024
LQEntries=32
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
LSQCheckLoads=true
LSQDepCheckShift=4
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
branchPred=system.cpu.branchPred
Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate. --HG-- extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec
2007-06-22 21:06:10 +02:00
cachePorts=200
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
checker=Null
Update refs for new CPU frequency changes. tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr: tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr: tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini: tests/quick/50.memtest/ref/alpha/linux/memtest/config.out: tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt: tests/quick/50.memtest/ref/alpha/linux/memtest/stdout: Update refs --HG-- extra : convert_revision : 8d9deb2b907843064b40e46207d9c9361941f022
2007-04-22 20:50:37 +02:00
clock=500
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
Update stats for changes. --HG-- extra : convert_revision : a24c4cd7e2fcd732f5da5679f0c0fbf205f22815
2007-03-25 07:05:48 +02:00
cpu_id=0
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
do_checkpoint_insts=true
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
do_quiesce=true
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
do_statistics_insts=true
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
dtb=system.cpu.dtb
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
interrupts=system.cpu.interrupts
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
isa=system.cpu.isa
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
issueToExecuteDelay=1
issueWidth=8
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
itb=system.cpu.itb
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
needsTSO=false
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
profile=0
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
progress_interval=0
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate. --HG-- extra : convert_revision : 33ad6a220945b344d2fc5c6abef8e67467e0c0ec
2007-06-22 21:06:10 +02:00
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
squashWidth=8
O3: Update stats for new ordering fix.
2011-09-13 18:58:09 +02:00
store_set_clear_period=250000
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
switched_out=false
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system=system
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
tracer=system.cpu.tracer
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu.workload
Update reference config.ini files to include port mappings. --HG-- extra : convert_revision : f9e91a60fa09b707d2a26be57f265b7ab1c07263
2006-09-05 22:24:47 +02:00
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system.cpu.dcache]
type=BaseCache
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
addr_ranges=0:18446744073709551615
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
assoc=2
block_size=64
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
clock=500
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=2
O3: Update stats for memory order violation checking patch.
2011-04-04 18:42:25 +02:00
is_top_level=true
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
max_miss_count=0
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
mshrs=4
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=2
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
size=262144
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
Update refs for recent changes. --HG-- extra : convert_revision : 30a02eec4d83c4e1708ed0a4e2b5faea88fe8e03
2007-03-30 22:59:40 +02:00
tgts_per_mshr=20
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
two_queue=false
write_buffers=8
Update reference config.ini files to include port mappings. --HG-- extra : convert_revision : f9e91a60fa09b707d2a26be57f265b7ab1c07263
2006-09-05 22:24:47 +02:00
cpu_side=system.cpu.dcache_port
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
mem_side=system.cpu.toL2Bus.slave[1]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
[system.cpu.dtb]
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
type=AlphaTLB
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
size=64
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system.cpu.fuPool]
type=FUPool
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system.cpu.fuPool.FUList0]
type=FUDesc
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
children=opList
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
count=6
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
opList=system.cpu.fuPool.FUList0.opList
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
[system.cpu.fuPool.FUList0.opList]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
children=opList
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
count=0
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
opList=system.cpu.fuPool.FUList4.opList
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
[system.cpu.fuPool.FUList4.opList]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
children=opList
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
count=0
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
opList=system.cpu.fuPool.FUList6.opList
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
[system.cpu.fuPool.FUList6.opList]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
[system.cpu.fuPool.FUList7]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
type=FUDesc
children=opList0 opList1
count=4
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
[system.cpu.fuPool.FUList7.opList0]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
[system.cpu.fuPool.FUList7.opList1]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
[system.cpu.fuPool.FUList8]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
type=FUDesc
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
children=opList
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
count=1
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
opList=system.cpu.fuPool.FUList8.opList
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
Regressions: Update regressions for SIMD opclass changes
2010-11-15 21:04:05 +01:00
[system.cpu.fuPool.FUList8.opList]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu.icache]
type=BaseCache
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
addr_ranges=0:18446744073709551615
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
assoc=2
block_size=64
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
clock=500
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=2
O3: Update stats for memory order violation checking patch.
2011-04-04 18:42:25 +02:00
is_top_level=true
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
max_miss_count=0
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
mshrs=4
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=2
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
size=131072
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
Update refs for recent changes. --HG-- extra : convert_revision : 30a02eec4d83c4e1708ed0a4e2b5faea88fe8e03
2007-03-30 22:59:40 +02:00
tgts_per_mshr=20
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
two_queue=false
write_buffers=8
Update reference config.ini files to include port mappings. --HG-- extra : convert_revision : f9e91a60fa09b707d2a26be57f265b7ab1c07263
2006-09-05 22:24:47 +02:00
cpu_side=system.cpu.icache_port
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
mem_side=system.cpu.toL2Bus.slave[0]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
[system.cpu.interrupts]
type=AlphaInterrupts
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
[system.cpu.isa]
type=AlphaISA
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
[system.cpu.itb]
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
type=AlphaTLB
Stats: Update the stats. --HG-- extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8
2007-08-27 05:27:53 +02:00
size=48
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system.cpu.l2cache]
type=BaseCache
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
addr_ranges=0:18446744073709551615
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
assoc=8
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
block_size=64
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
clock=500
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
2009-04-22 07:55:52 +02:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=20
O3: Update stats for memory order violation checking patch.
2011-04-04 18:42:25 +02:00
is_top_level=false
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
max_miss_count=0
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
mshrs=20
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
2009-02-16 18:09:45 +01:00
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=20
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
size=2097152
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
tgts_per_mshr=12
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
two_queue=false
write_buffers=8
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system.cpu.toL2Bus]
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
type=CoherentBus
update all the regresstion tests for release --HG-- extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
2007-05-16 01:25:35 +02:00
block_size=64
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
clock=500
Bus: Update the stats for the recent bus fix. --HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
2008-02-26 08:20:40 +01:00
header_cycles=1
regressions: stats updates due to no physmem in ruby
2013-03-07 04:57:10 +01:00
system=system
tests: update reference config.ini files for previous cset Rename 'responder_set' to 'use_default_range'.
2010-08-17 14:06:22 +02:00
use_default_range=false
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
width=32
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
tests: new ref outputs for new cache model --HG-- extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
2007-08-04 00:04:30 +02:00
[system.cpu.tracer]
type=ExeTracer
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system.cpu.workload]
type=LiveProcess
cmd=hello
Update to stats because of minor to branch mispredict accounting. --HG-- extra : convert_revision : bfb7db6bd118b623f6a38c05a962dc44456160cb
2007-01-23 08:44:44 +01:00
cwd=
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
egid=100
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
env=
Make default PhysicalMemory latency slightly more realistic. Also update stats to reflect change.
2008-08-04 00:13:29 +02:00
errout=cerr
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
euid=100
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
executable=tests/test-progs/hello/bin/alpha/tru64/hello
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
gid=100
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
input=cin
Update O3 ref outputs: very minor stats change due to previous cset. (from Steve on behalf of m5test). --HG-- extra : convert_revision : 696efdaa3dd7680dfc9c797a6a46a5053238c7d2
2008-01-15 19:13:08 +01:00
max_stack_size=67108864
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
output=cout
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
pid=100
ppid=99
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion.
2008-07-22 23:00:18 +02:00
simpoint=0
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system=system
Update refs. tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) --HG-- extra : convert_revision : d6bc241534483114def9cf88d7815ddfc9c88fd1
2006-10-07 17:32:10 +02:00
uid=100
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system.membus]
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
type=CoherentBus
update all the regresstion tests for release --HG-- extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
2007-05-16 01:25:35 +02:00
block_size=64
Updates refs. tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout: Update refs. --HG-- extra : convert_revision : 5341341507ddbe1211992e5f72013d7be0000bae
2006-10-10 17:04:05 +02:00
clock=1000
Bus: Update the stats for the recent bus fix. --HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
2008-02-26 08:20:40 +01:00
header_cycles=1
regressions: stats updates due to no physmem in ruby
2013-03-07 04:57:10 +01:00
system=system
tests: update reference config.ini files for previous cset Rename 'responder_set' to 'use_default_range'.
2010-08-17 14:06:22 +02:00
use_default_range=false
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
width=8
Regression Tests: Update statistics
2012-10-02 21:35:46 +02:00
master=system.physmem.port
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
slave=system.system_port system.cpu.l2cache.mem_side
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
[system.physmem]
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
type=SimpleDRAM
regressions: stats updates due to no physmem in ruby
2013-03-07 04:57:10 +01:00
activation_limit=4
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
addr_mapping=openmap
banks_per_rank=8
regressions: stats updates due to no physmem in ruby
2013-03-07 04:57:10 +01:00
channels=1
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
clock=1000
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
conf_table_reported=false
in_addr_map=true
regressions: stats updates due to no physmem in ruby
2013-03-07 04:57:10 +01:00
lines_per_rowbuffer=32
mem_sched_policy=frfcfs
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion.
2008-07-22 23:00:18 +02:00
null=false
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
page_policy=open
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
range=0:134217727
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
ranks_per_channel=2
read_buffer_size=32
regressions: stats updates due to no physmem in ruby
2013-03-07 04:57:10 +01:00
tBURST=5000
tCL=13750
tRCD=13750
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
tREFI=7800000
tRFC=300000
regressions: stats updates due to no physmem in ruby
2013-03-07 04:57:10 +01:00
tRP=13750
tWTR=7500
tXAW=40000
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
write_buffer_size=32
write_thresh_perc=70
Update to stats because of minor to branch mispredict accounting. --HG-- extra : convert_revision : bfb7db6bd118b623f6a38c05a962dc44456160cb
2007-01-23 08:44:44 +01:00
zero=false
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
port=system.membus.master[0]
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
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