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update all the regresstion tests for release

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--HG--
extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
This commit is contained in:
Ali Saidi 2007-05-15 19:25:35 -04:00
parent c30e615689
commit b85690e239
185 changed files with 8398 additions and 15583 deletions
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11
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -91,8 +91,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -267,8 +266,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -306,8 +304,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -339,6 +336,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -363,6 +361,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -249,7 +250,7 @@ type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -280,14 +281,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -318,14 +318,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -356,7 +355,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.toL2Bus]
type=Bus
@ -364,4 +362,5 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64

552
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 74294088 # Number of BTB hits
global.BPredUnit.BTBLookups 83217138 # Number of BTB lookups
global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 4320797 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 79655810 # Number of conditional branches predicted
global.BPredUnit.lookups 86600861 # Number of BP lookups
global.BPredUnit.usedRAS 1992384 # Number of times the RAS was used to get a target.
host_inst_rate 121760 # Simulator instruction rate (inst/s)
host_mem_usage 154560 # Number of bytes of host memory used
host_seconds 4644.82 # Real time elapsed on the host
host_tick_rate 28265671 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 20253948 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 12668807 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 134508955 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 44216516 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 65796417 # Number of BTB hits
global.BPredUnit.BTBLookups 73152793 # Number of BTB lookups
global.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 4224786 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 70143727 # Number of conditional branches predicted
global.BPredUnit.lookups 75959317 # Number of BP lookups
global.BPredUnit.usedRAS 1707904 # Number of times the RAS was used to get a target.
host_inst_rate 95235 # Simulator instruction rate (inst/s)
host_mem_usage 154544 # Number of bytes of host memory used
host_seconds 5938.47 # Real time elapsed on the host
host_tick_rate 31305923 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 11533351 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 9283325 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 125815870 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 42503953 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
sim_seconds 0.131289 # Number of seconds simulated
sim_ticks 131288904500 # Number of ticks simulated
sim_seconds 0.185909 # Number of seconds simulated
sim_ticks 185909249000 # Number of ticks simulated
system.cpu.commit.COM:branches 62547159 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 25836005 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 21750592 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 248547939
system.cpu.commit.COM:committed_per_cycle.samples 363164843
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 64112537 2579.48%
1 73997996 2977.21%
2 29649485 1192.91%
3 7413919 298.29%
4 16299890 655.80%
5 20436719 822.24%
6 3362671 135.29%
7 7438717 299.29%
8 25836005 1039.48%
0 150226418 4136.59%
1 99566964 2741.65%
2 34056070 937.76%
3 10333475 284.54%
4 20301573 559.02%
5 15829471 435.88%
6 8882909 244.60%
7 2217371 61.06%
8 21750592 598.92%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 115049510 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 154862033 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 4320164 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 4224164 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 94497449 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 52370845 # The number of squashed insts skipped by commit
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.464286 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.464286 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 115538611 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 2723.249468 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2089.628248 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114910502 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1710497500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.005436 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 628109 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 403470 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 469412000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 224639 # number of ReadReq MSHR misses
system.cpu.cpi 0.657443 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.657443 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 115591547 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3246.088003 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2434.144734 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 115095381 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1610598500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.004292 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 496166 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 273177 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 542787500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001929 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 222989 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3076.718619 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2314.396461 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 38683248 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2363144500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.019469 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 768073 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 511246 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 594399500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006510 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 256827 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 539.249147 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 250 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 319.012661 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 1172 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 632000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 1000 # number of cycles access was blocked
system.cpu.dcache.WriteReq_avg_miss_latency 3474.707454 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2824.359825 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 38691611 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2639770000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.019257 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 759710 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 502007 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 727846000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006532 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 257703 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 427.272727 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 0 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 319.928337 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 1210 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 517000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 154989932 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 2917.701274 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153593750 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 4073642000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.009008 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1396182 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 914716 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1063811500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003106 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 481466 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 155042868 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3384.385481 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153786992 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 4250368500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.008100 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1255876 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 775184 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1270633500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003100 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 480692 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 154989932 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2917.701274 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 155042868 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3384.385481 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 153593750 # number of overall hits
system.cpu.dcache.overall_miss_latency 4073642000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.009008 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1396182 # number of overall misses
system.cpu.dcache.overall_mshr_hits 914716 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1063811500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003106 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 481466 # number of overall MSHR misses
system.cpu.dcache.overall_hits 153786992 # number of overall hits
system.cpu.dcache.overall_miss_latency 4250368500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.008100 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1255876 # number of overall misses
system.cpu.dcache.overall_mshr_hits 775184 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1270633500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003100 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 480692 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 477370 # number of replacements
system.cpu.dcache.sampled_refs 481466 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 476596 # number of replacements
system.cpu.dcache.sampled_refs 480692 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.510322 # Cycle average of tags in use
system.cpu.dcache.total_refs 153593750 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 24474000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 338333 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 34835558 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 676 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 4837262 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 747469994 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 87926948 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 115162373 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 14029871 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 2002 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 10623061 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 86600861 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 72219408 # Number of cache lines fetched
system.cpu.fetch.Cycles 200341434 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 435 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 760297798 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 4883794 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.329810 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 72219408 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 76286472 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.895514 # Number of inst fetches per cycle
system.cpu.dcache.tagsinuse 4095.610639 # Cycle average of tags in use
system.cpu.dcache.total_refs 153786992 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 28323000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 338024 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 44010110 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 636 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3910489 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 686828869 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 203536444 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 106139742 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8653682 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1958 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 9478548 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 75959317 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 65390933 # Number of cache lines fetched
system.cpu.fetch.Cycles 182129217 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 2901518 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 693889852 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 4411999 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.204291 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 65390933 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 67504321 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.866206 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 262577811
system.cpu.fetch.rateDist.samples 371818526
system.cpu.fetch.rateDist.min_value 0
0 134455787 5120.61%
1 11289278 429.94%
2 12199345 464.60%
3 11605085 441.97%
4 7894720 300.66%
5 3823699 145.62%
6 3913283 149.03%
7 3555410 135.40%
8 73841204 2812.16%
0 255080243 6860.34%
1 9944321 267.45%
2 12043396 323.91%
3 10077209 271.02%
4 7005486 188.41%
5 3160802 85.01%
6 3551742 95.52%
7 3151910 84.77%
8 67803417 1823.56%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 72219408 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 4241.833509 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3311.810155 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 72218459 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 4025500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 949 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 3000500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 906 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 65390933 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5347.983454 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4573.991031 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 65389966 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 5171500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 967 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 4080000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 892 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 79711.323400 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 73307.136771 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 72219408 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 4241.833509 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency
system.cpu.icache.demand_hits 72218459 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 4025500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
system.cpu.icache.demand_misses 949 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3000500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 906 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 65390933 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5347.983454 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency
system.cpu.icache.demand_hits 65389966 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 5171500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000015 # miss rate for demand accesses
system.cpu.icache.demand_misses 967 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 4080000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 892 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 72219408 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 4241.833509 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency
system.cpu.icache.overall_accesses 65390933 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5347.983454 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 72218459 # number of overall hits
system.cpu.icache.overall_miss_latency 4025500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
system.cpu.icache.overall_misses 949 # number of overall misses
system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3000500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 906 # number of overall MSHR misses
system.cpu.icache.overall_hits 65389966 # number of overall hits
system.cpu.icache.overall_miss_latency 5171500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000015 # miss rate for overall accesses
system.cpu.icache.overall_misses 967 # number of overall misses
system.cpu.icache.overall_mshr_hits 75 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 4080000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 892 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -215,63 +215,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 34 # number of replacements
system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks.
system.cpu.icache.replacements 33 # number of replacements
system.cpu.icache.sampled_refs 892 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 774.513861 # Cycle average of tags in use
system.cpu.icache.total_refs 72218459 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 761.711791 # Cycle average of tags in use
system.cpu.icache.total_refs 65389966 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 997 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 69153659 # Number of branches executed
system.cpu.iew.EXEC:nop 45896023 # number of nop insts executed
system.cpu.iew.EXEC:rate 2.341699 # Inst execution rate
system.cpu.iew.EXEC:refs 168426251 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 41748280 # Number of stores executed
system.cpu.idleCycles 2468 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 67136036 # Number of branches executed
system.cpu.iew.EXEC:nop 41949449 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.608660 # Inst execution rate
system.cpu.iew.EXEC:refs 164353457 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 41112797 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 525987328 # num instructions consuming a value
system.cpu.iew.WB:count 611675009 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.792003 # average fanout of values written-back
system.cpu.iew.WB:consumers 478961290 # num instructions consuming a value
system.cpu.iew.WB:count 594114153 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.812310 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 416583352 # num instructions producing a value
system.cpu.iew.WB:rate 2.329500 # insts written-back per cycle
system.cpu.iew.WB:sent 613682130 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4878985 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 11826 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 134508955 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2507193 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 44216516 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 696353635 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 126677971 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 11034988 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 614878076 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 389064913 # num instructions producing a value
system.cpu.iew.WB:rate 1.597861 # insts written-back per cycle
system.cpu.iew.WB:sent 594699658 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 4485637 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 10981 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 125815870 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6586227 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 42503953 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 654225210 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 123240660 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4346710 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 598129643 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 518 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 14029871 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 4036 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 8653682 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 4417 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 4056 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 10594878 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 23131 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 2615 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 7105932 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 1847 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 1076564 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 5809 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 19459445 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 4403993 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 1076564 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 574744 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4304241 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 2.153847 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.153847 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 625913064 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 296430 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 5860 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 10766360 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 2691430 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 296430 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 519296 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3966341 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.521044 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.521044 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 602476353 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
IntAlu 452893161 72.36% # Type of FU issued
IntMult 6537 0.00% # Type of FU issued
IntAlu 435905994 72.35% # Type of FU issued
IntMult 6492 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 27 0.00% # Type of FU issued
FloatCmp 5 0.00% # Type of FU issued
@ -279,17 +279,17 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 4 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 130507417 20.85% # Type of FU issued
MemWrite 42505908 6.79% # Type of FU issued
MemRead 124769613 20.71% # Type of FU issued
MemWrite 41794213 6.94% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 6267821 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.010014 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 3485464 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.005785 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 5230779 83.45% # attempts to use FU when none available
IntMult 183 0.00% # attempts to use FU when none available
IntAlu 2980889 85.52% # attempts to use FU when none available
IntMult 104 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
@ -297,80 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 663118 10.58% # attempts to use FU when none available
MemWrite 373741 5.96% # attempts to use FU when none available
MemRead 331227 9.50% # attempts to use FU when none available
MemWrite 173244 4.97% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 262577811
system.cpu.iq.ISSUE:issued_per_cycle.samples 371818526
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 49543053 1886.80%
1 42653619 1624.42%
2 65996372 2513.40%
3 28722982 1093.88%
4 36210264 1379.03%
5 20379063 776.12%
6 16095665 612.99%
7 2026950 77.19%
8 949843 36.17%
0 125625601 3378.68%
1 89616652 2410.23%
2 55904072 1503.53%
3 46310572 1245.52%
4 27240019 732.62%
5 12675210 340.90%
6 11517465 309.76%
7 2752555 74.03%
8 176380 4.74%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 2.383724 # Inst issue rate
system.cpu.iq.iqInstsAdded 650457589 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 625913064 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 83477196 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 265708 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 44589775 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 482372 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 5974.559204 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2202.761362 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 456056 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 157226500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.054555 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 26316 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 57967868 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054555 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 26316 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 338333 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 338333 # number of Writeback hits
system.cpu.iq.ISSUE:rate 1.620351 # Inst issue rate
system.cpu.iq.iqInstsAdded 612275739 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 602476353 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 42659982 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 2623 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 21979774 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 481584 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 6174.721472 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2416.099471 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 455285 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 162389000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.054609 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 26299 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 63541000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054609 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 26299 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 338024 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 338024 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 30.186541 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 30.164987 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 482372 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 5974.559204 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 456056 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 157226500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.054555 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 26316 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 481584 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 6174.721472 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 455285 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 162389000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.054609 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 26299 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 57967868 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.054555 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 26316 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 63541000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.054609 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 26299 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 820705 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 5974.559204 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 819608 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 6174.721472 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 794389 # number of overall hits
system.cpu.l2cache.overall_miss_latency 157226500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.032065 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 26316 # number of overall misses
system.cpu.l2cache.overall_hits 793309 # number of overall hits
system.cpu.l2cache.overall_miss_latency 162389000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.032087 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 26299 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 57967868 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.032065 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 26316 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 63541000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.032087 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 26299 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -382,31 +382,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 932 # number of replacements
system.cpu.l2cache.sampled_refs 26316 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 931 # number of replacements
system.cpu.l2cache.sampled_refs 26299 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 25073.756706 # Cycle average of tags in use
system.cpu.l2cache.total_refs 794389 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 25071.267749 # Cycle average of tags in use
system.cpu.l2cache.total_refs 793309 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 904 # number of writebacks
system.cpu.numCycles 262577811 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 2682297 # Number of cycles rename is blocking
system.cpu.numCycles 371818526 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 11517489 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 30243185 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 96498295 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1942834 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 952429183 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 727912324 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 552445892 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 117213862 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 14029871 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 32153216 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 88591003 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 50706382 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 32462126 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 206624315 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 21712 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 889109667 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 674900294 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 515718683 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 111518348 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 8653682 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 33504424 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 51863794 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 268 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 59569309 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 24 # count of temporary serializing insts renamed
system.cpu.timesIdled 32 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

1
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 964119 # Simulator instruction rate (inst/s)
host_mem_usage 148524 # Number of bytes of host memory used
host_seconds 624.26 # Real time elapsed on the host
host_tick_rate 482059313 # Simulator tick rate (ticks/s)
host_inst_rate 963880 # Simulator instruction rate (inst/s)
host_mem_usage 148548 # Number of bytes of host memory used
host_seconds 624.41 # Real time elapsed on the host
host_tick_rate 481939681 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856965 # Number of instructions simulated
sim_seconds 0.300928 # Number of seconds simulated

11
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

102
tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 642291 # Simulator instruction rate (inst/s)
host_mem_usage 153996 # Number of bytes of host memory used
host_seconds 937.05 # Real time elapsed on the host
host_tick_rate 404322160 # Simulator tick rate (ticks/s)
host_inst_rate 494073 # Simulator instruction rate (inst/s)
host_mem_usage 153964 # Number of bytes of host memory used
host_seconds 1218.16 # Real time elapsed on the host
host_tick_rate 624626994 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856965 # Number of instructions simulated
sim_seconds 0.378869 # Number of seconds simulated
sim_ticks 378869140000 # Number of ticks simulated
sim_seconds 0.760893 # Number of seconds simulated
sim_ticks 760892614000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 2584.255983 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1584.255983 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 12040.967639 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11040.967639 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 520035000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 2423028000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 318803000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 2221796000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 2608.788455 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1608.788455 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 12166.766996 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11166.766996 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 663057500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 3092342000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 408894500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2838179000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 2597.947935 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 12111.178208 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency
system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1183092500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 5515370000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses
system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 727697500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 5059975000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2597.947935 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 12111.178208 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 153509968 # number of overall hits
system.cpu.dcache.overall_miss_latency 1183092500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 5515370000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses
system.cpu.dcache.overall_misses 455395 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 727697500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 5059975000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.423304 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.250869 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 102411000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 257148000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 325723 # number of writebacks
system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3746.540881 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2746.540881 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 13969.811321 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12969.811321 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 2978500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 11106000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 2183500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 10311000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3746.540881 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 13969.811321 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency
system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 2978500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 11106000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2183500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 10311000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3746.540881 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 13969.811321 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 601856171 # number of overall hits
system.cpu.icache.overall_miss_latency 2978500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 11106000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 795 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2183500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 10311000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 674.110982 # Cycle average of tags in use
system.cpu.icache.tagsinuse 673.943506 # Cycle average of tags in use
system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2564.564334 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1563.181738 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 66930000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 339274000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 40795917 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 287078000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2564.564334 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 66930000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 339274000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 40795917 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 287078000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2564.564334 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 755815 # number of overall hits
system.cpu.l2cache.overall_miss_latency 66930000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 339274000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 26098 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 40795917 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 287078000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 903 # number of replacements
system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 24878.910085 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 24875.090462 # Cycle average of tags in use
system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 883 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 378869140000 # number of cpu cycles simulated
system.cpu.numCycles 760892614000 # number of cpu cycles simulated
system.cpu.num_insts 601856965 # Number of instructions executed
system.cpu.num_refs 154862034 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls

1
tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 687229 # Simulator instruction rate (inst/s)
host_mem_usage 149588 # Number of bytes of host memory used
host_seconds 2167.42 # Real time elapsed on the host
host_tick_rate 343614381 # Simulator tick rate (ticks/s)
host_inst_rate 723585 # Simulator instruction rate (inst/s)
host_mem_usage 149576 # Number of bytes of host memory used
host_seconds 2058.52 # Real time elapsed on the host
host_tick_rate 361792205 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514860 # Number of instructions simulated
sim_seconds 0.744757 # Number of seconds simulated

4
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout
View file

@ -36,8 +36,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 27 2007 14:35:32
M5 started Fri Apr 27 14:35:40 2007
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 13:02:33 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

11
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

110
tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 510352 # Simulator instruction rate (inst/s)
host_mem_usage 155048 # Number of bytes of host memory used
host_seconds 2918.60 # Real time elapsed on the host
host_tick_rate 353062922 # Simulator tick rate (ticks/s)
host_inst_rate 529254 # Simulator instruction rate (inst/s)
host_mem_usage 154916 # Number of bytes of host memory used
host_seconds 2814.36 # Real time elapsed on the host
host_tick_rate 733354350 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489514860 # Number of instructions simulated
sim_seconds 1.030450 # Number of seconds simulated
sim_ticks 1030449926500 # Number of ticks simulated
sim_seconds 2.063927 # Number of seconds simulated
sim_ticks 2063926516000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 2729.300186 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1729.300186 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 12044.273310 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11044.273310 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 528065000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 2330326000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 334585000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 2136846000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 3071.428571 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2071.428571 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_miss_latency 12285.714286 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11285.714286 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 21500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency 86000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 14500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency 79000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 2724.587576 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1724.587576 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 12168.472925 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11168.472925 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 707698000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 3160700000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 447953000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2900955000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 2726.599371 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 12115.452590 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency
system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1235763000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 5491026000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses
system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 782538000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 5037801000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2726.599371 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 12115.452590 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 568905105 # number of overall hits
system.cpu.dcache.overall_miss_latency 1235763000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 5491026000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses
system.cpu.dcache.overall_misses 453225 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 782538000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 5037801000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 449136 # number of replacements
system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.694265 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.630445 # Cycle average of tags in use
system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 112631000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 274426000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 316447 # number of writebacks
system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3687.613843 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2687.613843 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 13859.744991 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12859.744991 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 4049000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 15218000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 2951000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 14120000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3687.613843 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 13859.744991 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency
system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 4049000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 15218000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2951000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 14120000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3687.613843 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 13859.744991 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1489513763 # number of overall hits
system.cpu.icache.overall_miss_latency 4049000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 15218000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 1098 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2951000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 14120000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 115 # number of replacements
system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 891.763656 # Cycle average of tags in use
system.cpu.icache.tagsinuse 891.684170 # Cycle average of tags in use
system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2631.120103 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1629.899651 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 71527000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 353405000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 44308822 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 299035000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses)
@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2631.120103 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 71527000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 353405000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 44308822 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 299035000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2630.249320 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 12995.697580 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 743583 # number of overall hits
system.cpu.l2cache.overall_miss_latency 71527000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 353405000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 27194 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 44308822 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 299035000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 2632 # number of replacements
system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 24268.399126 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 24267.041661 # Cycle average of tags in use
system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 2531 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1030449926500 # number of cpu cycles simulated
system.cpu.numCycles 2063926516000 # number of cpu cycles simulated
system.cpu.num_insts 1489514860 # Number of instructions executed
system.cpu.num_refs 569359656 # Number of memory references
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls

6
tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout
View file

@ -36,9 +36,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 27 2007 14:35:32
M5 started Fri Apr 27 14:35:40 2007
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 13:36:53 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1030449926500 because target called exit()
Exiting @ tick 2063926516000 because target called exit()

1
tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 658093 # Simulator instruction rate (inst/s)
host_mem_usage 149896 # Number of bytes of host memory used
host_seconds 2613.00 # Real time elapsed on the host
host_tick_rate 329046277 # Simulator tick rate (ticks/s)
host_inst_rate 686638 # Simulator instruction rate (inst/s)
host_mem_usage 149820 # Number of bytes of host memory used
host_seconds 2504.37 # Real time elapsed on the host
host_tick_rate 343319148 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1719594534 # Number of instructions simulated
sim_seconds 0.859797 # Number of seconds simulated

4
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout
View file

@ -25,8 +25,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 27 2007 14:35:32
M5 started Fri Apr 27 15:11:49 2007
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 14:23:47 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

11
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

112
tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 462859 # Simulator instruction rate (inst/s)
host_mem_usage 155288 # Number of bytes of host memory used
host_seconds 3715.16 # Real time elapsed on the host
host_tick_rate 345995852 # Simulator tick rate (ticks/s)
host_inst_rate 480485 # Simulator instruction rate (inst/s)
host_mem_usage 155316 # Number of bytes of host memory used
host_seconds 3578.87 # Real time elapsed on the host
host_tick_rate 745845171 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1719594534 # Number of instructions simulated
sim_seconds 1.285430 # Number of seconds simulated
sim_ticks 1285429818500 # Number of ticks simulated
sim_seconds 2.669285 # Number of seconds simulated
sim_ticks 2669284585000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3129.930590 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2129.930590 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 12893.226605 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11893.226605 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 40901091000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 168485217000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 27833360000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 155417486000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 3090.909091 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2090.909091 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_miss_latency 13090.909091 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 12090.909091 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 34000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency 144000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 23000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency 133000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 2764.531806 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1764.531806 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 12404.292450 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11404.292450 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4719047500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 21174090000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3012050500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 19467093000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3087.714271 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 12836.737637 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency
system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 45620138500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 189659307000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses
system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 30845410500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 174884579000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3087.714271 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 12836.737637 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 760003458 # number of overall hits
system.cpu.dcache.overall_miss_latency 45620138500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 189659307000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses
system.cpu.dcache.overall_misses 14774728 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 30845410500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 174884579000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 14770643 # number of replacements
system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4094.607725 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4094.628585 # Cycle average of tags in use
system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1932183000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 3913237000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 4191356 # number of writebacks
system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3753.607103 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2753.607103 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 13991.120977 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12991.120977 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 3382000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 12606000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 2481000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 11705000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3753.607103 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 13991.120977 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency
system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 3382000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 12606000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
system.cpu.icache.demand_misses 901 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2481000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 11705000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3753.607103 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 13991.120977 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1719593634 # number of overall hits
system.cpu.icache.overall_miss_latency 3382000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 12606000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
system.cpu.icache.overall_misses 901 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2481000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 11705000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 31 # number of replacements
system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 737.434314 # Cycle average of tags in use
system.cpu.icache.tagsinuse 737.715884 # Cycle average of tags in use
system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2607.028468 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1605.780536 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 12999.785859 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.785859 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 16118879000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 80375791000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 9928308213 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 68010081000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses)
@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2607.028468 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 12999.785859 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 16118879000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 80375791000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 9928308213 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 68010081000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2595.599252 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 12942.794779 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 12756915 # number of overall hits
system.cpu.l2cache.overall_miss_latency 16118879000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 80375791000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 6210080 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 9928308213 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 68010081000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 6150087 # number of replacements
system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 26097.875810 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 26129.060966 # Cycle average of tags in use
system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 390549075000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.warmup_cycle 806915893000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1069081 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1285429818500 # number of cpu cycles simulated
system.cpu.numCycles 2669284585000 # number of cpu cycles simulated
system.cpu.num_insts 1719594534 # Number of instructions executed
system.cpu.num_refs 774793634 # Number of memory references
system.cpu.workload.PROG:num_syscalls 632 # Number of system calls

6
tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout
View file

@ -25,9 +25,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 27 2007 14:35:32
M5 started Fri Apr 27 15:24:20 2007
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 15:05:32 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1285429818500 because target called exit()
Exiting @ tick 2669284585000 because target called exit()

11
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -91,8 +91,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -267,8 +266,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -306,8 +304,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -339,6 +336,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -363,6 +361,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -249,7 +250,7 @@ type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -280,14 +281,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -318,14 +318,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -356,7 +355,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.toL2Bus]
type=Bus
@ -364,4 +362,5 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64

556
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,112 +1,112 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 38358431 # Number of BTB hits
global.BPredUnit.BTBLookups 50162851 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1146 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 6112182 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 38942362 # Number of conditional branches predicted
global.BPredUnit.lookups 68824046 # Number of BP lookups
global.BPredUnit.usedRAS 14094584 # Number of times the RAS was used to get a target.
host_inst_rate 88313 # Simulator instruction rate (inst/s)
host_mem_usage 157144 # Number of bytes of host memory used
host_seconds 4252.75 # Real time elapsed on the host
host_tick_rate 26084457 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 79078987 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 58020753 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 131723270 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 96432918 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 36408912 # Number of BTB hits
global.BPredUnit.BTBLookups 43706931 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1105 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 5391565 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 33884568 # Number of conditional branches predicted
global.BPredUnit.lookups 59377619 # Number of BP lookups
global.BPredUnit.usedRAS 11768977 # Number of times the RAS was used to get a target.
host_inst_rate 72337 # Simulator instruction rate (inst/s)
host_mem_usage 157124 # Number of bytes of host memory used
host_seconds 5192.02 # Real time elapsed on the host
host_tick_rate 28301038 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 55015552 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 43012918 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 120933927 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 90962569 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574812 # Number of instructions simulated
sim_seconds 0.110931 # Number of seconds simulated
sim_ticks 110930737500 # Number of ticks simulated
system.cpu.commit.COM:branches 44587533 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 15191652 # number cycles where commit BW limit reached
sim_insts 375574819 # Number of instructions simulated
sim_seconds 0.146939 # Number of seconds simulated
sim_ticks 146939447000 # Number of ticks simulated
system.cpu.commit.COM:branches 44587532 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 12019969 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 203296876
system.cpu.commit.COM:committed_per_cycle.samples 280687503
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 83055980 4085.45%
1 37801777 1859.44%
2 20090473 988.23%
3 18525905 911.27%
4 11216575 551.73%
5 8853752 435.51%
6 5489461 270.02%
7 3071301 151.07%
8 15191652 747.26%
0 153383398 5464.56%
1 43042738 1533.48%
2 19983570 711.95%
3 20747693 739.17%
4 12078292 430.31%
5 11042042 393.39%
6 5000100 178.14%
7 3389701 120.76%
8 12019969 428.23%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 398664587 # Number of instructions committed
system.cpu.commit.COM:count 398664594 # Number of instructions committed
system.cpu.commit.COM:loads 100651995 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 174183397 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 6107953 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions
system.cpu.commit.branchMispredicts 5387368 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 122897297 # The number of squashed insts skipped by commit
system.cpu.committedInsts 375574812 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated
system.cpu.cpi 0.590725 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.590725 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 96817111 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4478.552279 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3669.007021 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 96815619 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 6682000 # number of ReadReq miss cycles
system.cpu.commit.commitSquashedInsts 80492961 # The number of squashed insts skipped by commit
system.cpu.committedInsts 375574819 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
system.cpu.cpi 0.782478 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.782478 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 96341397 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5402.232747 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4689.672802 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 96339919 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 7984500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1492 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 495 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 3658000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_misses 1478 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 4586500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 997 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 978 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 4580.037179 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3751.017852 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73511046 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 44348500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000132 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 9683 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 6490 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 11977000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 5858.789942 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4984.052533 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73511622 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 53356000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000124 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 9107 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 5909 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 15939000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 3198 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40650.755370 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 40673.261734 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 170337840 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 4566.487696 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency
system.cpu.dcache.demand_hits 170326665 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 51030500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000066 # miss rate for demand accesses
system.cpu.dcache.demand_misses 11175 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6985 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 15635000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_accesses 169862126 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 5795.040151 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency
system.cpu.dcache.demand_hits 169851541 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 61340500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000062 # miss rate for demand accesses
system.cpu.dcache.demand_misses 10585 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6409 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 20525500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4190 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 170337840 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 4566.487696 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 169862126 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 5795.040151 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 170326665 # number of overall hits
system.cpu.dcache.overall_miss_latency 51030500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000066 # miss rate for overall accesses
system.cpu.dcache.overall_misses 11175 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6985 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 15635000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_hits 169851541 # number of overall hits
system.cpu.dcache.overall_miss_latency 61340500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000062 # miss rate for overall accesses
system.cpu.dcache.overall_misses 10585 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6409 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 20525500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4190 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 787 # number of replacements
system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 781 # number of replacements
system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3304.118717 # Cycle average of tags in use
system.cpu.dcache.total_refs 170326665 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 3294.483088 # Cycle average of tags in use
system.cpu.dcache.total_refs 169851541 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 642 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 19129336 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4391 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 12122968 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 582055742 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 80258799 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 100428895 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 18564601 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 12469 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 3479847 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 68824046 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 70113587 # Number of cache lines fetched
system.cpu.fetch.Cycles 177754526 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1413 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 605291130 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 6551564 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.310212 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 70113587 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 52453015 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.728239 # Number of inst fetches per cycle
system.cpu.dcache.writebacks 637 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 7091571 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 4262 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 10528111 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 508290393 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 182764130 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 90473414 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 13191511 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 12840 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 358389 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 59377619 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 61063139 # Number of cache lines fetched
system.cpu.fetch.Cycles 154416855 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 2298760 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 522129068 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 5723447 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.202048 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 61063139 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 48177889 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.776680 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 221861478
system.cpu.fetch.rateDist.samples 293879015
system.cpu.fetch.rateDist.min_value 0
0 114220541 5148.28%
1 8239331 371.37%
2 8549373 385.35%
3 6969058 314.12%
4 16046109 723.25%
5 8875051 400.03%
6 9195050 414.45%
7 2819832 127.10%
8 46947133 2116.06%
0 200525300 6823.40%
1 7846897 267.01%
2 7291722 248.12%
3 6200462 210.99%
4 13845529 471.13%
5 7438768 253.12%
6 7492914 254.97%
7 2335483 79.47%
8 40901940 1391.80%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 70113587 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3851.773227 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2889.186432 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 70109583 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 15422500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000057 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4004 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 11328500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000056 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3921 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 61063139 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5151.654640 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4230.492813 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 61059120 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 20704500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000066 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4019 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 16482000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 17880.536343 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 15672.258727 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 70113587 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3851.773227 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency
system.cpu.icache.demand_hits 70109583 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 15422500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000057 # miss rate for demand accesses
system.cpu.icache.demand_misses 4004 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 11328500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000056 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3921 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 61063139 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5151.654640 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency
system.cpu.icache.demand_hits 61059120 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 20704500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000066 # miss rate for demand accesses
system.cpu.icache.demand_misses 4019 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 16482000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 70113587 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3851.773227 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency
system.cpu.icache.overall_accesses 61063139 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5151.654640 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 70109583 # number of overall hits
system.cpu.icache.overall_miss_latency 15422500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000057 # miss rate for overall accesses
system.cpu.icache.overall_misses 4004 # number of overall misses
system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 11328500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000056 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3921 # number of overall MSHR misses
system.cpu.icache.overall_hits 61059120 # number of overall hits
system.cpu.icache.overall_miss_latency 20704500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000066 # miss rate for overall accesses
system.cpu.icache.overall_misses 4019 # number of overall misses
system.cpu.icache.overall_mshr_hits 123 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 16482000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1998 # number of replacements
system.cpu.icache.sampled_refs 3921 # Sample count of references to valid blocks.
system.cpu.icache.replacements 1976 # number of replacements
system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1828.295849 # Cycle average of tags in use
system.cpu.icache.total_refs 70109583 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1822.947356 # Cycle average of tags in use
system.cpu.icache.total_refs 61059120 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles -2 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 52992725 # Number of branches executed
system.cpu.iew.EXEC:nop 29946505 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.944645 # Inst execution rate
system.cpu.iew.EXEC:refs 194719104 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 80042784 # Number of stores executed
system.cpu.idleCycles 6367 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 50329288 # Number of branches executed
system.cpu.iew.EXEC:nop 26718868 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.409679 # Inst execution rate
system.cpu.iew.EXEC:refs 190324589 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 79889528 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 297392817 # num instructions consuming a value
system.cpu.iew.WB:count 427980775 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.704330 # average fanout of values written-back
system.cpu.iew.WB:consumers 266244037 # num instructions consuming a value
system.cpu.iew.WB:count 411128901 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.717332 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 209462789 # num instructions producing a value
system.cpu.iew.WB:rate 1.929045 # insts written-back per cycle
system.cpu.iew.WB:sent 430386834 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6770153 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 2285856 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 131723270 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 248 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6165269 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 96432918 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 521561792 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 114676320 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 13198323 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 431441879 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 131901 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 190985280 # num instructions producing a value
system.cpu.iew.WB:rate 1.398973 # insts written-back per cycle
system.cpu.iew.WB:sent 411485990 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6032644 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1137801 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 120933927 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 222 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6771454 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 90962569 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 479157588 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 110435061 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10298797 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 414275208 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 25295 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 18564601 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 554549 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 21083 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 13191511 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 115109 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 10646448 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 56371 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 7097511 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 3223 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 636490 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 215134 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 31071275 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 22901516 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 636490 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 1000963 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5769190 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.692835 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.692835 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 444640202 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 404889 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 176320 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 20281932 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 17431167 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 404889 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 802823 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5229821 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.277991 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.277991 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 424574005 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 33581 0.01% # Type of FU issued
IntAlu 177043734 39.82% # Type of FU issued
IntMult 2204532 0.50% # Type of FU issued
IntAlu 163144501 38.43% # Type of FU issued
IntMult 2125088 0.50% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 36105087 8.12% # Type of FU issued
FloatCmp 7997969 1.80% # Type of FU issued
FloatCvt 3013999 0.68% # Type of FU issued
FloatMult 17176525 3.86% # Type of FU issued
FloatDiv 1578480 0.36% # Type of FU issued
FloatAdd 34659405 8.16% # Type of FU issued
FloatCmp 7790033 1.83% # Type of FU issued
FloatCvt 2881594 0.68% # Type of FU issued
FloatMult 16618307 3.91% # Type of FU issued
FloatDiv 1566111 0.37% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 116850777 26.28% # Type of FU issued
MemWrite 82635518 18.58% # Type of FU issued
MemRead 113765764 26.80% # Type of FU issued
MemWrite 81989621 19.31% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 12556872 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.028241 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 9576176 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.022555 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 57761 0.46% # attempts to use FU when none available
IntAlu 12415 0.13% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 28133 0.22% # attempts to use FU when none available
FloatCmp 21849 0.17% # attempts to use FU when none available
FloatCvt 3461 0.03% # attempts to use FU when none available
FloatMult 3478872 27.70% # attempts to use FU when none available
FloatDiv 916669 7.30% # attempts to use FU when none available
FloatAdd 46832 0.49% # attempts to use FU when none available
FloatCmp 11338 0.12% # attempts to use FU when none available
FloatCvt 25702 0.27% # attempts to use FU when none available
FloatMult 2984764 31.17% # attempts to use FU when none available
FloatDiv 331535 3.46% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 6621449 52.73% # attempts to use FU when none available
MemWrite 1428678 11.38% # attempts to use FU when none available
MemRead 4942933 51.62% # attempts to use FU when none available
MemWrite 1220657 12.75% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 221861478
system.cpu.iq.ISSUE:issued_per_cycle.samples 293879015
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 66879354 3014.46%
1 37689855 1698.80%
2 36617552 1650.47%
3 29239458 1317.92%
4 27293259 1230.19%
5 13755301 620.00%
6 5789291 260.94%
7 3467682 156.30%
8 1129726 50.92%
0 129735390 4414.59%
1 52072154 1771.89%
2 39787134 1353.86%
3 29621395 1007.95%
4 21763636 740.56%
5 12600620 428.77%
6 4911147 167.11%
7 2561440 87.16%
8 826099 28.11%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 2.004134 # Inst issue rate
system.cpu.iq.iqInstsAdded 491615039 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 444640202 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 248 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 114649126 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1134366 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 83844967 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 8108 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3327.551159 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1909.064236 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 729 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 24554000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.910089 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 7379 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 14086985 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910089 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 7379 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 642 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 642 # number of Writeback hits
system.cpu.iq.ISSUE:rate 1.444724 # Inst issue rate
system.cpu.iq.iqInstsAdded 452438498 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 424574005 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 222 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 75756994 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1109878 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 55099010 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4677.770224 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2436.233855 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 715 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 34405000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.911400 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 7355 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 17918500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911400 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 7355 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 637 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 637 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.185798 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.183821 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 8108 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3327.551159 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 729 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 24554000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.910089 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7379 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4677.770224 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 715 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 34405000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.911400 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7355 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 14086985 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.910089 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7379 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 17918500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.911400 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7355 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 8750 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3327.551159 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4677.770224 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1371 # number of overall hits
system.cpu.l2cache.overall_miss_latency 24554000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.843314 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7379 # number of overall misses
system.cpu.l2cache.overall_hits 1352 # number of overall hits
system.cpu.l2cache.overall_miss_latency 34405000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.844723 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7355 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 14086985 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.843314 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7379 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 17918500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.844723 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7355 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -383,30 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 7379 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 7355 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 6669.459869 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1371 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 6644.823451 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1352 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 221861478 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 6569281 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532333 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1971772 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 86889182 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 8681438 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 731270765 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 559458182 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 360795698 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 96896401 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 18564601 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 12635219 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 101263365 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 306794 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37801 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 32486829 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 267 # count of temporary serializing insts renamed
system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.numCycles 293879015 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 3715266 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 115195 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 185747540 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 2602652 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 654991501 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 496454048 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 320284080 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 87805227 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 13191511 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 3048084 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 60751739 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 371387 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 37057 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 7965999 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 243 # count of temporary serializing insts renamed
system.cpu.timesIdled 133 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout
View file

@ -1,2 +1,2 @@
Eon, Version 1.1
OO-style eon Time= 0.100000
OO-style eon Time= 0.133333

1
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

6
tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 844104 # Simulator instruction rate (inst/s)
host_inst_rate 828868 # Simulator instruction rate (inst/s)
host_mem_usage 151076 # Number of bytes of host memory used
host_seconds 472.29 # Real time elapsed on the host
host_tick_rate 422051705 # Simulator tick rate (ticks/s)
host_seconds 480.97 # Real time elapsed on the host
host_tick_rate 414433819 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664597 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated

11
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

142
tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,65 +1,65 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 557007 # Simulator instruction rate (inst/s)
host_mem_usage 156576 # Number of bytes of host memory used
host_seconds 715.73 # Real time elapsed on the host
host_tick_rate 396092779 # Simulator tick rate (ticks/s)
host_inst_rate 579996 # Simulator instruction rate (inst/s)
host_mem_usage 156556 # Number of bytes of host memory used
host_seconds 687.36 # Real time elapsed on the host
host_tick_rate 824955659 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664597 # Number of instructions simulated
sim_seconds 0.283494 # Number of seconds simulated
sim_ticks 283494379000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3630.526316 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2630.526316 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 94753539 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3449000 # number of ReadReq miss cycles
sim_insts 398664611 # Number of instructions simulated
sim_seconds 0.567040 # Number of seconds simulated
sim_ticks 567040254000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13741.052632 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.052632 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 13054000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2499000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 12104000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3618.988132 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2618.988132 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73517527 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 11588000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 13962.523423 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12962.523423 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 44708000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 8386000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 41506000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40527.713391 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3621.628131 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency
system.cpu.dcache.demand_hits 168271066 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 15037000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13911.849711 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency
system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 57762000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 10885000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 53610000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3621.628131 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13911.849711 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 168271066 # number of overall hits
system.cpu.dcache.overall_miss_latency 15037000 # number of overall miss cycles
system.cpu.dcache.overall_hits 168271068 # number of overall hits
system.cpu.dcache.overall_miss_latency 57762000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4152 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 10885000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 53610000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,52 +76,52 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3289.772430 # Cycle average of tags in use
system.cpu.dcache.total_refs 168271066 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 3289.654807 # Cycle average of tags in use
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 625 # number of writebacks
system.cpu.icache.ReadReq_accesses 398664598 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3633.814321 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2633.814321 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 398660925 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 13347000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_accesses 398664612 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13745.167438 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12745.167438 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 398660939 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 50486000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 9674000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 46813000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 108538.231691 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 108538.235502 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 398664598 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3633.814321 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency
system.cpu.icache.demand_hits 398660925 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 13347000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 398664612 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13745.167438 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency
system.cpu.icache.demand_hits 398660939 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 50486000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 9674000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 46813000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 398664598 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3633.814321 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency
system.cpu.icache.overall_accesses 398664612 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13745.167438 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 398660925 # number of overall hits
system.cpu.icache.overall_miss_latency 13347000 # number of overall miss cycles
system.cpu.icache.overall_hits 398660939 # number of overall hits
system.cpu.icache.overall_miss_latency 50486000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
system.cpu.icache.overall_misses 3673 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 9674000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 46813000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1769 # number of replacements
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1795.510184 # Cycle average of tags in use
system.cpu.icache.total_refs 398660925 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1795.458615 # Cycle average of tags in use
system.cpu.icache.total_refs 398660939 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2707.276275 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1705.023697 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 19422000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 93262000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 12231840 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 78914000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2707.276275 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 19422000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 93262000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 12231840 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 78914000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2707.276275 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1276 # number of overall hits
system.cpu.l2cache.overall_miss_latency 19422000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 93262000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7174 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 12231840 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 78914000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -203,14 +203,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 6483.699084 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 6483.455048 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 283494379000 # number of cpu cycles simulated
system.cpu.num_insts 398664597 # Number of instructions executed
system.cpu.num_refs 174183399 # Number of memory references
system.cpu.numCycles 567040254000 # number of cpu cycles simulated
system.cpu.num_insts 398664611 # Number of instructions executed
system.cpu.num_refs 174183401 # Number of memory references
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout
View file

@ -1,2 +1,2 @@
Eon, Version 1.1
OO-style eon Time= 0.283333
OO-style eon Time= 0.566667

1
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 855453 # Simulator instruction rate (inst/s)
host_mem_usage 151192 # Number of bytes of host memory used
host_seconds 2348.45 # Real time elapsed on the host
host_tick_rate 427726617 # Simulator tick rate (ticks/s)
host_inst_rate 855891 # Simulator instruction rate (inst/s)
host_mem_usage 151228 # Number of bytes of host memory used
host_seconds 2347.25 # Real time elapsed on the host
host_tick_rate 427945543 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987607 # Number of instructions simulated
sim_seconds 1.004494 # Number of seconds simulated

11
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

104
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 594701 # Simulator instruction rate (inst/s)
host_mem_usage 156660 # Number of bytes of host memory used
host_seconds 3378.14 # Real time elapsed on the host
host_tick_rate 405574512 # Simulator tick rate (ticks/s)
host_inst_rate 622738 # Simulator instruction rate (inst/s)
host_mem_usage 156744 # Number of bytes of host memory used
host_seconds 3226.05 # Real time elapsed on the host
host_tick_rate 852686846 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987607 # Number of instructions simulated
sim_seconds 1.370090 # Number of seconds simulated
sim_ticks 1370089513500 # Number of ticks simulated
sim_seconds 2.750814 # Number of seconds simulated
sim_ticks 2750814393000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3511.656558 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2511.656558 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 13971.031250 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12971.031250 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 5120669500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 20372446000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3662477500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 18914254000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3914.581944 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2914.581944 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 13873.860351 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12873.860351 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 281662000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 998252000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 209710000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 926300000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3530.603329 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 13966.461980 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency
system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 5402331500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 21370698000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3872187500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 19840554000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3530.603329 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 13966.461980 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 720334778 # number of overall hits
system.cpu.dcache.overall_miss_latency 5402331500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 21370698000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1530144 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3872187500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 19840554000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.457388 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4095.422371 # Cycle average of tags in use
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 325153000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 702832000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 74589 # number of writebacks
system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 2952.765194 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1952.765194 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 12448.659872 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11448.659872 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 31287500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 131906000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 20691500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 121310000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 2952.765194 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 12448.659872 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency
system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 31287500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 131906000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 20691500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 121310000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 2952.765194 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 12448.659872 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 2008977012 # number of overall hits
system.cpu.icache.overall_miss_latency 31287500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 131906000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_misses 10596 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 20691500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 121310000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1478.638648 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1478.610505 # Cycle average of tags in use
system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2545.120588 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1544.109658 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3835145500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 19589206000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 2326760167 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 16575482000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2545.120588 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3835145500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 19589206000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2326760167 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 16575482000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2543.307872 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 12990.740986 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 107393 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3835145500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 19589206000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1507936 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2326760167 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 16575482000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 1474094 # number of replacements
system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 32754.836517 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 32753.638584 # Cycle average of tags in use
system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 1084960000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.warmup_cycle 2394479000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66804 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1370089513500 # number of cpu cycles simulated
system.cpu.numCycles 2750814393000 # number of cpu cycles simulated
system.cpu.num_insts 2008987607 # Number of instructions executed
system.cpu.num_refs 722390435 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls

11
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -91,8 +91,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -267,8 +266,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -306,8 +304,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -339,6 +336,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -363,6 +361,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -249,7 +250,7 @@ type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -280,14 +281,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -318,14 +318,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -356,7 +355,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.toL2Bus]
type=Bus
@ -364,4 +362,5 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64

558
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 7744324 # Number of BTB hits
global.BPredUnit.BTBLookups 13591046 # Number of BTB lookups
global.BPredUnit.RASInCorrect 32932 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 452723 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 10077718 # Number of conditional branches predicted
global.BPredUnit.lookups 15489897 # Number of BP lookups
global.BPredUnit.usedRAS 1844517 # Number of times the RAS was used to get a target.
host_inst_rate 108228 # Simulator instruction rate (inst/s)
host_mem_usage 159488 # Number of bytes of host memory used
host_seconds 735.41 # Real time elapsed on the host
host_tick_rate 23792996 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 12942665 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 11520420 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 21780362 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 15866784 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 7411086 # Number of BTB hits
global.BPredUnit.BTBLookups 13158968 # Number of BTB lookups
global.BPredUnit.RASInCorrect 32147 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 450892 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 9746581 # Number of conditional branches predicted
global.BPredUnit.lookups 14988034 # Number of BP lookups
global.BPredUnit.usedRAS 1776543 # Number of times the RAS was used to get a target.
host_inst_rate 99683 # Simulator instruction rate (inst/s)
host_mem_usage 159476 # Number of bytes of host memory used
host_seconds 798.45 # Real time elapsed on the host
host_tick_rate 35303213 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 9747985 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 9298064 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 21418262 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 15459606 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
sim_seconds 0.017498 # Number of seconds simulated
sim_ticks 17497602000 # Number of ticks simulated
sim_seconds 0.028188 # Number of seconds simulated
sim_ticks 28187684500 # Number of ticks simulated
system.cpu.commit.COM:branches 13754477 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 4260073 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 3230574 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 33996100
system.cpu.commit.COM:committed_per_cycle.samples 55590975
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 8358440 2458.65%
1 8230566 2421.03%
2 4712162 1386.09%
3 3108634 914.41%
4 2121957 624.18%
5 1131901 332.95%
6 1374606 404.34%
7 697761 205.25%
8 4260073 1253.11%
0 26501535 4767.24%
1 10970497 1973.43%
2 5466463 983.34%
3 3506601 630.79%
4 2372940 426.86%
5 1558557 280.36%
6 1098347 197.58%
7 885461 159.28%
8 3230574 581.13%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20379399 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 356682 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 355366 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 6565781 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 4551161 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.439684 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.439684 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 19603173 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4020.633151 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2686.323277 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19458721 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 580788500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007369 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 144452 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 82734 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 165794500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003148 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61718 # number of ReadReq MSHR misses
system.cpu.cpi 0.708309 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.708309 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20049834 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4729.134904 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3349.390829 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19907503 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 673102500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.007099 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 142331 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 80854 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 205910500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003066 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61477 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 2642.114676 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3379.334983 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 13777457 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 2208596500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.057202 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 835920 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 692465 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 484782500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 3029.723364 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4119.889460 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14053363 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1696687500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.038322 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 560014 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 416536 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 591113500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143478 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 161.990993 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 165.699134 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34216550 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 2845.231198 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33236178 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2789385000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.028652 # miss rate for demand accesses
system.cpu.dcache.demand_misses 980372 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 775199 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 650577000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005996 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 205173 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 34663211 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3374.111014 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency
system.cpu.dcache.demand_hits 33960866 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2369790000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.020262 # miss rate for demand accesses
system.cpu.dcache.demand_misses 702345 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 497390 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 797024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005913 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 204955 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34216550 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2845.231198 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 34663211 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3374.111014 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 33236178 # number of overall hits
system.cpu.dcache.overall_miss_latency 2789385000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.028652 # miss rate for overall accesses
system.cpu.dcache.overall_misses 980372 # number of overall misses
system.cpu.dcache.overall_mshr_hits 775199 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 650577000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005996 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 205173 # number of overall MSHR misses
system.cpu.dcache.overall_hits 33960866 # number of overall hits
system.cpu.dcache.overall_miss_latency 2369790000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.020262 # miss rate for overall accesses
system.cpu.dcache.overall_misses 702345 # number of overall misses
system.cpu.dcache.overall_mshr_hits 497390 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 797024000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005913 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 204955 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 201077 # number of replacements
system.cpu.dcache.sampled_refs 205173 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 200859 # number of replacements
system.cpu.dcache.sampled_refs 204955 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4079.993551 # Cycle average of tags in use
system.cpu.dcache.total_refs 33236178 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 90338000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147781 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 1516721 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 98391 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3463978 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 98144908 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 14320248 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 17547399 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 999107 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 287801 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 611733 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 15489897 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 12778073 # Number of cache lines fetched
system.cpu.fetch.Cycles 31147667 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 14471 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 99913909 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 465674 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.442629 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 12778073 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9588841 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.855074 # Number of inst fetches per cycle
system.cpu.dcache.tagsinuse 4080.110580 # Cycle average of tags in use
system.cpu.dcache.total_refs 33960866 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 144827000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147753 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 583473 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 97307 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3380270 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 95203508 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 37386702 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 17614461 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 784542 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 292514 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 6340 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 14988034 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 12416477 # Number of cache lines fetched
system.cpu.fetch.Cycles 30119953 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 260035 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 96279919 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 467393 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.265861 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 12416477 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 9187629 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.707832 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 34995208
system.cpu.fetch.rateDist.samples 56375518
system.cpu.fetch.rateDist.min_value 0
0 16625619 4750.83%
1 1365816 390.29%
2 1258616 359.65%
3 1410956 403.19%
4 3900976 1114.72%
5 1678758 479.71%
6 612174 174.93%
7 1011089 288.92%
8 7131204 2037.77%
0 38672046 6859.72%
1 1321940 234.49%
2 1201428 213.11%
3 1338454 237.42%
4 3789980 672.27%
5 1624217 288.11%
6 592859 105.16%
7 975150 172.97%
8 6859444 1216.74%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 12778073 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 2888.242687 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1894.538715 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 12690553 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 252779000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006849 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 87520 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 654 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 164571000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006798 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 86866 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 12416477 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3477.694454 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2488.876340 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 12330467 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 299116500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.006927 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 86010 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1011 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 211552000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006846 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 84999 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 146.093443 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 145.066024 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 12778073 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 2888.242687 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency
system.cpu.icache.demand_hits 12690553 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 252779000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006849 # miss rate for demand accesses
system.cpu.icache.demand_misses 87520 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 654 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 164571000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006798 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 86866 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 12416477 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3477.694454 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency
system.cpu.icache.demand_hits 12330467 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 299116500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.006927 # miss rate for demand accesses
system.cpu.icache.demand_misses 86010 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1011 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 211552000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.006846 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 84999 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 12778073 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 2888.242687 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency
system.cpu.icache.overall_accesses 12416477 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3477.694454 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 12690553 # number of overall hits
system.cpu.icache.overall_miss_latency 252779000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006849 # miss rate for overall accesses
system.cpu.icache.overall_misses 87520 # number of overall misses
system.cpu.icache.overall_mshr_hits 654 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 164571000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006798 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 86866 # number of overall MSHR misses
system.cpu.icache.overall_hits 12330467 # number of overall hits
system.cpu.icache.overall_miss_latency 299116500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.006927 # miss rate for overall accesses
system.cpu.icache.overall_misses 86010 # number of overall misses
system.cpu.icache.overall_mshr_hits 1011 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 211552000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.006846 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 84999 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 84818 # number of replacements
system.cpu.icache.sampled_refs 86866 # Sample count of references to valid blocks.
system.cpu.icache.replacements 82951 # number of replacements
system.cpu.icache.sampled_refs 84999 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1921.828467 # Cycle average of tags in use
system.cpu.icache.total_refs 12690553 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 15230287000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tagsinuse 1918.432617 # Cycle average of tags in use
system.cpu.icache.total_refs 12330467 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 24669337000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 6484 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14304724 # Number of branches executed
system.cpu.iew.EXEC:nop 9152219 # number of nop insts executed
system.cpu.iew.EXEC:rate 2.363053 # Inst execution rate
system.cpu.iew.EXEC:refs 36160680 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15116998 # Number of stores executed
system.cpu.idleCycles 25301 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 14196900 # Number of branches executed
system.cpu.iew.EXEC:nop 9006488 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.455602 # Inst execution rate
system.cpu.iew.EXEC:refs 36045074 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 15052480 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 43283574 # num instructions consuming a value
system.cpu.iew.WB:count 82548148 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.757836 # average fanout of values written-back
system.cpu.iew.WB:consumers 39431808 # num instructions consuming a value
system.cpu.iew.WB:count 81784655 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.769564 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 32801872 # num instructions producing a value
system.cpu.iew.WB:rate 2.358841 # insts written-back per cycle
system.cpu.iew.WB:sent 82621578 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 398195 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 20355 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 21780362 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4681 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 352010 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 15866784 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 94903979 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 21043682 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 752566 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 82695525 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 5889 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 30345313 # num instructions producing a value
system.cpu.iew.WB:rate 1.450712 # insts written-back per cycle
system.cpu.iew.WB:sent 81828309 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 387091 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 10156 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 21418262 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 4652 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 597409 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 15459606 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 92891480 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 20992594 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 333391 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 82060341 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 141 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 132 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 999107 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 7135 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 784542 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 478 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 1325562 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 2239 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 828061 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 554 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 16849 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1491 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1400963 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1022165 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 16849 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 105190 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 293005 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 2.274362 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.274362 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 83448091 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 19340 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1425 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1038863 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 614987 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 19340 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 103732 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 283359 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.411814 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.411814 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 82393732 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
IntAlu 46687810 55.95% # Type of FU issued
IntMult 45238 0.05% # Type of FU issued
IntAlu 45892607 55.70% # Type of FU issued
IntMult 44107 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 120004 0.14% # Type of FU issued
FloatAdd 116900 0.14% # Type of FU issued
FloatCmp 87 0.00% # Type of FU issued
FloatCvt 122290 0.15% # Type of FU issued
FloatCvt 120453 0.15% # Type of FU issued
FloatMult 50 0.00% # Type of FU issued
FloatDiv 37770 0.05% # Type of FU issued
FloatDiv 37768 0.05% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 21206489 25.41% # Type of FU issued
MemWrite 15228353 18.25% # Type of FU issued
MemRead 21065064 25.57% # Type of FU issued
MemWrite 15116696 18.35% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 1422206 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017043 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 898002 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.010899 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 169452 11.91% # attempts to use FU when none available
IntAlu 168043 18.71% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 649726 45.68% # attempts to use FU when none available
MemWrite 603028 42.40% # attempts to use FU when none available
MemRead 309725 34.49% # attempts to use FU when none available
MemWrite 420234 46.80% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 34995208
system.cpu.iq.ISSUE:issued_per_cycle.samples 56375518
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 5876071 1679.11%
1 8518834 2434.29%
2 6419045 1834.26%
3 4436708 1267.80%
4 4423684 1264.08%
5 2554091 729.84%
6 1512126 432.10%
7 794096 226.92%
8 460553 131.60%
0 22612550 4011.06%
1 13769796 2442.51%
2 7834961 1389.78%
3 4029672 714.79%
4 3712649 658.56%
5 1993297 353.57%
6 1449259 257.07%
7 434309 77.04%
8 539025 95.61%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 2.384558 # Inst issue rate
system.cpu.iq.iqInstsAdded 85747079 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 83448091 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4681 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 5951026 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 23998 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 98 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 4012087 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 291992 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3325.548649 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1922.235296 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 122257 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 564462000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.581300 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 169735 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 326270608 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.581300 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 169735 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147781 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 147317 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses
system.cpu.iq.ISSUE:rate 1.461516 # Inst issue rate
system.cpu.iq.iqInstsAdded 83880340 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 82393732 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 4652 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4104955 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 35761 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 69 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2730801 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 289883 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4226.385671 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2218.670959 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 120272 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 716841500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.585102 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 169611 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 376311000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.585102 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 169611 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 147292 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.003120 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 461 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.003120 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 461 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.588205 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 1.577516 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 291992 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3325.548649 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 122257 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 564462000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.581300 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 169735 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 289883 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4226.385671 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 120272 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 716841500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.585102 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 169611 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 326270608 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.581300 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 169735 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 376311000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.585102 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 169611 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 439773 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3316.482471 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 437636 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4214.929559 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 269574 # number of overall hits
system.cpu.l2cache.overall_miss_latency 564462000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.387016 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 170199 # number of overall misses
system.cpu.l2cache.overall_hits 267564 # number of overall hits
system.cpu.l2cache.overall_miss_latency 716841500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.388615 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 170072 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 326270608 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.385960 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 169735 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 376311000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.387562 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 169611 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -386,31 +386,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 136967 # number of replacements
system.cpu.l2cache.sampled_refs 169735 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 136843 # number of replacements
system.cpu.l2cache.sampled_refs 169611 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 32064.700481 # Cycle average of tags in use
system.cpu.l2cache.total_refs 269574 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 8508988000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 115938 # number of writebacks
system.cpu.numCycles 34995208 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 201241 # Number of cycles rename is blocking
system.cpu.l2cache.tagsinuse 32058.525051 # Cycle average of tags in use
system.cpu.l2cache.total_refs 267564 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 13792867000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 115936 # number of writebacks
system.cpu.numCycles 56375518 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 238131 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 31178 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 14721876 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1110145 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 117085470 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 96973574 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 58152082 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 17754494 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 999107 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1242602 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 5605201 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 75888 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 4701 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2792735 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 4699 # count of temporary serializing insts renamed
system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 31030 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 37626801 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 240022 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 113729051 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 94390828 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 56605918 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 17378620 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 784542 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 281505 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4059037 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 65919 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 4656 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 641192 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 4654 # count of temporary serializing insts renamed
system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------

1
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 842354 # Simulator instruction rate (inst/s)
host_mem_usage 152996 # Number of bytes of host memory used
host_seconds 104.87 # Real time elapsed on the host
host_tick_rate 421175511 # Simulator tick rate (ticks/s)
host_inst_rate 840697 # Simulator instruction rate (inst/s)
host_mem_usage 152968 # Number of bytes of host memory used
host_seconds 105.08 # Real time elapsed on the host
host_tick_rate 420346781 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340674 # Number of instructions simulated
sim_seconds 0.044170 # Number of seconds simulated

11
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

104
tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 562157 # Simulator instruction rate (inst/s)
host_mem_usage 158620 # Number of bytes of host memory used
host_seconds 157.15 # Real time elapsed on the host
host_tick_rate 396922606 # Simulator tick rate (ticks/s)
host_inst_rate 585395 # Simulator instruction rate (inst/s)
host_mem_usage 158604 # Number of bytes of host memory used
host_seconds 150.91 # Real time elapsed on the host
host_tick_rate 839295251 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340674 # Number of instructions simulated
sim_seconds 0.062375 # Number of seconds simulated
sim_ticks 62374966500 # Number of ticks simulated
sim_seconds 0.126657 # Number of seconds simulated
sim_ticks 126656575000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3130.058422 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2130.058422 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 12987.854851 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11987.854851 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 190198000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 789207000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 129433000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 728442000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3436.431765 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2436.431765 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 13826.199000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.199000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 493396000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 1985138000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 349818000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1841560000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3345.326241 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 13576.902561 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency
system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 683594000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 2774345000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 479251000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 2570002000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3345.326241 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 13576.902561 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34685672 # number of overall hits
system.cpu.dcache.overall_miss_latency 683594000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 2774345000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
system.cpu.dcache.overall_misses 204343 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 479251000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 2570002000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 200247 # number of replacements
system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4082.118898 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4081.697925 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 307192000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 661090000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 # number of writebacks
system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 2831.355644 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1831.355644 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 12197.393898 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11197.393898 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 216417500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 932320000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 139981500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 855884000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 2831.355644 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 12197.393898 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency
system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 216417500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 932320000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 139981500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 855884000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 2831.355644 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 12197.393898 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 88264239 # number of overall hits
system.cpu.icache.overall_miss_latency 216417500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 932320000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
system.cpu.icache.overall_misses 76436 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 139981500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 855884000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 74391 # number of replacements
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1880.010701 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1878.885583 # Cycle average of tags in use
system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2532.769537 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1531.091909 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 12999.768790 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.768790 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 427222500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 2192775000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 258261521 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1855419000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2532.769537 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 12999.768790 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 427222500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 2192775000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 258261521 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 1855419000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2526.209820 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 12966.100192 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 259377 # number of overall hits
system.cpu.l2cache.overall_miss_latency 427222500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 2192775000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 169116 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 258261521 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 1855419000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 135910 # number of replacements
system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 32002.173981 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 31979.717205 # Cycle average of tags in use
system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 30452104000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.warmup_cycle 61925078000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 115911 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 62374966500 # number of cpu cycles simulated
system.cpu.numCycles 126656575000 # number of cpu cycles simulated
system.cpu.num_insts 88340674 # Number of instructions executed
system.cpu.num_refs 35224019 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls

1
tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 644632 # Simulator instruction rate (inst/s)
host_mem_usage 151548 # Number of bytes of host memory used
host_seconds 211.36 # Real time elapsed on the host
host_tick_rate 322315545 # Simulator tick rate (ticks/s)
host_inst_rate 672762 # Simulator instruction rate (inst/s)
host_mem_usage 151516 # Number of bytes of host memory used
host_seconds 202.52 # Real time elapsed on the host
host_tick_rate 336380340 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136246936 # Number of instructions simulated
sim_seconds 0.068123 # Number of seconds simulated

4
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout
View file

@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 27 2007 14:35:32
M5 started Fri Apr 27 15:55:23 2007
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 16:40:43 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

11
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

114
tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 466766 # Simulator instruction rate (inst/s)
host_mem_usage 157052 # Number of bytes of host memory used
host_seconds 291.90 # Real time elapsed on the host
host_tick_rate 335938336 # Simulator tick rate (ticks/s)
host_inst_rate 480067 # Simulator instruction rate (inst/s)
host_mem_usage 157016 # Number of bytes of host memory used
host_seconds 283.81 # Real time elapsed on the host
host_tick_rate 698858124 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136246936 # Number of instructions simulated
sim_seconds 0.098059 # Number of seconds simulated
sim_ticks 98059078500 # Number of ticks simulated
sim_seconds 0.198342 # Number of seconds simulated
sim_ticks 198341876000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3241.706786 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2241.706786 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 147462000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 101973000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 3166.666667 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2166.666667 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 47500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 32500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3588.938331 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2588.938331 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 377463000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 272289000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3484.100277 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency
system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 524925000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses
system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 374262000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3484.100277 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 57944942 # number of overall hits
system.cpu.dcache.overall_miss_latency 524925000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses
system.cpu.dcache.overall_misses 150663 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 374262000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4090.058697 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 224414000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 107279 # number of writebacks
system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 2800.327765 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1800.327765 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 523728500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 336704500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 2800.327765 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency
system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 523728500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 336704500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 2800.327765 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 136059913 # number of overall hits
system.cpu.icache.overall_miss_latency 523728500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses
system.cpu.icache.overall_misses 187024 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 336704500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 2008.440865 # Cycle average of tags in use
system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use
system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 69827484000 # Cycle when the warmup percentage was hit.
system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2644.770157 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1643.366085 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 356195000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 221326901 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses)
@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2644.770157 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 356195000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 221326901 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2634.831752 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 309728 # number of overall hits
system.cpu.l2cache.overall_miss_latency 356195000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 135187 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 221326901 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 101911 # number of replacements
system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 32141.182824 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use
system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 20627583000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 82918 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 98059078500 # number of cpu cycles simulated
system.cpu.numCycles 198341876000 # number of cpu cycles simulated
system.cpu.num_insts 136246936 # Number of instructions executed
system.cpu.num_refs 58111522 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls

6
tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 27 2007 14:35:32
M5 started Fri Apr 27 15:58:57 2007
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 16:44:06 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 98059078500 because target called exit()
Exiting @ tick 198341876000 because target called exit()

11
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -91,8 +91,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -267,8 +266,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -306,8 +304,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -339,6 +336,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -363,6 +361,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -249,7 +250,7 @@ type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -280,14 +281,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -318,14 +318,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -356,7 +355,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.toL2Bus]
type=Bus
@ -364,4 +362,5 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64

554
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 264221270 # Number of BTB hits
global.BPredUnit.BTBLookups 273071573 # Number of BTB lookups
global.BPredUnit.RASInCorrect 122 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 19541079 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 228439261 # Number of conditional branches predicted
global.BPredUnit.lookups 295748685 # Number of BP lookups
global.BPredUnit.usedRAS 20371548 # Number of times the RAS was used to get a target.
host_inst_rate 108663 # Simulator instruction rate (inst/s)
host_mem_usage 154628 # Number of bytes of host memory used
host_seconds 15976.47 # Real time elapsed on the host
host_tick_rate 25821276 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 80477635 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 37646176 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 533254174 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 186471924 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 236329759 # Number of BTB hits
global.BPredUnit.BTBLookups 244099867 # Number of BTB lookups
global.BPredUnit.RASInCorrect 116 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 19342549 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 203388054 # Number of conditional branches predicted
global.BPredUnit.lookups 265702680 # Number of BP lookups
global.BPredUnit.usedRAS 19620183 # Number of times the RAS was used to get a target.
host_inst_rate 104740 # Simulator instruction rate (inst/s)
host_mem_usage 154596 # Number of bytes of host memory used
host_seconds 16574.74 # Real time elapsed on the host
host_tick_rate 38540500 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 53067106 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 26767467 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 497279728 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 174034666 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
sim_seconds 0.412533 # Number of seconds simulated
sim_ticks 412532848500 # Number of ticks simulated
sim_seconds 0.638799 # Number of seconds simulated
sim_ticks 638798750000 # Number of ticks simulated
system.cpu.commit.COM:branches 214632552 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 78248119 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 60317471 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 772086758
system.cpu.commit.COM:committed_per_cycle.samples 1240430038
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 242551958 3141.51%
1 161050324 2085.91%
2 101638189 1316.41%
3 63812257 826.49%
4 43982002 569.65%
5 37612088 487.15%
6 28299494 366.53%
7 14892327 192.88%
8 78248119 1013.46%
0 616961832 4973.77%
1 236071207 1903.14%
2 130159070 1049.31%
3 77572840 625.37%
4 40072787 323.06%
5 42334502 341.29%
6 22413470 180.69%
7 14526859 117.11%
8 60317471 486.26%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 445666361 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 19540581 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 19342064 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 358953852 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 213160886 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.475256 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.475256 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 463286594 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3710.591477 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2550.415742 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 454594407 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 32253155000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.018762 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 8692187 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1395111 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 18610577500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015751 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7297076 # number of ReadReq MSHR misses
system.cpu.cpi 0.735925 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.735925 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 460303357 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3955.169300 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2868.381634 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 451791924 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 33664158500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.018491 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 8511433 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1219244 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 20916781000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015842 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7292189 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 6275.157749 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8072.319138 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 157494886 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 20291450500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.020118 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 3233616 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1350145 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 15203979000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011718 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1883471 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 1064.957356 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 500 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 66.672421 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 75157 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 5468 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 80039000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 2734000 # number of cycles access was blocked
system.cpu.dcache.WriteReq_avg_miss_latency 6699.535635 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8433.632873 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 157310932 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 22896132000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.021263 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 3417570 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1533904 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 15886147500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011720 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1883666 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 1092.259997 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets 571.397227 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 66.381046 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 62416 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 56970 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 68174500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 32552500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 624015096 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 4405.959540 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency
system.cpu.dcache.demand_hits 612089293 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 52544605500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.019111 # miss rate for demand accesses
system.cpu.dcache.demand_misses 11925803 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2745256 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 33814556500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.014712 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9180547 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 621031859 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 4741.409697 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency
system.cpu.dcache.demand_hits 609102856 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 56560290500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.019208 # miss rate for demand accesses
system.cpu.dcache.demand_misses 11929003 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 2753148 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 36802928500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.014775 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9175855 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 624015096 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 4405.959540 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 621031859 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 4741.409697 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 612089293 # number of overall hits
system.cpu.dcache.overall_miss_latency 52544605500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.019111 # miss rate for overall accesses
system.cpu.dcache.overall_misses 11925803 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2745256 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 33814556500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.014712 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9180547 # number of overall MSHR misses
system.cpu.dcache.overall_hits 609102856 # number of overall hits
system.cpu.dcache.overall_miss_latency 56560290500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.019208 # miss rate for overall accesses
system.cpu.dcache.overall_misses 11929003 # number of overall misses
system.cpu.dcache.overall_mshr_hits 2753148 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 36802928500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.014775 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9175855 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 9176451 # number of replacements
system.cpu.dcache.sampled_refs 9180547 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 9171759 # number of replacements
system.cpu.dcache.sampled_refs 9175855 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4083.178096 # Cycle average of tags in use
system.cpu.dcache.total_refs 612089293 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 4996762000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2245686 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 22551440 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 546 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 44940582 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2380682647 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 322635695 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 423064703 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 52978940 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1700 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 3834921 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 295748685 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 302488728 # Number of cache lines fetched
system.cpu.fetch.Cycles 741391553 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2447585283 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 20057035 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.358455 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 302488728 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 284592818 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.966534 # Number of inst fetches per cycle
system.cpu.dcache.tagsinuse 4081.309726 # Cycle average of tags in use
system.cpu.dcache.total_refs 609102856 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8881811000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2245633 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 27333658 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 501 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 42431183 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 2163062948 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 823856490 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 388659524 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 37167487 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 1638 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 580367 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 265702680 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 277957843 # Number of cache lines fetched
system.cpu.fetch.Cycles 672748425 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 10624598 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 2197044125 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 19810424 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.207971 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 277957843 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 255949942 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.719668 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 825065699
system.cpu.fetch.rateDist.samples 1277597526
system.cpu.fetch.rateDist.min_value 0
0 386162878 4680.39%
1 30694739 372.03%
2 18778429 227.60%
3 29987039 363.45%
4 87656406 1062.42%
5 50975460 617.84%
6 28097158 340.54%
7 26422023 320.24%
8 166291567 2015.49%
0 882806946 6909.90%
1 27356477 214.12%
2 16416749 128.50%
3 27123610 212.30%
4 80197027 627.72%
5 46838848 366.62%
6 25144427 196.81%
7 24073126 188.42%
8 147640316 1155.61%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 302488728 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 4286.486486 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3340.579710 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 302487803 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 3965000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_accesses 277957843 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5447.729673 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4641.891892 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 277956896 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 5159000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 925 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 2996500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_misses 947 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 4122000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 897 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses 888 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 337221.630992 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 313014.522523 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 302488728 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 4286.486486 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency
system.cpu.icache.demand_hits 302487803 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 3965000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_accesses 277957843 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5447.729673 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency
system.cpu.icache.demand_hits 277956896 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 5159000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
system.cpu.icache.demand_misses 925 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2996500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_misses 947 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 4122000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 897 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses 888 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 302488728 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 4286.486486 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency
system.cpu.icache.overall_accesses 277957843 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5447.729673 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 302487803 # number of overall hits
system.cpu.icache.overall_miss_latency 3965000 # number of overall miss cycles
system.cpu.icache.overall_hits 277956896 # number of overall hits
system.cpu.icache.overall_miss_latency 5159000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_misses 925 # number of overall misses
system.cpu.icache.overall_mshr_hits 28 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2996500 # number of overall MSHR miss cycles
system.cpu.icache.overall_misses 947 # number of overall misses
system.cpu.icache.overall_mshr_hits 59 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 4122000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 897 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses 888 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -216,79 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 897 # Sample count of references to valid blocks.
system.cpu.icache.sampled_refs 888 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 700.392428 # Cycle average of tags in use
system.cpu.icache.total_refs 302487803 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 691.554117 # Cycle average of tags in use
system.cpu.icache.total_refs 277956896 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 498 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 240658046 # Number of branches executed
system.cpu.iew.EXEC:nop 109011682 # number of nop insts executed
system.cpu.iew.EXEC:rate 2.343638 # Inst execution rate
system.cpu.iew.EXEC:refs 670450767 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 171332493 # Number of stores executed
system.cpu.idleCycles 973 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 231142223 # Number of branches executed
system.cpu.iew.EXEC:nop 101615397 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.460942 # Inst execution rate
system.cpu.iew.EXEC:refs 650877785 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 168419462 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1329316260 # num instructions consuming a value
system.cpu.iew.WB:count 1919496913 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.807674 # average fanout of values written-back
system.cpu.iew.WB:consumers 1210814193 # num instructions consuming a value
system.cpu.iew.WB:count 1847797148 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.819076 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1073654377 # num instructions producing a value
system.cpu.iew.WB:rate 2.326478 # insts written-back per cycle
system.cpu.iew.WB:sent 1925768214 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 21262198 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 271227 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 533254174 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 16376681 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 186471924 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2178733969 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 499118274 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 42707495 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1933655185 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 3473 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 991749121 # num instructions producing a value
system.cpu.iew.WB:rate 1.446306 # insts written-back per cycle
system.cpu.iew.WB:sent 1849274792 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 20085867 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1985372 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 497279728 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 38 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 27992821 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 174034666 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2032941045 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 482458323 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 14098084 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1866495371 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 77 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 253 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 52978940 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 31539 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 1402 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 37167487 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 36044 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 331862 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 34494542 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 128095 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 409084 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 20784106 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 401249 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 361683 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 87587813 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 25566942 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 361683 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 691850 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 20570348 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 2.104128 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.104128 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 1976362680 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 306932 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 51613367 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 13129684 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 306932 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 672336 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 19413531 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.358835 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.358835 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 1880593455 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
IntAlu 1288510764 65.20% # Type of FU issued
IntAlu 1224165146 65.09% # Type of FU issued
IntMult 78 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 234 0.00% # Type of FU issued
FloatAdd 199 0.00% # Type of FU issued
FloatCmp 15 0.00% # Type of FU issued
FloatCvt 154 0.00% # Type of FU issued
FloatMult 14 0.00% # Type of FU issued
FloatCvt 141 0.00% # Type of FU issued
FloatMult 13 0.00% # Type of FU issued
FloatDiv 24 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 513015840 25.96% # Type of FU issued
MemWrite 174835557 8.85% # Type of FU issued
MemRead 487297898 25.91% # Type of FU issued
MemWrite 169129941 8.99% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 18092397 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.009154 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 14841221 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.007892 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 2424231 13.40% # attempts to use FU when none available
IntAlu 753308 5.08% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 11434785 63.20% # attempts to use FU when none available
MemWrite 4233381 23.40% # attempts to use FU when none available
MemRead 10126775 68.23% # attempts to use FU when none available
MemWrite 3961138 26.69% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 825065699
system.cpu.iq.ISSUE:issued_per_cycle.samples 1277597526
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 201043450 2436.70%
1 117715520 1426.74%
2 151671107 1838.29%
3 100094924 1213.18%
4 99857816 1210.30%
5 89528622 1085.11%
6 51943929 629.57%
7 9400422 113.94%
8 3809909 46.18%
0 550473495 4308.66%
1 242915598 1901.35%
2 174612702 1366.73%
3 111937959 876.16%
4 91216702 713.97%
5 63235343 494.96%
6 32411117 253.69%
7 9228529 72.23%
8 1566081 12.26%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 2.395400 # Inst issue rate
system.cpu.iq.iqInstsAdded 2069722245 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1976362680 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 325012863 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1550012 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 175292310 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 9181444 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4578.076271 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1904.625556 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7012219 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 9930877500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.236262 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 2169225 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4131561371 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236262 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 2169225 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2245686 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2216531 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.012983 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 29155 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.012983 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 29155 # number of Writeback MSHR misses
system.cpu.iq.ISSUE:rate 1.471976 # Inst issue rate
system.cpu.iq.iqInstsAdded 1931325610 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1880593455 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 179510503 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 87058 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 101093002 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 9176743 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 5323.405393 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2210.600583 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7008183 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 11544124000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.236310 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 2168560 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4793820000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236310 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 2168560 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2245633 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2216502 # number of Writeback hits
system.cpu.l2cache.Writeback_miss_rate 0.012972 # miss rate for Writeback accesses
system.cpu.l2cache.Writeback_misses 29131 # number of Writeback misses
system.cpu.l2cache.Writeback_mshr_miss_rate 0.012972 # mshr miss rate for Writeback accesses
system.cpu.l2cache.Writeback_mshr_misses 29131 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.254400 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 4.253830 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9181444 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4578.076271 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7012219 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 9930877500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.236262 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2169225 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 9176743 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 5323.405393 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7008183 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 11544124000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.236310 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2168560 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4131561371 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.236262 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2169225 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 4793820000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.236310 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2168560 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 11427130 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4517.361648 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 11422376 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 5252.842188 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 9228750 # number of overall hits
system.cpu.l2cache.overall_miss_latency 9930877500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.192383 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2198380 # number of overall misses
system.cpu.l2cache.overall_hits 9224685 # number of overall hits
system.cpu.l2cache.overall_miss_latency 11544124000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.192402 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2197691 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4131561371 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.189831 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2169225 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 4793820000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.189852 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2168560 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -386,32 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 2136457 # number of replacements
system.cpu.l2cache.sampled_refs 2169225 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 2135792 # number of replacements
system.cpu.l2cache.sampled_refs 2168560 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31578.699946 # Cycle average of tags in use
system.cpu.l2cache.total_refs 9228750 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 29958824000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1039499 # number of writebacks
system.cpu.numCycles 825065699 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 6100420 # Number of cycles rename is blocking
system.cpu.l2cache.tagsinuse 31406.160078 # Cycle average of tags in use
system.cpu.l2cache.total_refs 9224685 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 53019662000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1039396 # number of writebacks
system.cpu.numCycles 1277597526 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 16292159 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4850719 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 338099779 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 9291025 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1319 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2964381647 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2307795213 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1730632745 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 411108509 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 52978940 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 16777593 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 354429782 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 458 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 47 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 42678716 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 45 # count of temporary serializing insts renamed
system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 4365074 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 834284464 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 6221923 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 448 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 2711841153 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2114466649 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1591248178 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 378627043 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 37167487 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 11225904 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 215045215 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 469 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 45 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 21611838 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 43 # count of temporary serializing insts renamed
system.cpu.timesIdled 27 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------

1
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 929031 # Simulator instruction rate (inst/s)
host_mem_usage 148624 # Number of bytes of host memory used
host_seconds 1958.79 # Real time elapsed on the host
host_tick_rate 464515386 # Simulator tick rate (ticks/s)
host_inst_rate 918892 # Simulator instruction rate (inst/s)
host_mem_usage 148632 # Number of bytes of host memory used
host_seconds 1980.41 # Real time elapsed on the host
host_tick_rate 459446111 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780129 # Number of instructions simulated
sim_seconds 0.909890 # Number of seconds simulated

11
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

104
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 623968 # Simulator instruction rate (inst/s)
host_mem_usage 154076 # Number of bytes of host memory used
host_seconds 2916.46 # Real time elapsed on the host
host_tick_rate 423514548 # Simulator tick rate (ticks/s)
host_inst_rate 637714 # Simulator instruction rate (inst/s)
host_mem_usage 154060 # Number of bytes of host memory used
host_seconds 2853.60 # Real time elapsed on the host
host_tick_rate 886477792 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780129 # Number of instructions simulated
sim_seconds 1.235165 # Number of seconds simulated
sim_ticks 1235165291000 # Number of ticks simulated
sim_seconds 2.529655 # Number of seconds simulated
sim_ticks 2529654621000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 2978.629098 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1978.629098 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 12378.042992 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11378.042992 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 21512892500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 89399351000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 14290478500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 82176937000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 2992.340366 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1992.340366 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 12836.520018 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11836.520018 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5653488500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 24252294000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3764168500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 22362974000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 2981.472133 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 12473.108302 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency
system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 27166381000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 113651645000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 18054647000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 104539911000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2981.472133 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 12473.108302 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 596212431 # number of overall hits
system.cpu.dcache.overall_miss_latency 27166381000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 113651645000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9111734 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 18054647000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 104539911000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4078.615858 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 4078.970916 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 20287970000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.warmup_cycle 40631938000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2244708 # number of writebacks
system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3779.301746 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2779.301746 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 13987.531172 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12987.531172 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 3031000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 11218000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 2229000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 10416000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3779.301746 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 13987.531172 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency
system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 3031000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 11218000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 2229000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 10416000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3779.301746 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 13987.531172 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1819779328 # number of overall hits
system.cpu.icache.overall_miss_latency 3031000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 11218000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
system.cpu.icache.overall_misses 802 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 2229000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 10416000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 611.013893 # Cycle average of tags in use
system.cpu.icache.tagsinuse 611.364745 # Cycle average of tags in use
system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2722.045846 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.036352 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 12996.354425 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10996.354425 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 5880035500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 28074114000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 3713381532 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 23753808000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses)
@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2722.045846 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 12996.354425 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 5880035500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 28074114000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 3713381532 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 23753808000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2685.867535 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 12823.621788 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 9167994 # number of overall hits
system.cpu.l2cache.overall_miss_latency 5880035500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 28074114000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 2189250 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 3713381532 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 23753808000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 2127385 # number of replacements
system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 31158.106837 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 31194.155037 # Cycle average of tags in use
system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 122436614000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.warmup_cycle 245730069000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 1038202 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1235165291000 # number of cpu cycles simulated
system.cpu.numCycles 2529654621000 # number of cpu cycles simulated
system.cpu.num_insts 1819780129 # Number of instructions executed
system.cpu.num_refs 606571345 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls

11
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -91,8 +91,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -267,8 +266,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -306,8 +304,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -339,6 +336,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -363,6 +361,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -249,7 +250,7 @@ type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -280,14 +281,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -318,14 +318,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -356,7 +355,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.toL2Bus]
type=Bus
@ -364,4 +362,5 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64

550
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 14247678 # Number of BTB hits
global.BPredUnit.BTBLookups 18312009 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1187 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 1953985 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 15742663 # Number of conditional branches predicted
global.BPredUnit.lookups 20998495 # Number of BP lookups
global.BPredUnit.usedRAS 1857732 # Number of times the RAS was used to get a target.
host_inst_rate 58248 # Simulator instruction rate (inst/s)
host_mem_usage 156992 # Number of bytes of host memory used
host_seconds 1445.19 # Real time elapsed on the host
host_tick_rate 23712867 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 20592604 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 6080799 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 35412339 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 11200166 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 11874522 # Number of BTB hits
global.BPredUnit.BTBLookups 15445749 # Number of BTB lookups
global.BPredUnit.RASInCorrect 1158 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 1931947 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 13190559 # Number of conditional branches predicted
global.BPredUnit.lookups 17824174 # Number of BP lookups
global.BPredUnit.usedRAS 1655464 # Number of times the RAS was used to get a target.
host_inst_rate 74830 # Simulator instruction rate (inst/s)
host_mem_usage 156844 # Number of bytes of host memory used
host_seconds 1124.95 # Real time elapsed on the host
host_tick_rate 39347975 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 14674251 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 4294265 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 31675298 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 10012759 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
sim_seconds 0.034270 # Number of seconds simulated
sim_ticks 34269677000 # Number of ticks simulated
sim_seconds 0.044264 # Number of seconds simulated
sim_ticks 44264420500 # Number of ticks simulated
system.cpu.commit.COM:branches 10240685 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3363462 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 2948022 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 59572652
system.cpu.commit.COM:committed_per_cycle.samples 81602250
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 25280039 4243.56%
1 15284536 2565.70%
2 7326530 1229.85%
3 3334393 559.72%
4 2152142 361.26%
5 1242273 208.53%
6 890288 149.45%
7 698989 117.33%
8 3363462 564.60%
0 44887304 5500.74%
1 17052684 2089.73%
2 8186225 1003.19%
3 3991011 489.08%
4 1764745 216.26%
5 1325913 162.48%
6 892255 109.34%
7 554091 67.90%
8 2948022 361.27%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20034413 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 1941454 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 1919652 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 63250167 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 46410426 # The number of squashed insts skipped by commit
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
system.cpu.cpi 0.814203 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.814203 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 23612894 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4229.600000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3389.648438 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23612269 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2643500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 625 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 113 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1735500 # number of ReadReq MSHR miss cycles
system.cpu.cpi 1.051666 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.051666 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 23047695 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5314.424635 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4545.725646 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 23047078 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3279000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 617 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 114 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2286500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 512 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses 503 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3064.490759 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3618.087558 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6493474 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 23379000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001173 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 7629 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 5893 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 6281000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_avg_miss_latency 3836.081210 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4946.808511 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6493764 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 28153000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.001129 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 7339 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 5600 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 8602500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1736 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 13392.234431 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 13176.111508 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 30113997 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3152.713836 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency
system.cpu.dcache.demand_hits 30105743 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 26022500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000274 # miss rate for demand accesses
system.cpu.dcache.demand_misses 8254 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 6006 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 8016500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2248 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 29548798 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3950.729010 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency
system.cpu.dcache.demand_hits 29540842 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 31432000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000269 # miss rate for demand accesses
system.cpu.dcache.demand_misses 7956 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5714 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 30113997 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3152.713836 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 29548798 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3950.729010 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 30105743 # number of overall hits
system.cpu.dcache.overall_miss_latency 26022500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000274 # miss rate for overall accesses
system.cpu.dcache.overall_misses 8254 # number of overall misses
system.cpu.dcache.overall_mshr_hits 6006 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 8016500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2248 # number of overall MSHR misses
system.cpu.dcache.overall_hits 29540842 # number of overall hits
system.cpu.dcache.overall_miss_latency 31432000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000269 # miss rate for overall accesses
system.cpu.dcache.overall_misses 7956 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5714 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 162 # number of replacements
system.cpu.dcache.sampled_refs 2248 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 163 # number of replacements
system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1463.572116 # Cycle average of tags in use
system.cpu.dcache.total_refs 30105743 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1457.683096 # Cycle average of tags in use
system.cpu.dcache.total_refs 29540842 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 106 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 6099480 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 13208 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 3247204 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 173741531 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 23444029 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 28861256 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 8966698 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 40444 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1167888 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 20998495 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 20206829 # Number of cache lines fetched
system.cpu.fetch.Cycles 51475298 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 3593 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 180749377 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2035048 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.306371 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 20206829 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 16105410 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.637162 # Number of inst fetches per cycle
system.cpu.dcache.writebacks 107 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 2294607 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 12777 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 2890400 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 151561971 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 53136009 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 26139582 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 6926673 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 40541 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 32053 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 17824174 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 18016265 # Number of cache lines fetched
system.cpu.fetch.Cycles 44691424 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 975254 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 154588435 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 2011658 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.201337 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 18016265 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 13529986 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.746191 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 68539351
system.cpu.fetch.rateDist.samples 88528924
system.cpu.fetch.rateDist.min_value 0
0 37270886 5437.88%
1 3420236 499.02%
2 1457458 212.65%
3 2151808 313.95%
4 4198050 612.50%
5 1495508 218.20%
6 1665097 242.94%
7 1343985 196.09%
8 15536323 2266.77%
0 61853767 6986.84%
1 2838595 320.64%
2 1299355 146.77%
3 1865057 210.67%
4 3537974 399.64%
5 1231942 139.16%
6 1400771 158.23%
7 1171977 132.38%
8 13329486 1505.66%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 20206829 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3070.200019 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2096.460002 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 20196480 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 31773500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000512 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10349 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 21201500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000500 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 10113 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 18016265 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3877.692156 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2918.898279 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 18006143 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 39250000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000562 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 10122 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 28666500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000545 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 9821 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 1997.080985 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1833.432746 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 20206829 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3070.200019 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency
system.cpu.icache.demand_hits 20196480 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 31773500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000512 # miss rate for demand accesses
system.cpu.icache.demand_misses 10349 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 21201500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000500 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 10113 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 18016265 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3877.692156 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency
system.cpu.icache.demand_hits 18006143 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 39250000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000562 # miss rate for demand accesses
system.cpu.icache.demand_misses 10122 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 28666500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000545 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 9821 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 20206829 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3070.200019 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency
system.cpu.icache.overall_accesses 18016265 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3877.692156 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 20196480 # number of overall hits
system.cpu.icache.overall_miss_latency 31773500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000512 # miss rate for overall accesses
system.cpu.icache.overall_misses 10349 # number of overall misses
system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 21201500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000500 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 10113 # number of overall MSHR misses
system.cpu.icache.overall_hits 18006143 # number of overall hits
system.cpu.icache.overall_miss_latency 39250000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000562 # miss rate for overall accesses
system.cpu.icache.overall_misses 10122 # number of overall misses
system.cpu.icache.overall_mshr_hits 301 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 28666500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000545 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 9821 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 8192 # number of replacements
system.cpu.icache.sampled_refs 10113 # Sample count of references to valid blocks.
system.cpu.icache.replacements 7904 # number of replacements
system.cpu.icache.sampled_refs 9821 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1564.702526 # Cycle average of tags in use
system.cpu.icache.total_refs 20196480 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1549.418815 # Cycle average of tags in use
system.cpu.icache.total_refs 18006143 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 2998 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 13347594 # Number of branches executed
system.cpu.iew.EXEC:nop 13508406 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.523954 # Inst execution rate
system.cpu.iew.EXEC:refs 32463851 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7352116 # Number of stores executed
system.cpu.idleCycles 7902 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 12543861 # Number of branches executed
system.cpu.iew.EXEC:nop 11949352 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.130385 # Inst execution rate
system.cpu.iew.EXEC:refs 31528912 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 7145648 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 95064439 # num instructions consuming a value
system.cpu.iew.WB:count 103132878 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.721353 # average fanout of values written-back
system.cpu.iew.WB:consumers 87529341 # num instructions consuming a value
system.cpu.iew.WB:count 98214425 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.729574 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 68574976 # num instructions producing a value
system.cpu.iew.WB:rate 1.504725 # insts written-back per cycle
system.cpu.iew.WB:sent 104172184 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2117203 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 606505 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 35412339 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 444 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 632938 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 11200166 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 155150547 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 25111735 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2600272 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 104450796 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 226857 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 63859133 # num instructions producing a value
system.cpu.iew.WB:rate 1.109405 # insts written-back per cycle
system.cpu.iew.WB:sent 99107976 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 2078247 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 190251 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 31675298 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 411 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2578287 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 10012759 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 138313092 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 24383264 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1412890 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 100071797 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 38223 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 8966698 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 304686 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 6926673 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 64568 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 1001916 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 10875 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 828690 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 779 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 88969 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9698 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 15377926 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 4697471 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 88969 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 207130 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1910073 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 1.228195 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.228195 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 107051068 # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 84249 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 9673 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 11640885 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 3510064 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 84249 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 193948 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1884299 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.950872 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.950872 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 101484687 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 7 0.00% # Type of FU issued
IntAlu 66598699 62.21% # Type of FU issued
IntMult 478232 0.45% # Type of FU issued
IntAlu 62609480 61.69% # Type of FU issued
IntMult 467679 0.46% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2814666 2.63% # Type of FU issued
FloatCmp 115604 0.11% # Type of FU issued
FloatCvt 2391391 2.23% # Type of FU issued
FloatMult 308778 0.29% # Type of FU issued
FloatDiv 755076 0.71% # Type of FU issued
FloatSqrt 324 0.00% # Type of FU issued
MemRead 26034990 24.32% # Type of FU issued
MemWrite 7553301 7.06% # Type of FU issued
FloatAdd 2780950 2.74% # Type of FU issued
FloatCmp 115557 0.11% # Type of FU issued
FloatCvt 2364134 2.33% # Type of FU issued
FloatMult 305451 0.30% # Type of FU issued
FloatDiv 755050 0.74% # Type of FU issued
FloatSqrt 320 0.00% # Type of FU issued
MemRead 24826231 24.46% # Type of FU issued
MemWrite 7259828 7.15% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 2233247 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.020862 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 1739512 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.017141 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 352978 15.81% # attempts to use FU when none available
IntAlu 236478 13.59% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 856 0.04% # attempts to use FU when none available
FloatCmp 8 0.00% # attempts to use FU when none available
FloatCvt 3654 0.16% # attempts to use FU when none available
FloatMult 2325 0.10% # attempts to use FU when none available
FloatDiv 987087 44.20% # attempts to use FU when none available
FloatAdd 1 0.00% # attempts to use FU when none available
FloatCmp 0 0.00% # attempts to use FU when none available
FloatCvt 223 0.01% # attempts to use FU when none available
FloatMult 1629 0.09% # attempts to use FU when none available
FloatDiv 705159 40.54% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 766963 34.34% # attempts to use FU when none available
MemWrite 119376 5.35% # attempts to use FU when none available
MemRead 710061 40.82% # attempts to use FU when none available
MemWrite 85961 4.94% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 68539351
system.cpu.iq.ISSUE:issued_per_cycle.samples 88528924
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 25564605 3729.92%
1 14833050 2164.17%
2 10859904 1584.48%
3 6945297 1013.33%
4 5154135 752.00%
5 2881350 420.39%
6 1567848 228.75%
7 633355 92.41%
8 99807 14.56%
0 43673541 4933.25%
1 18286123 2065.55%
2 11155754 1260.13%
3 6962814 786.50%
4 4628513 522.82%
5 2073707 234.24%
6 1255435 141.81%
7 360879 40.76%
8 132158 14.93%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.561892 # Inst issue rate
system.cpu.iq.iqInstsAdded 141641697 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 107051068 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 444 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 56891185 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 501220 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 55 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 52161048 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 12360 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3103.922717 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1864.884465 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 7236 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 15904500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.414563 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 5124 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 9555668 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.414563 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 5124 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits
system.cpu.iq.ISSUE:rate 1.146345 # Inst issue rate
system.cpu.iq.iqInstsAdded 126363329 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 101484687 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 411 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 41115515 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 151595 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 37587907 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 12063 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4597.386006 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.176887 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 6975 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 23391500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.421786 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 5088 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 12466500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.421786 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 5088 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 1.432865 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 1.391903 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 12360 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3103.922717 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 7236 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 15904500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.414563 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 12063 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4597.386006 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 6975 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 23391500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.421786 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5088 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 9555668 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.414563 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 12466500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.421786 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5088 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 12466 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3103.922717 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 12170 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4597.386006 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 7342 # number of overall hits
system.cpu.l2cache.overall_miss_latency 15904500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.411038 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5124 # number of overall misses
system.cpu.l2cache.overall_hits 7082 # number of overall hits
system.cpu.l2cache.overall_miss_latency 23391500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.418077 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5088 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 9555668 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.411038 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 12466500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.418077 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5088 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -383,30 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 5124 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 5088 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3431.784338 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7342 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 3405.740601 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7082 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 68539351 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 2079138 # Number of cycles rename is blocking
system.cpu.numCycles 88528924 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 1217757 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1661115 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 25239317 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1954833 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 215732838 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 167129936 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 122925813 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 28288722 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 8966698 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 3960770 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 54498452 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 4706 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 484 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 9920797 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 473 # count of temporary serializing insts renamed
system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 511469 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 54000366 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 581686 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 190129267 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 147303303 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 108348051 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 25314451 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 6926673 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 1065045 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 39920690 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 4632 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 447 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2624388 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 437 # count of temporary serializing insts renamed
system.cpu.timesIdled 98 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------

1
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 754988 # Simulator instruction rate (inst/s)
host_mem_usage 150624 # Number of bytes of host memory used
host_seconds 121.73 # Real time elapsed on the host
host_tick_rate 377492666 # Simulator tick rate (ticks/s)
host_inst_rate 935813 # Simulator instruction rate (inst/s)
host_mem_usage 150648 # Number of bytes of host memory used
host_seconds 98.21 # Real time elapsed on the host
host_tick_rate 467904361 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903057 # Number of instructions simulated
sim_seconds 0.045952 # Number of seconds simulated

11
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

100
tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 335846 # Simulator instruction rate (inst/s)
host_mem_usage 156240 # Number of bytes of host memory used
host_seconds 273.71 # Real time elapsed on the host
host_tick_rate 216396349 # Simulator tick rate (ticks/s)
host_inst_rate 651405 # Simulator instruction rate (inst/s)
host_mem_usage 156232 # Number of bytes of host memory used
host_seconds 141.08 # Real time elapsed on the host
host_tick_rate 840119018 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903057 # Number of instructions simulated
sim_seconds 0.059229 # Number of seconds simulated
sim_ticks 59229023000 # Number of ticks simulated
sim_seconds 0.118528 # Number of seconds simulated
sim_ticks 118527938000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3629.746835 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2629.746835 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 13776.371308 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12776.371308 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1720500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 6530000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1246500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 6056000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3602.116705 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.116705 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 13970.251716 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12970.251716 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 6296500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 24420000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 4548500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 22672000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3608.010801 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 13928.892889 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency
system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 8017000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 30950000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5795000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 28728000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3608.010801 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 13928.892889 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 26495079 # number of overall hits
system.cpu.dcache.overall_miss_latency 8017000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 30950000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2222 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5795000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 28728000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1441.710869 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 1441.614290 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3077.908343 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2077.908343 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 12615.981199 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11615.981199 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 26193000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 107362000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 17683000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 98852000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3077.908343 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 12615.981199 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency
system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 26193000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 107362000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 17683000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 98852000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3077.908343 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 12615.981199 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 91894548 # number of overall hits
system.cpu.icache.overall_miss_latency 26193000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 107362000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_misses 8510 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 17683000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 98852000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1418.735069 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1418.637331 # Cycle average of tags in use
system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2703.820319 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1702.820319 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 12881000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 61932000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 8112236 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 52404000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2703.820319 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 12881000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 61932000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 8112236 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 52404000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2703.820319 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 6072 # number of overall hits
system.cpu.l2cache.overall_miss_latency 12881000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 61932000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4764 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 8112236 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 52404000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3173.029647 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 3172.809799 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 59229023000 # number of cpu cycles simulated
system.cpu.numCycles 118527938000 # number of cpu cycles simulated
system.cpu.num_insts 91903057 # Number of instructions executed
system.cpu.num_refs 26537109 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls

1
tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 668374 # Simulator instruction rate (inst/s)
host_mem_usage 150556 # Number of bytes of host memory used
host_seconds 289.41 # Real time elapsed on the host
host_tick_rate 334186387 # Simulator tick rate (ticks/s)
host_inst_rate 673586 # Simulator instruction rate (inst/s)
host_mem_usage 150548 # Number of bytes of host memory used
host_seconds 287.17 # Real time elapsed on the host
host_tick_rate 336792536 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435973 # Number of instructions simulated
sim_seconds 0.096718 # Number of seconds simulated

4
tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout
View file

@ -18,8 +18,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 27 2007 14:35:32
M5 started Fri Apr 27 16:03:50 2007
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 16:48:51 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav

11
tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

108
tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 490451 # Simulator instruction rate (inst/s)
host_mem_usage 156012 # Number of bytes of host memory used
host_seconds 394.40 # Real time elapsed on the host
host_tick_rate 342594746 # Simulator tick rate (ticks/s)
host_inst_rate 500598 # Simulator instruction rate (inst/s)
host_mem_usage 156000 # Number of bytes of host memory used
host_seconds 386.41 # Real time elapsed on the host
host_tick_rate 699597163 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193435973 # Number of instructions simulated
sim_seconds 0.135121 # Number of seconds simulated
sim_ticks 135120940500 # Number of ticks simulated
sim_seconds 0.270332 # Number of seconds simulated
sim_ticks 270331639000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3786.144578 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2786.144578 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 1885500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 6972000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 6474000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_miss_latency 14000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 13000 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits
system.cpu.dcache.SwapReq_miss_latency 3500 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency 14000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses
system.cpu.dcache.SwapReq_mshr_miss_latency 2500 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency 13000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3587.016575 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2587.016575 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 13987.108656 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12987.108656 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3895500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 15190000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 2809500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 14104000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3649.621212 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency
system.cpu.dcache.demand_avg_miss_latency 13991.161616 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency
system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 5781000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency 22162000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4197000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 20578000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3649.621212 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 13991.161616 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 76708968 # number of overall hits
system.cpu.dcache.overall_miss_latency 5781000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency 22162000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1584 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4197000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 20578000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 26 # number of replacements
system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1237.515646 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 1237.473868 # Cycle average of tags in use
system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 23 # number of writebacks
system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3066.269971 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2066.269971 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 12584.365830 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11584.365830 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 37617000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 154385000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 25349000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 142117000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3066.269971 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 12584.365830 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency
system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 37617000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 154385000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 25349000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 142117000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3066.269971 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 12584.365830 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 193423706 # number of overall hits
system.cpu.icache.overall_miss_latency 37617000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 154385000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
system.cpu.icache.overall_misses 12268 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 25349000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 142117000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 10342 # number of replacements
system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1591.858190 # Cycle average of tags in use
system.cpu.icache.tagsinuse 1591.809550 # Cycle average of tags in use
system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2720.824463 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.824463 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 14058500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 67171000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 8886333 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 56837000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses)
@ -174,29 +174,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2720.824463 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 14058500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 67171000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 8886333 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 56837000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2720.824463 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 8708 # number of overall hits
system.cpu.l2cache.overall_miss_latency 14058500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 67171000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5167 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 8886333 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 56837000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -213,12 +213,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3507.285738 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 3507.169610 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 135120940500 # number of cpu cycles simulated
system.cpu.numCycles 270331639000 # number of cpu cycles simulated
system.cpu.num_insts 193435973 # Number of instructions executed
system.cpu.num_refs 76732959 # Number of memory references
system.cpu.workload.PROG:num_syscalls 396 # Number of system calls

6
tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout
View file

@ -18,11 +18,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 27 2007 14:35:32
M5 started Fri Apr 27 16:08:41 2007
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 16:53:38 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 135120940500 because target called exit()
Exiting @ tick 270331639000 because target called exit()

13
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
View file

@ -33,9 +33,14 @@ symbolfile=
[system.bridge]
type=Bridge
delay=0
queue_size_a=16
queue_size_b=16
delay=100
fix_partial_write_a=false
fix_partial_write_b=true
nack_delay=8
req_size_a=16
req_size_b=16
resp_size_a=16
resp_size_b=16
write_ack=false
side_a=system.iobus.port[14]
side_b=system.membus.port[2]
@ -111,6 +116,7 @@ sys=system
[system.iobus]
type=Bus
children=responder
block_size=64
bus_id=0
clock=2
responder_set=false
@ -137,6 +143,7 @@ pio=system.iobus.default
[system.membus]
type=Bus
children=responder
block_size=64
bus_id=1
clock=2
responder_set=false

13
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out
View file

@ -69,6 +69,7 @@ bus_id=1
clock=2
width=64
responder_set=false
block_size=64
[system.intrctrl]
type=IntrControl
@ -103,10 +104,15 @@ zero=true
[system.bridge]
type=Bridge
queue_size_a=16
queue_size_b=16
delay=0
req_size_a=16
req_size_b=16
resp_size_a=16
resp_size_b=16
delay=100
nack_delay=8
write_ack=false
fix_partial_write_a=false
fix_partial_write_b=true
[system.disk0.image.child]
type=RawDiskImage
@ -361,6 +367,7 @@ bus_id=0
clock=2
width=64
responder_set=false
block_size=64
[system.iobus.responder]
type=IsaFake

8
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 571923 # Simulator instruction rate (inst/s)
host_mem_usage 373992 # Number of bytes of host memory used
host_seconds 3905.40 # Real time elapsed on the host
host_tick_rate 571972 # Simulator tick rate (ticks/s)
host_inst_rate 584673 # Simulator instruction rate (inst/s)
host_mem_usage 374168 # Number of bytes of host memory used
host_seconds 3820.23 # Real time elapsed on the host
host_tick_rate 584723 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 2233583679 # Number of instructions simulated
sim_seconds 1.116889 # Number of seconds simulated

10126
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr
View file

File diff suppressed because it is too large Load diff

4
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout
View file

@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Mar 30 2007 12:26:45
M5 started Fri Mar 30 12:26:47 2007
M5 compiled May 15 2007 17:08:10
M5 started Tue May 15 17:08:12 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Global frequency set at 2000000000 ticks per second

11
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -91,8 +91,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -267,8 +266,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -306,8 +304,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -339,6 +336,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -363,6 +361,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -249,7 +250,7 @@ type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -280,14 +281,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=20
write_buffers=8
@ -318,14 +318,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -356,7 +355,6 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.toL2Bus]
type=Bus
@ -364,4 +362,5 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64

482
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 606 # Number of BTB hits
global.BPredUnit.BTBLookups 1858 # Number of BTB lookups
global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted
global.BPredUnit.lookups 2195 # Number of BP lookups
global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target.
host_inst_rate 22780 # Simulator instruction rate (inst/s)
global.BPredUnit.BTBHits 524 # Number of BTB hits
global.BPredUnit.BTBLookups 1590 # Number of BTB lookups
global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted
global.BPredUnit.lookups 1843 # Number of BP lookups
global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target.
host_inst_rate 54565 # Simulator instruction rate (inst/s)
host_mem_usage 154084 # Number of bytes of host memory used
host_seconds 0.25 # Real time elapsed on the host
host_tick_rate 14337041 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 138 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit.
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 44392410 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 127 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1144 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5623 # Number of instructions simulated
sim_seconds 0.000004 # Number of seconds simulated
sim_ticks 3543500 # Number of ticks simulated
sim_seconds 0.000005 # Number of seconds simulated
sim_ticks 4588000 # Number of ticks simulated
system.cpu.commit.COM:branches 862 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 6315
system.cpu.commit.COM:committed_per_cycle.samples 8514
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 4255 6737.93%
1 915 1448.93%
2 408 646.08%
3 162 256.53%
4 140 221.69%
5 91 144.10%
6 121 191.61%
7 102 161.52%
8 121 191.61%
0 6195 7276.25%
1 1158 1360.11%
2 469 550.86%
3 176 206.72%
4 131 153.86%
5 99 116.28%
6 109 128.02%
7 73 85.74%
8 104 122.15%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1791 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 3588 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
system.cpu.cpi 1.635604 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.635604 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1475 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5928.571429 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5385 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1342 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 788500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.090169 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 538500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.067797 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 4501.457726 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1544000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 373500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 10.468208 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses
system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses
system.cpu.dcache.demand_accesses 2287 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 4900.210084 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1811 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2332500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.208133 # miss rate for demand accesses
system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 912000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.075645 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 2287 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 4900.210084 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1857 # number of overall hits
system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses
system.cpu.dcache.overall_misses 471 # number of overall misses
system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses
system.cpu.dcache.overall_hits 1811 # number of overall hits
system.cpu.dcache.overall_miss_latency 2332500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.208133 # miss rate for overall accesses
system.cpu.dcache.overall_misses 476 # number of overall misses
system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 912000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.075645 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use
system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 112.670676 # Cycle average of tags in use
system.cpu.dcache.total_refs 1811 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched
system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle
system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 144 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 10499 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 1848 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 682 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 1843 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1471 # Number of cache lines fetched
system.cpu.fetch.Cycles 3451 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 11450 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.200391 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1471 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 765 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.244971 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 7088
system.cpu.fetch.rateDist.samples 9197
system.cpu.fetch.rateDist.min_value 0
0 4755 6708.52%
1 197 277.93%
2 177 249.72%
3 163 229.97%
4 234 330.14%
5 170 239.84%
6 198 279.35%
7 114 160.84%
8 1080 1523.70%
0 7219 7849.30%
1 167 181.58%
2 147 159.83%
3 129 140.26%
4 200 217.46%
5 139 151.14%
6 181 196.80%
7 99 107.64%
8 916 995.98%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 1471 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5375.757576 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4524.038462 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1141 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1774000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.224337 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1411500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.212101 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 3.657051 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency
system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses
system.cpu.icache.demand_misses 328 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 1471 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5375.757576 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency
system.cpu.icache.demand_hits 1141 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1774000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.224337 # miss rate for demand accesses
system.cpu.icache.demand_misses 330 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1411500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.212101 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency
system.cpu.icache.overall_accesses 1471 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5375.757576 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1288 # number of overall hits
system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses
system.cpu.icache.overall_misses 328 # number of overall misses
system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses
system.cpu.icache.overall_hits 1141 # number of overall hits
system.cpu.icache.overall_miss_latency 1774000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.224337 # miss rate for overall accesses
system.cpu.icache.overall_misses 330 # number of overall misses
system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1411500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.212101 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -216,78 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use
system.cpu.icache.total_refs 1288 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 165.938349 # Cycle average of tags in use
system.cpu.icache.total_refs 1141 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.iew.EXEC:branches 1203 # Number of branches executed
system.cpu.iew.EXEC:nop 41 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate
system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 989 # Number of stores executed
system.cpu.idleCycles 2475 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1148 # Number of branches executed
system.cpu.iew.EXEC:nop 40 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.837338 # Inst execution rate
system.cpu.iew.EXEC:refs 2524 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 977 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 5598 # num instructions consuming a value
system.cpu.iew.WB:count 7767 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back
system.cpu.iew.WB:consumers 5205 # num instructions consuming a value
system.cpu.iew.WB:count 7402 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.742747 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 4153 # num instructions producing a value
system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle
system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions
system.cpu.iew.WB:producers 3866 # num instructions producing a value
system.cpu.iew.WB:rate 0.804828 # insts written-back per cycle
system.cpu.iew.WB:sent 7467 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 374 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 1876 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1144 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 9245 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1547 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 280 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 682 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 50 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued
system.cpu.iew.lsq.thread.0.squashedLoads 897 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 332 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.611395 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 2 0.02% # Type of FU issued
IntAlu 5713 66.97% # Type of FU issued
(null) 2 0.03% # Type of FU issued
IntAlu 5322 66.68% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatAdd 2 0.03% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 1773 20.78% # Type of FU issued
MemWrite 1040 12.19% # Type of FU issued
MemRead 1662 20.82% # Type of FU issued
MemWrite 992 12.43% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
IntAlu 7 5.47% # attempts to use FU when none available
IntAlu 0 0.00% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@ -296,43 +297,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 78 60.94% # attempts to use FU when none available
MemWrite 43 33.59% # attempts to use FU when none available
MemRead 71 66.98% # attempts to use FU when none available
MemWrite 35 33.02% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 7088
system.cpu.iq.ISSUE:issued_per_cycle.samples 9197
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 4068 5739.28%
1 771 1087.75%
2 763 1076.47%
3 485 684.26%
4 504 711.06%
5 295 416.20%
6 144 203.16%
7 40 56.43%
8 18 25.40%
0 5952 6471.68%
1 1107 1203.65%
2 919 999.24%
3 442 480.59%
4 375 407.74%
5 250 271.83%
6 115 125.04%
7 26 28.27%
8 11 11.96%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate
system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles
system.cpu.iq.ISSUE:rate 0.867783 # Inst issue rate
system.cpu.iq.iqInstsAdded 9183 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 7981 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3171 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2045 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4639.751553 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2463.768116 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 2241000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1190000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
@ -341,32 +342,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency
system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4639.751553 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 2241000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 1190000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4639.751553 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 2241000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 485 # number of overall misses
system.cpu.l2cache.overall_misses 483 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 1190000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -379,28 +380,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 278.222582 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 7088 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking
system.cpu.numCycles 9197 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
system.cpu.rename.RENAME:IdleCycles 6383 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 12854 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 7485 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 1746 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 682 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 3434 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
system.cpu.timesIdled 25 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2007 21:50:58
M5 started Sat Apr 21 21:51:06 2007
M5 executing on zamp.eecs.umich.edu
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:39 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 3543500 because target called exit()
Exiting @ tick 4588000 because target called exit()

1
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
View file

@ -48,6 +48,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

1
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess

8
tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 357156 # Simulator instruction rate (inst/s)
host_mem_usage 148180 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 171417285 # Simulator tick rate (ticks/s)
host_inst_rate 576538 # Simulator instruction rate (inst/s)
host_mem_usage 148208 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 276546720 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated

6
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2007 21:50:58
M5 started Sat Apr 21 21:51:08 2007
M5 executing on zamp.eecs.umich.edu
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:40 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2820500 because target called exit()

11
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
View file

@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=1000
lifo=false
max_miss_count=0
mshrs=10
@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
latency=10000
lifo=false
max_miss_count=0
mshrs=10
@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
@ -171,6 +169,7 @@ uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false

11
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
View file

@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.workload]
type=LiveProcess
@ -61,13 +62,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -98,14 +100,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -136,14 +137,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@ -174,5 +174,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1

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