2011-02-08 04:23:11 +01:00
---------- Begin Simulation Statistics ----------
2015-03-02 11:04:20 +01:00
sim_seconds 0.000021 # Number of seconds simulated
2015-09-25 13:27:03 +02:00
sim_ticks 20818000 # Number of ticks simulated
final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-02-08 04:23:11 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-09-25 13:27:03 +02:00
host_inst_rate 48919 # Simulator instruction rate (inst/s)
host_op_rate 88616 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 189245943 # Simulator tick rate (ticks/s)
host_mem_usage 313416 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
2012-08-15 16:38:05 +02:00
sim_insts 5380 # Number of instructions simulated
2013-03-11 23:45:09 +01:00
sim_ops 9747 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-09-15 15:14:09 +02:00
system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory
system.physmem.bytes_read::total 26560 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory
system.physmem.num_reads::total 415 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::cpu.inst 848496493 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 427322509 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1275819003 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 848496493 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 848496493 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 848496493 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 427322509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1275819003 # Total bandwidth to/from this memory (bytes/s)
2015-09-15 15:14:09 +02:00
system.physmem.readReqs 415 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2015-09-15 15:14:09 +02:00
system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2015-09-15 15:14:09 +02:00
system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2015-09-15 15:14:09 +02:00
system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::0 32 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::1 1 # Per bank write bursts
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::2 6 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::3 8 # Per bank write bursts
system.physmem.perBankRdBursts::4 50 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::5 46 # Per bank write bursts
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::6 21 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::7 33 # Per bank write bursts
system.physmem.perBankRdBursts::8 25 # Per bank write bursts
system.physmem.perBankRdBursts::9 72 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::10 63 # Per bank write bursts
2015-09-15 15:14:09 +02:00
system.physmem.perBankRdBursts::11 16 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 2 # Per bank write bursts
system.physmem.perBankRdBursts::13 17 # Per bank write bursts
system.physmem.perBankRdBursts::14 6 # Per bank write bursts
system.physmem.perBankRdBursts::15 17 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-09-25 13:27:03 +02:00
system.physmem.totGap 20722000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-09-15 15:14:09 +02:00
system.physmem.readPktSize::6 415 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.bytesPerActivate::samples 96 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 252 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 164.484740 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 262.126687 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 35 36.46% 36.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 26 27.08% 63.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 15 15.62% 79.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 6 6.25% 85.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3 3.12% 88.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 3.12% 91.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 2.08% 93.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 1.04% 94.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 5.21% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 96 # Bytes accessed per row activation
system.physmem.totQLat 4745000 # Total ticks spent queuing
system.physmem.totMemAccLat 12526250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-09-15 15:14:09 +02:00
system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 1275.82 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBWSys 1275.82 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-09-15 15:14:09 +02:00
system.physmem.busUtil 9.97 # Data bus utilization in percentage
system.physmem.busUtilRead 9.97 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-09-15 15:14:09 +02:00
system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2015-09-15 15:14:09 +02:00
system.physmem.readRowHits 309 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2015-09-15 15:14:09 +02:00
system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2015-09-25 13:27:03 +02:00
system.physmem.avgGap 49932.53 # Average gap between requests
2015-09-15 15:14:09 +02:00
system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 959400 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2015-03-02 11:04:20 +01:00
system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_0.totalEnergy 13105245 # Total energy per rank (pJ)
system.physmem_0.averagePower 827.743250 # Core power per rank (mW)
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.actEnergy 423360 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 231000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1536600 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
2015-09-15 15:14:09 +02:00
system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 14021235 # Total energy per rank (pJ)
system.physmem_1.averagePower 885.598295 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 271750 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.lookups 3234 # Number of BP lookups
system.cpu.branchPred.condPredicted 3234 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 514 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 2557 # Number of BTB lookups
system.cpu.branchPred.BTBHits 881 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-09-15 15:14:09 +02:00
system.cpu.branchPred.BTBHitPct 34.454439 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 86 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 11 # Number of system calls
2015-09-25 13:27:03 +02:00
system.cpu.numCycles 41637 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-15 15:14:09 +02:00
system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 14637 # Number of instructions fetch has processed
system.cpu.fetch.Branches 3234 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1161 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9674 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1159 # Number of cycles fetch has spent squashing
2015-07-03 16:15:03 +02:00
system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
2015-09-15 15:14:09 +02:00
system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.CacheLines 2075 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 22725 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.149527 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.648759 # Number of instructions fetched each cycle (Total)
2011-02-08 04:23:11 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.rateDist::0 18699 82.28% 82.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 221 0.97% 83.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 146 0.64% 83.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 231 1.02% 84.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 214 0.94% 85.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 258 1.14% 86.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 336 1.48% 88.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 205 0.90% 89.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2415 10.63% 100.00% # Number of instructions fetched each cycle (Total)
2011-02-08 04:23:11 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-09-15 15:14:09 +02:00
system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu.fetch.branchRate 0.077671 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.351538 # Number of inst fetches per cycle
2015-09-15 15:14:09 +02:00
system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3206 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 406 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 579 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 24310 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 579 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 11710 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1815 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1004 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 3327 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4290 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 23005 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 71 # Number of times rename has blocked due to IQ full
2015-07-03 16:15:03 +02:00
system.cpu.rename.SQFullEvents 4163 # Number of times rename has blocked due to SQ full
2015-09-15 15:14:09 +02:00
system.cpu.rename.RenamedOperands 26169 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 57126 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 32219 # Number of integer rename lookups
2013-10-16 16:44:12 +02:00
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
2013-03-11 23:45:09 +01:00
system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
2015-09-15 15:14:09 +02:00
system.cpu.rename.UndoneMaps 15106 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 1472 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2371 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1574 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 20 # Number of conflicting loads.
2014-06-22 23:33:09 +02:00
system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
2015-09-15 15:14:09 +02:00
system.cpu.iq.iqInstsAdded 20445 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 17161 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 10724 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 15317 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 22725 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.755160 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.702113 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::0 17737 78.05% 78.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1126 4.95% 83.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 880 3.87% 86.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 631 2.78% 89.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 810 3.56% 93.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 590 2.60% 95.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 568 2.50% 98.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 280 1.23% 99.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 103 0.45% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-09-15 15:14:09 +02:00
system.cpu.iq.issued_per_cycle::total 22725 # Number of insts issued each cycle
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-09-15 15:14:09 +02:00
system.cpu.iq.fu_full::IntAlu 151 71.23% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.23% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 43 20.28% 91.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 18 8.49% 100.00% # attempts to use FU when none available
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2013-03-11 23:45:09 +01:00
system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::IntAlu 13707 79.87% 79.89% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 4 0.02% 79.91% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.95% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2071 12.07% 92.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Type of FU issued
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::total 17161 # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.rate 0.412157 # Inst issue rate
2015-09-15 15:14:09 +02:00
system.cpu.iq.fu_busy_cnt 212 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 31202 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 15767 # Number of integer instruction queue wakeup accesses
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
2015-04-23 05:22:29 +02:00
system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
2011-05-23 17:59:13 +02:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
2015-09-15 15:14:09 +02:00
system.cpu.iq.int_alu_accesses 17366 # Number of integer alu accesses
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.forwLoads 220 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 1318 # Number of loads squashed
2013-05-30 18:54:18 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 639 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2014-06-22 23:33:09 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2015-09-15 15:14:09 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-09-15 15:14:09 +02:00
system.cpu.iew.iewSquashCycles 579 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1449 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 20471 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2371 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1574 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 136 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 660 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 16265 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1913 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 896 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
2015-09-15 15:14:09 +02:00
system.cpu.iew.exec_refs 3175 # number of memory reference insts executed
system.cpu.iew.exec_branches 1626 # Number of branches executed
system.cpu.iew.exec_stores 1262 # Number of stores executed
2015-09-25 13:27:03 +02:00
system.cpu.iew.exec_rate 0.390638 # Inst execution rate
2015-09-15 15:14:09 +02:00
system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 15771 # cumulative count of insts written-back
system.cpu.iew.wb_producers 10637 # num instructions producing a value
system.cpu.iew.wb_consumers 16589 # num instructions consuming a value
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2015-09-25 13:27:03 +02:00
system.cpu.iew.wb_rate 0.378774 # insts written-back per cycle
2015-09-15 15:14:09 +02:00
system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2015-09-15 15:14:09 +02:00
system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
2015-09-15 15:14:09 +02:00
system.cpu.commit.branchMispredicts 565 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 20943 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.465406 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.357230 # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-09-15 15:14:09 +02:00
system.cpu.commit.committed_per_cycle::0 17686 84.45% 84.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 994 4.75% 89.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 561 2.68% 91.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 764 3.65% 95.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 370 1.77% 97.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 129 0.62% 97.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 114 0.54% 98.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 70 0.33% 98.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 255 1.22% 100.00% # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-09-15 15:14:09 +02:00
system.cpu.commit.committed_per_cycle::total 20943 # Number of insts commited each cycle
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 5380 # Number of instructions committed
2013-03-11 23:45:09 +01:00
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 1988 # Number of memory references committed
system.cpu.commit.loads 1053 # Number of loads committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 1208 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 9653 # Number of committed integer instructions.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 106 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
2015-09-15 15:14:09 +02:00
system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 41158 # The number of ROB reads
system.cpu.rob.rob_writes 42744 # The number of ROB writes
system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
2015-09-25 13:27:03 +02:00
system.cpu.idleCycles 18912 # Total number of cycles that the CPU has spent unscheduled due to idling
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 5380 # Number of Instructions Simulated
2013-03-11 23:45:09 +01:00
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
2015-09-25 13:27:03 +02:00
system.cpu.cpi 7.739219 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.739219 # CPI: Total CPI of All Threads
system.cpu.ipc 0.129212 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.129212 # IPC: Total IPC of All Threads
2015-09-15 15:14:09 +02:00
system.cpu.int_regfile_reads 20871 # number of integer regfile reads
system.cpu.int_regfile_writes 12651 # number of integer regfile writes
2011-05-23 17:59:13 +02:00
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
2015-09-15 15:14:09 +02:00
system.cpu.cc_regfile_reads 8081 # number of cc regfile reads
system.cpu.cc_regfile_writes 4880 # number of cc regfile writes
system.cpu.misc_regfile_reads 7277 # number of misc regfile reads
2013-03-11 23:45:09 +01:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.tagsinuse 81.973847 # Cycle average of tags in use
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 81.973847 # Average occupied blocks per requestor
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5305 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5305 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1525 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1525 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2383 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2383 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2383 # number of overall hits
system.cpu.dcache.overall_hits::total 2383 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 200 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 200 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 200 # number of overall misses
system.cpu.dcache.overall_misses::total 200 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9653500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9653500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 6433000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 16086500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 16086500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 16086500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 16086500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1648 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1648 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
2015-09-15 15:14:09 +02:00
system.cpu.dcache.demand_accesses::cpu.data 2583 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2583 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2583 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2583 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074636 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.074636 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.077429 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.077429 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.077429 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.077429 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78483.739837 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 78483.739837 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83545.454545 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 83545.454545 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 80432.500000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 80432.500000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 80432.500000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 80432.500000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-09-15 15:14:09 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.250000 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-09-15 15:14:09 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 61 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5286500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5286500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6356000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6356000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11642500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11642500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11642500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11642500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037621 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037621 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.053813 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.053813 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.053813 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.053813 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85266.129032 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85266.129032 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82545.454545 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82545.454545 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 0 # number of replacements
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.tagsinuse 130.304167 # Cycle average of tags in use
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.total_refs 1706 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 277 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.158845 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 130.304167 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.063625 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.063625 # Average percentage of cache occupancy
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 277 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4427 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1706 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1706 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1706 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1706 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1706 # number of overall hits
system.cpu.icache.overall_hits::total 1706 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
system.cpu.icache.overall_misses::total 369 # number of overall misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28132500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28132500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28132500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28132500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28132500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28132500 # number of overall miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 2075 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2075 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2075 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2075 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2075 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2075 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.177831 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.177831 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.177831 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.177831 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.177831 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.177831 # miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76239.837398 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76239.837398 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76239.837398 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76239.837398 # average overall miss latency
2014-06-22 23:33:09 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014-06-22 23:33:09 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2014-06-22 23:33:09 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 277 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 277 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22319000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 22319000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22319000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 22319000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22319000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22319000 # number of overall MSHR miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133494 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.133494 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.133494 # mshr miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80574.007220 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80574.007220 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.tagsinuse 162.380689 # Cycle average of tags in use
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.343988 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 32.036700 # Average occupied blocks per requestor
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003978 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000978 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.004955 # Average percentage of cache occupancy
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.tag_accesses 3743 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3743 # Number of data accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 276 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 276 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 62 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 62 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 139 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 139 # number of overall misses
system.cpu.l2cache.overall_misses::total 415 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6240500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6240500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21891500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 21891500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5193000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5193000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 21891500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11433500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 33325000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 21891500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11433500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 33325000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 277 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 277 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 62 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 277 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 139 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 416 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 277 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 139 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 416 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996390 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996390 # miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996390 # miss rate for demand accesses
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.997596 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996390 # miss rate for overall accesses
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.997596 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81045.454545 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81045.454545 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79317.028986 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79317.028986 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83758.064516 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83758.064516 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79317.028986 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82255.395683 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80301.204819 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79317.028986 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82255.395683 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80301.204819 # average overall miss latency
2011-02-08 04:23:11 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
2011-02-08 04:23:11 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 276 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 276 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 62 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 62 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5470500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5470500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19131500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19131500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4573000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4573000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19131500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10043500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 29175000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19131500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10043500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 29175000 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996390 # mshr miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for demand accesses
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997596 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for overall accesses
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997596 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71045.454545 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71045.454545 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69317.028986 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69317.028986 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73758.064516 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73758.064516 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 277 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 554 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 832 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17728 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 0.002404 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.049029 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::0 415 99.76% 99.76% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 415500 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadResp 338 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadExReq 77 # Transaction distribution
system.membus.trans_dist::ReadExResp 77 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 338 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 830 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 830 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 830 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26560 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26560 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 26560 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::samples 415 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::0 415 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::total 415 # Request fanout histogram
system.membus.reqLayer0.occupancy 500000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
2015-09-15 15:14:09 +02:00
system.membus.respLayer1.occupancy 2216750 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.membus.respLayer1.utilization 10.6 # Layer utilization (%)
2011-02-08 04:23:11 +01:00
---------- End Simulation Statistics ----------
