Commit graph

709 commits

Author SHA1 Message Date
Gabe Black
f985b752d3 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
2006-10-27 02:34:26 -04:00
Gabe Black
709d50cd6b Got rid of some outdated comments.
--HG--
extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
2006-10-27 01:43:51 -04:00
Gabe Black
b1cc98ed54 Made the regfile compatible with the new definitions in MiscRegFile
--HG--
extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
2006-10-27 01:43:26 -04:00
Gabe Black
944bfde6b3 Clean up MiscRegFile
--HG--
extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
2006-10-27 01:36:42 -04:00
Gabe Black
2cb190d1e3 Reorganized the MiscRegFile
--HG--
extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
2006-10-26 22:48:02 -04:00
Gabe Black
f33bab2386 Cleaned up the decoder slightly.
--HG--
extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
2006-10-26 22:47:17 -04:00
Gabe Black
f88b90dd56 Added a few functions to stuff values into bitfields in an instruction.
--HG--
extra : convert_revision : 507d7e13fd6276acf36b75eba31dff5e8080113f
2006-10-26 20:25:22 -04:00
Gabe Black
d1b30102fd Changed the number of register windows to be more realistic.
--HG--
extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
2006-10-26 20:24:01 -04:00
Gabe Black
5024b20278 Got rid of some debug output
--HG--
extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
2006-10-26 20:23:00 -04:00
Gabe Black
e441be1b82 Change the default function from setMiscRegWithEffect to setMiscReg
--HG--
extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
2006-10-26 20:22:23 -04:00
Ali Saidi
d626a32c52 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 473901bcd44bd2c563a3293d7326cd5aed8b630f
2006-10-26 15:49:19 -04:00
Ali Saidi
f4be29804f Fix simple timing port keep a list of all packets, have only one event, and scan all packets on a functional access.
--HG--
extra : convert_revision : c735a6408443b5cc90d1c1841c7aeb61e02ec6ae
2006-10-25 18:34:21 -04:00
Gabe Black
93b3176d4e Fixed the priv instruction format.
src/arch/sparc/isa/formats/priv.isa:
    Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
    Added an Hpstate operand, and adjusted the numbering.

--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
2006-10-25 17:58:44 -04:00
Gabe Black
99d9d40e6c Implemented the saved and restored instructions, fixed up register window instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction.
--HG--
extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
2006-10-25 17:54:14 -04:00
Gabe Black
047455625e Fixed the bitfield FCN to include the right bits.
--HG--
extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
2006-10-25 17:50:39 -04:00
Gabe Black
e2eef8859b Implemented the SPARC fill and spill handlers.
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
    Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.

--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
2006-10-25 17:49:41 -04:00
Ron Dreslinski
eda7148af2 Fix fixPacket functionality to calculate sizes properly
src/mem/packet.cc:
    Copy size is calculated by END-BEGIN not BEGIN-END

--HG--
extra : convert_revision : 0e2725c5551f8f70ff05cb285e0822afc0bb3f87
2006-10-25 14:14:37 -04:00
Gabe Black
1b1495930c Replace the Alpha No op with a SPARC one.
--HG--
extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
2006-10-24 15:50:41 -04:00
Ali Saidi
0f98905ecc Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 4db140e6e8408b3ed39da327515b8e88a2701e6b
2006-10-24 12:59:19 -04:00
Ali Saidi
650ebe4ec3 Add more traceflags for ethernet
--HG--
extra : convert_revision : a5025f501d72626d1bcb4dcc24ee353ceb160ce7
2006-10-24 12:59:07 -04:00
Steve Reinhardt
06482e6eed Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : a077304e608753f50f4a12216901d156469eebe4
2006-10-24 11:50:20 -04:00
Lisa Hsu
764f27a0c9 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
2006-10-23 18:46:05 -04:00
Lisa Hsu
4da3938ed9 get rid of the "resume" step at the end of changeToTiming/Atomic because this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok.
--HG--
extra : convert_revision : 7530cf140844e18cc26df80057f8760f29ec952b
2006-10-23 18:45:30 -04:00
Lisa Hsu
0a2387f38c make this parallel to the other cpu types so that resume works correctly.
--HG--
extra : convert_revision : 3c165af27ea0e6c7f2a17819c1717d8900f54cc1
2006-10-23 18:43:56 -04:00
Gabe Black
ef8b7713ca Minor compile fix. Not sure why this is broken.
--HG--
extra : convert_revision : 6f181b15f37114ca0a3965cabcb2036bd2f97916
2006-10-23 11:17:59 -04:00
Gabe Black
18b2d94b8c Move around more SPARC memory code, and make block memory operations work with the timing cpu
--HG--
extra : convert_revision : 37358504c4d05d78d08c19ba3d0c99d38c4babf5
2006-10-23 11:17:15 -04:00
Gabe Black
466c387318 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
2006-10-23 09:44:58 -04:00
Gabe Black
20208d00e6 Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description.
--HG--
rename : src/arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats/formats.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/basicmem.isa
rename : src/arch/sparc/isa/formats/blockmem.isa => src/arch/sparc/isa/formats/mem/blockmem.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/mem.isa
extra : convert_revision : dbbb00f997a102871b084b209b9fa08c5e1853ee
2006-10-23 07:55:52 -04:00
Gabe Black
e9908e3c85 Don't let interupts interupt microcode at undesired points.
--HG--
extra : convert_revision : a8ddc6b213b1a1b0d9c5cd194b88ac0c6bfb2a21
2006-10-23 02:39:02 -04:00
Gabe Black
a8973c6054 Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <inttypes.hh>
--HG--
extra : convert_revision : c1e46c012a26cdb0603416f8e8a99e0ecb1c09bc
2006-10-23 02:37:54 -04:00
Gabe Black
f31d73a433 Start making memory ops work with InitiateAcc and CompleteAcc, and some minor cleanups
--HG--
extra : convert_revision : 178a8c5d0506c75ad7a7e8d691c8863235ed7e95
2006-10-23 02:36:46 -04:00
Gabe Black
3d6ff82552 Change the default constructors to take ExtMachInsts rather than regular MachInsts
--HG--
extra : convert_revision : 8fa34f82e0cbf5ce81775d572b182826c578581f
2006-10-23 02:32:58 -04:00
Steve Reinhardt
e321a21e27 Clean up cache DPRINTFs
--HG--
extra : convert_revision : f836e77efd40e25259d7794dd148696586b79a09
2006-10-22 21:07:38 -07:00
Steve Reinhardt
1b21d9ba5e s/pktuest/request/ (all in comments)
--HG--
extra : convert_revision : 7ce779242a15245a20322c0b6c40d02c8ddd15ad
2006-10-22 20:38:34 -07:00
Steve Reinhardt
199084b339 Add DPRINTF for non-timed quiesce.
--HG--
extra : convert_revision : 5487f4fc07dbea6e5a651c104ea1d2fe864fb057
2006-10-22 16:22:45 -07:00
Steve Reinhardt
5e2263fc52 Small bug fixes for timing LL/SC. Better now but
not necessarily 100% there yet.

src/mem/cache/cache_impl.hh:
    Generate response packet on failed store conditional.
src/mem/packet.hh:
    Clear packet flags when reinitializing.
    (SATISFIED in particular is one we don't want to leave set.)

--HG--
extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
2006-10-21 23:35:00 -07:00
Steve Reinhardt
0159529343 Add Quiesce trace flag to track CPU quiesce/wakeup events.
--HG--
extra : convert_revision : 23be99d0fe6e2184523efe5d9e0a1ac7bf19d087
2006-10-21 23:32:14 -07:00
Steve Reinhardt
883ed108e4 Just give up if a store conditional misses completely
in the cache (don't treat as normal write miss).

--HG--
extra : convert_revision : c030eb6ba25318cae422e4da31e3b802049c8c74
2006-10-21 17:19:33 -07:00
Steve Reinhardt
82e90bf5e0 Fix formatting that got screwed up when tabs were removed.
--HG--
extra : convert_revision : 98596542a5774fe010e25632836ce92b66779f53
2006-10-21 13:54:48 -07:00
Steve Reinhardt
1e6aa0d0d0 Refactor coherence state table initialization.
--HG--
extra : convert_revision : eb36dd2cc1463e5076f4758a59cf68cc6b2bafc5
2006-10-21 13:43:14 -07:00
Steve Reinhardt
3ac1ca8ff6 Tweak a few things for better page fault debugging.
src/sim/faults.cc:
    Fix fault message.
src/kern/tru64/tru64.hh:
    Add DPRINTF to see where new thread stacks are allocated.
src/arch/alpha/faults.cc:
    Add print statement so we know what the faulting address is in SE mode.

--HG--
extra : convert_revision : 6eb2b513c339496a0d013b7e914953a0a066c12d
2006-10-21 05:28:05 -04:00
Nathan Binkert
dff1a022b8 Missing case
--HG--
extra : convert_revision : 128896dd1a654fe9a02e2c07ef6ce6799b62f21f
2006-10-21 00:31:46 -07:00
Gabe Black
0b5cf4ba6e Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
2006-10-20 16:39:47 -04:00
Nathan Binkert
6c6b78126a Construct a correct value of PYTHONHOME from the interpreter
running SCons, make it into a sticky option that can be
overridden at build time, and set it up before the interpreter
is started.  Also, fix the code that turns sticky options into
config/*.hh so that it works with types other than bool.

--HG--
extra : convert_revision : 602398b35d4da4e813f78865678ed348fdea7270
2006-10-20 11:37:59 -07:00
Ron Dreslinski
ba24ce6bb6 Get rid of a variable put back by merge.
--HG--
extra : convert_revision : 5ddb6ae5d5412f062c07c16a27b79483430b5f22
2006-10-20 13:05:39 -04:00
Ron Dreslinski
54ed57cc4c Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/tport.cc:
    Merge PacketPtr changes

--HG--
extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
2006-10-20 13:04:59 -04:00
Ron Dreslinski
28e9641c2c Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
    Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Use fix Packet function
src/mem/packet.cc:
    Fix an assert that was checking the wrong thing
src/mem/tport.cc:
    Properly detect if we need to do the access to the functional device

--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
2006-10-20 13:01:21 -04:00
Ali Saidi
7be58fd5f4 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : c0f9bde20585b3811ff906728b003072b69696b5
2006-10-20 13:00:15 -04:00
Ali Saidi
32384b2f6b still working on getting past initialization
--HG--
extra : convert_revision : 7a5fccb9a19d363e479ef24012a7b8598272eaa9
2006-10-20 13:00:05 -04:00
Nathan Binkert
a4c6f0d69e Use PacketPtr everywhere
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-20 00:10:12 -07:00
Nathan Binkert
7245d4530d refactor code for the packet, get rid of packet_impl.hh
and call it packet_access.hh and fix the #includes so
things compile right.

--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-19 23:38:45 -07:00
Nathan Binkert
5b246a0567 initialize end, clean up loop
--HG--
extra : convert_revision : e1c107f0c0fd5d535acd2d6c43571a5df57c9ed3
2006-10-19 23:35:59 -07:00
Nathan Binkert
b937d54510 Fix compile of m5.fast
--HG--
extra : convert_revision : a8a37c318e55e48e697e4aaba339328f000b3f60
2006-10-19 23:34:59 -07:00
Ron Dreslinski
780aa0a0eb Fix corner case on assertion.
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.

src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Fix corner case on assertion
tests/configs/memtest.py:
    Updated memtester with uncacheable addresses and functional accesses

--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
2006-10-19 21:26:46 -04:00
Ron Dreslinski
cc1feb9f6d Fix memtester to use functional access, fix cache to work functionally now that we could test it.
src/cpu/memtest/memtest.cc:
    Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
    Fix cache to handle functional accesses properly based on memtester changes
    Still need to fix functional accesses in timing mode now that the memtester can test it.

--HG--
extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
2006-10-19 21:07:53 -04:00
Ron Dreslinski
210e73f2a2 Small changes:
?? doesn't compile in warn statements
Should have been false, where I had a true.

src/cpu/o3/lsq_impl.hh:
    Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
    Forgot to signal atomic mode in snoopProbe

--HG--
extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
2006-10-19 20:18:17 -04:00
Ron Dreslinski
e34e564f79 Fixes to get single level uni-coherence to work.
Now to try L2 caches in FS.

src/mem/cache/base_cache.hh:
    Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
    Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
    Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Properly forward invalidates in atomic/timing uni-coherence

--HG--
extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7
2006-10-19 20:02:57 -04:00
Ron Dreslinski
9cf063eb8e Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
2006-10-19 19:00:43 -04:00
Ron Dreslinski
39d24f7241 Always get the functional access from the highest level of cache first.
src/mem/cache/cache_impl.hh:
    Get the read data from the highest level of cache on a functional access

--HG--
extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
2006-10-19 19:00:27 -04:00
Steve Reinhardt
11f0badbaa Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 8a70922250092c013fa4db6d83254b438ee6c4be
2006-10-19 13:33:08 -04:00
Steve Reinhardt
a78e92381b Add "All" compund flag to enable all defined trace flags.
--HG--
extra : convert_revision : dcc699d8341f762dee659290cd35206e326e1179
2006-10-19 10:32:08 -07:00
Steve Reinhardt
e78684fc6c Add new event priority for trace enable events so
that tracing gets turned on as the very first thing
in the selected cycle (tick).

--HG--
extra : convert_revision : c08f749ca42782af1b48e5aa5f0860bf7076bd3c
2006-10-19 10:21:23 -07:00
Steve Reinhardt
bba3dfb0d3 First cut at LL/SC support in caches (atomic mode only).
configs/example/fs.py:
    Add MOESI protocol to caches (uni coherence not quite working w/FS yet).

--HG--
extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
2006-10-19 00:33:33 -07:00
Gabe Black
54c9701a25 Zeroed out the actual LSB in addition to moving it's original value the MSB.
--HG--
extra : convert_revision : d29efe01781d72ee6e61818e7b93972262c0616b
2006-10-18 20:53:59 -04:00
Gabe Black
bb2ab310eb Fixed up exetrace.cc to deal with microcode, and to made floating point register numbers correlate to the numbers used in SPARC in m5 and statetrace.
src/cpu/exetrace.cc:
    Fixed up to deal with microcode, and to make floating point register numbers correlate to the numbers used in SPARC.
util/statetrace/arch/tracechild_sparc.cc:
util/statetrace/arch/tracechild_sparc.hh:
    Make floating point register numbers correlate to the numbers used in SPARC.

--HG--
extra : convert_revision : 878897292f696092453cf61d6eac2d1c407ca13b
2006-10-18 20:52:34 -04:00
Gabe Black
849d5e2efb Fixed a compiler error, disassembly output, and corrected the address calculation.
--HG--
extra : convert_revision : d34b3c0443064addb6f454ac70fbaeda0678e329
2006-10-18 20:48:08 -04:00
Gabe Black
94926a72e9 Fixed up ldblockf_p, implemented stdfa properly, and got rid of some old code.
--HG--
extra : convert_revision : 263b4b835d6d1bc9049acdc1398286277bede97a
2006-10-18 20:44:51 -04:00
Lisa Hsu
75ecd3be60 how did i not commit this already? the other way doesn't seem to work, need to convert to System ptr first to access System method.
src/python/m5/SimObject.py:
    how did i not commit this already?  the other way doesn't seem to work.

--HG--
extra : convert_revision : 55737d3d10742a1913a376d1febbc5809f2fab8f
2006-10-18 18:04:53 -04:00
Lisa Hsu
15770fb7b4 need some initializations before doing the loop.
--HG--
extra : convert_revision : e5e8b16ae4f119c923d8c0d295aa9569d7a8fe5b
2006-10-18 18:01:33 -04:00
Lisa Hsu
c2c48645c9 only do this assert after you know you're not switched out or idle.
--HG--
extra : convert_revision : 0cd0d31db44fe7e8e44bde90e1756873faca422f
2006-10-18 17:59:11 -04:00
Ron Dreslinski
5bcdc74fe2 Fix WriteInvalidateResp
--HG--
extra : convert_revision : ac4281944202a9a2f166b305a1eaea507e484bcc
2006-10-18 16:38:02 -04:00
Ron Dreslinski
63c2a782d6 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
2006-10-18 13:34:52 -04:00
Steve Reinhardt
0e2561710b Break a lot of overly long lines.
Factor out some asserts that were on both
sides of an if/else.

--HG--
extra : convert_revision : 78f0c2d76a81a98216b2f281159c6b6ea0147731
2006-10-18 08:41:05 -07:00
Steve Reinhardt
caf123586f Get rid of doData() lines (were already commented out).
Reindent due to resulting changes in nesting.

--HG--
extra : convert_revision : 6be099d572efb618efb08fbc06d7e0e4b5b4cab2
2006-10-18 08:24:24 -07:00
Steve Reinhardt
6cd187e1f0 Get rid of obsolete in-cache copy support.
--HG--
extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
2006-10-18 08:16:22 -07:00
Steve Reinhardt
f735399b39 Include packet_impl.hh (need this on my laptop,
but not on zizzer... g++ 4 thing maybe?)

--HG--
extra : convert_revision : 31c49f1c55fe9daf6365411bfb5bb7f6ccc8032d
2006-10-17 21:16:17 -07:00
Steve Reinhardt
05c487ef3c Enable MP systems via cmd-line flag in fs.py.
configs/example/fs.py:
    Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
    Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
    Don't need to set console & intrcontrol cpu
    params anymore (default is fixed now).

--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
2006-10-17 21:15:11 -07:00
Ali Saidi
e51b075a27 add code to serialize se structures. Lisa is working on the python side of things and will test
src/mem/page_table.cc:
src/mem/page_table.hh:
    add code to serialize/unserialize page table
src/sim/process.cc:
src/sim/process.hh:
    add code to serialize/unserialize process

--HG--
extra : convert_revision : ee9eb5e2c38c5d317a2f381972c552d455e0db9e
2006-10-17 19:38:36 -04:00
Ron Dreslinski
9c582c7e14 Fixes for uni-coherence in timing mode for FS.
Still a bug in atomic uni-coherence in FS.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
    Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
    Only deallocate once

--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
2006-10-17 18:50:19 -04:00
Ron Dreslinski
4fff6d4603 Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request.
Still need to rework upgrades into this system, but works for now.

src/mem/cache/base_cache.cc:
    Re order code to be more readable
src/mem/cache/base_cache.hh:
    Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
    Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
    Demorgans to make it easier to understand
src/mem/tport.cc:
    Delete writebacks

--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
2006-10-17 16:47:22 -04:00
Ron Dreslinski
6e8bfa4e63 Properly chack the pkt pointer on upgrades to insure no segfaults when writebacks delete the packet.
--HG--
extra : convert_revision : 72b1c6296a16319f4d16c62bc7038365654dbc40
2006-10-17 15:07:40 -04:00
Ron Dreslinski
288b98eb69 Fix it so that the cache does not assume to gave the packet it sent out via sendTiming.
Still need to fix upgrades to use this path

src/mem/cache/base_cache.cc:
    Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
    Use copy of packet, because sendTiming may have changed the pkt
    Also, delete the copy when the time comes

--HG--
extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
2006-10-17 15:05:21 -04:00
Ron Dreslinski
685e588b45 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : c3650273684f3fbdcd2e14e95d09ee3c6de8d6b6
2006-10-17 14:05:23 -04:00
Gabe Black
b55271aee9 Corrected the "Authors" line
--HG--
extra : convert_revision : 0202e130b170dcc2f45403c58cf51ec8c2e4e094
2006-10-16 15:59:48 -04:00
Gabe Black
519d11bab3 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 898976bbd322e55bc234035456df8090c6dcf72d
2006-10-16 15:56:53 -04:00
Gabe Black
f1661baf30 Fix up microcode support.
src/arch/sparc/isa/formats/blockmem.isa:
    Several small and medium bug fixes.
src/cpu/simple/base.cc:
    Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
    Made sure the microPC and nextMicroPC are initialized properly.

--HG--
extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
2006-10-16 15:56:46 -04:00
Gabe Black
7fefa2a621 Changed how floating point register numbers are decoded to fit with the spec.
--HG--
extra : convert_revision : 155f48c84d06619c9c1c43375beb9d0a1c7495c9
2006-10-16 15:53:48 -04:00
Gabe Black
546dff6b6a Made sure the constructor for insts use ExtMachInst rather than MachInst, since otherwise the EXT_ASI field is lost.
src/arch/sparc/isa/base.isa:
src/arch/sparc/isa/formats/micro.isa:
    Switch MachInst to ExtMachInst so that the EXT_ASI field is available to the instructions.
src/arch/sparc/utility.hh:
    Made sure EXT_ASI was set to the appropriate ASI value whether or not the asi register was used.

--HG--
extra : convert_revision : cc4363dfe7da81969959cec9d5ad48528edeb8ce
2006-10-16 15:52:14 -04:00
Gabe Black
67794ace5c Added in missing portions of the stat structure copying function.
--HG--
extra : convert_revision : cfabcb07b2c0c5655a757e8c98999ec3cf791e09
2006-10-15 21:54:59 -04:00
Gabe Black
333a7c4ba2 Started implementing microcode.
--HG--
extra : convert_revision : 51df0454085e13df023efd8a0c0a12f9756c4690
2006-10-15 21:04:14 -04:00
Gabe Black
dc7d9af582 Added an execute function to the macro op so it can be instantiated.
--HG--
extra : convert_revision : 89dd46f5bbac966e6eb4f6f747419fa1d344eb87
2006-10-15 20:54:35 -04:00
Gabe Black
7009d0e523 Fix how additional template parameters are handled. Non string parameters are not processed as code.
src/arch/isa_parser.py:
    Changed the way the extra template parameters are specified. MIPS might need to be adjusted.
src/arch/sparc/isa/decoder.isa:
    Changed how Frd_N was set up.
src/arch/sparc/isa/formats/blockmem.isa:
    Fixed up handling of block memory operations
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem.isa:
src/arch/sparc/isa/formats/priv.isa:
    Fix up extra template parameters.

--HG--
extra : convert_revision : ebf850d192193521bb84ca36b577051f74338d23
2006-10-15 20:37:28 -04:00
Steve Reinhardt
9202422d6e Get rid of unused CacheBlk << output operator.
--HG--
extra : convert_revision : d5c0aadc35edf5c9495afcd3375f1f64716ef845
2006-10-14 02:09:05 -04:00
Kevin Lim
a50e83c134 Fix assertion. I haven't tested it fully (I can't reproduce Lisa's error) but I believe it should fix what she's running into (which was definitely a bug).
src/cpu/o3/fetch_impl.hh:
    Move assertion to area where it should really always be true.  Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).

--HG--
extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
2006-10-13 17:35:23 -04:00
Ron Dreslinski
1871495b8d Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : f62790e46a7e3eb88a6f8c7bfaa08526285248a3
2006-10-13 15:47:35 -04:00
Ron Dreslinski
a17afb1649 Fix for DMA's in FS caches.
Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)

Now both timing/atomic caches with MOESI in UP fail at same point.

src/dev/io_device.hh:
    DMA's should send WriteInvalidates
src/mem/bridge.cc:
    Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Fix CSHR's for flow control.
src/mem/packet.hh:
    Make a writeInvalidateResp, since the DMA expects responses to it's writes

--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
2006-10-13 15:47:05 -04:00
Ali Saidi
ca4063ac00 fix a bug in CopyStringOut. dprintk appears to work again.
--HG--
extra : convert_revision : cd0d13a85ddc7599308db8604a8f63a48679cc05
2006-10-13 14:28:46 -04:00
Lisa Hsu
339b1f8516 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

src/cpu/simple/timing.cc:
    hand merge

--HG--
extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
2006-10-12 18:56:57 -04:00
Gabe Black
92fd211a07 Changed the sign extension function from mine to the provided one. Mine relied on implementation specific behavior, namely right shifting a signed value.
--HG--
extra : convert_revision : 4f5ef44d012de87919ad681024fe2ed0213a412f
2006-10-12 17:39:15 -04:00
Gabe Black
98b00d92fd Some support for handling block loads and stores and ASIs properly.
src/arch/sparc/isa/bitfields.isa:
    Added a field to retrieve the asi from the ExtMachInst
src/arch/sparc/isa/decoder.isa:
    Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field.
src/arch/sparc/isa/formats.isa:
    add includes for the new formats.
src/arch/sparc/isa/formats/basic.isa:
    Add a template for BasicDecodeWithMnemonic which is needed by the unimp format.
src/arch/sparc/isa/formats/mem.isa:
    Change around the memory format to figure out the memory access width on its own.
src/arch/sparc/isa/operands.isa:
    Added support for the operands of block loads/stores which are offset from Frd.
src/arch/sparc/utility.hh:
    Encoded the ASI into the ExtMachInst

--HG--
extra : convert_revision : 5c6026a07e3a919e738d27f78beb0faf6b060643
2006-10-12 17:38:06 -04:00
Gabe Black
866dda9778 StaticInst support for microcode
--HG--
extra : convert_revision : c9e062637faf2166f0d36b914f3efa7f80626663
2006-10-12 17:32:02 -04:00
Gabe Black
6943c731ea The beginnings of an instruction format to deal with block loads and stores. This takes advantage of microcode.
--HG--
extra : convert_revision : ac912df76c781f40fc462f314451148c5cdfaf43
2006-10-12 17:30:25 -04:00
Gabe Black
b2d9c65db7 Some support for macro/micro instructions in SPARC.
--HG--
extra : convert_revision : 1f0687d58ab3a4823911a67d8d5c66b27cc211a5
2006-10-12 17:29:28 -04:00
Gabe Black
dd217a9d3f Support for returning unimplemented instruction in the decoder, lifted from Alpha
--HG--
extra : convert_revision : 7e26053696b23fbc0b8cd5827a5072dcf2526e2b
2006-10-12 17:27:06 -04:00
Ali Saidi
3d2764acf3 replace functional code in tport with fixPacket().
fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address.

--HG--
extra : convert_revision : 783ec438271b24ddb0ae742b4efd1ed7d6be93f3
2006-10-12 15:30:30 -04:00
Ron Dreslinski
eddbb6801f Fix CSHR retrys
--HG--
extra : convert_revision : caa7664f6c945396fa38ce62fbda018ebed4eaa6
2006-10-12 15:02:56 -04:00
Ali Saidi
4a96779350 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 0e184a0784100112db5841c587bd3dd638f8bdc0
2006-10-12 15:02:50 -04:00
Ali Saidi
0615d92d33 small bus updates for functional accesses
--HG--
extra : convert_revision : c7a6b199c74ed4b4ffab14bbffb51e72d75b7742
2006-10-12 15:02:25 -04:00
Ron Dreslinski
3aaa3456dc Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : fa5b2cfa79d87a0612b8116d407a8b2959d9095a
2006-10-12 14:31:31 -04:00
Ron Dreslinski
fe230ddb8f Remove bus and top level parameters from cache
src/mem/cache/base_cache.hh:
    Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
    Remove top level parameters from the cache

--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
2006-10-12 14:21:25 -04:00
Ali Saidi
2c9d506f46 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

src/mem/packet.hh:
    hand merge

--HG--
extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
2006-10-12 14:18:42 -04:00
Ali Saidi
3ba2ed6aef add a traceflag for functional accesses
implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such

src/base/traceflags.py:
    add a traceflag for functional accesses
src/mem/packet.cc:
    implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
    add the ability to print a packet to an ostream
    remove tabs in file
    mark const functions as such

--HG--
extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
2006-10-12 14:15:09 -04:00
Ron Dreslinski
f89b56b61a Check the response queue on functional accesses.
The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?

src/mem/cache/base_cache.cc:
src/mem/tport.cc:
    Add in functional check of retry queued packets.

--HG--
extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
2006-10-12 13:59:03 -04:00
Ron Dreslinski
6ffdc7b4d7 Another memleak in the memtester (need [] with the delete)
src/cpu/memtest/memtest.cc:
    Another memleak in the memtester

--HG--
extra : convert_revision : f7ab079e90d578fb6b9d1ff238d049fcce55b01b
2006-10-12 13:45:28 -04:00
Ron Dreslinski
dd18ffe51d Fix a memory leak in the memtester
--HG--
extra : convert_revision : 93062b0f1a3ba7a5210e2f27099f20ae8f66522b
2006-10-12 13:43:12 -04:00
Ron Dreslinski
ba4c224c39 Fix problems with unCacheable addresses in timing-coherence
src/base/traceflags.py:
src/mem/physical.cc:
    Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
    Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
    Set the size properly on unCacheable accesses

--HG--
extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
2006-10-12 13:33:21 -04:00
Gabe Black
866cfaf9dc Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
2006-10-12 10:58:45 -04:00
Ron Dreslinski
388d484269 Make default ID unique (not broadcast)
Fix a segfault associated with DefaultId

src/mem/bus.cc:
    Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
    Make the Default ID more unique (it overlapped with Broadcast ID)

--HG--
extra : convert_revision : 9182805c5cf4d9fe004e6c5be8547a8f41ed7bfe
2006-10-11 20:54:06 -04:00
Ron Dreslinski
14c8e8b227 Forgot to mark myself as on the retry list
--HG--
extra : convert_revision : c20170320a284a7bf143a929e4d3aa1475a8bfe0
2006-10-11 19:47:11 -04:00
Ron Dreslinski
3c7e0ec752 Fix bus in FS mode.
src/mem/bus.cc:
    Add debugging statement
src/mem/bus.hh:
    Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
    Rework timing port to retry properly

--HG--
extra : convert_revision : fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
2006-10-11 19:25:48 -04:00
Lisa Hsu
ba795552f5 System not global object, need to preface it with objects.
--HG--
extra : convert_revision : 5e105d7082a8c103fb5d5383c3093734bfd590f5
2006-10-11 18:54:31 -04:00
Lisa Hsu
8acecfef9b since memoryMode was put into the System (from SimObject), things got broken - this fixes it so that changeToTiming/changeToAtomic works.
src/python/m5/SimObject.py:
    now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode.
src/sim/main.cc:
    need this conversion now.
src/sim/sim_object.hh:
    put the enum back into SimObject.
src/sim/system.hh:
    memoryMode is now a part of SimObject, need the ::'s

--HG--
extra : convert_revision : 0ade06957fa57b497798e1f50c237ca1badc821d
2006-10-11 18:53:50 -04:00
Lisa Hsu
024b33a1ef some drain changes in timing (kevin's) and some memory mode assertion changes so that when you come out of resume, you only assert if you're really wrong.
src/cpu/simple/atomic.cc:
    memory mode assertion change so that it only goes off if it's supposed to.
src/cpu/simple/timing.cc:
    some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to.

--HG--
extra : convert_revision : 007d8610f097e08f01367b905ada49f93cf37ca3
2006-10-11 18:44:48 -04:00
Ron Dreslinski
567afbf6ce More cache fixes. Atomic coherence now works as well.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
    Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Debug output.
    Clean up memleak in atomic mode.
    Set hitLatency.
    Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
    Add command strings for new commands
src/python/m5/objects/MemTest.py:
    Add param to test atomic memory.

--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
2006-10-11 18:28:33 -04:00
Ron Dreslinski
03c42ea590 Update for Atomic Coherece with Gabes bus
--HG--
extra : convert_revision : 6a23052056d1c61cba0a4c77f1030cee419c6fa3
2006-10-11 01:59:38 -04:00
Ron Dreslinski
4e35c5656f Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 70187b8f04d0f8424512f64bdade05bf1aca85a3
2006-10-11 01:02:18 -04:00
Ron Dreslinski
c2012601e9 Use bus response time paramteres
Fix bug with deadlocking

src/mem/cache/base_cache.cc:
    Make sure to not wait anymore

--HG--
extra : convert_revision : 5f7b44a1c475820b9862275a0d6113ec2991735d
2006-10-11 01:01:40 -04:00
Gabe Black
7767f5af73 Don't call recvRetry if the bus is busy anyway. This takes care of a corner case as well when dealing with grants that aren't used.
--HG--
extra : convert_revision : 38f7ef1b41477fb2a2438387ef3a81cccd3e7a8a
2006-10-11 00:54:47 -04:00
Ron Dreslinski
07dad71f6f Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : d2d19b27533f35c6570ee84c6c83b2919f27b97f
2006-10-11 00:31:40 -04:00
Gabe Black
a139e4394d Make the bus work if the other sides recvRetry doesn't call sendTiming for some reason.
--HG--
extra : convert_revision : e722ddb0354a5c021dc7c44a3e2f0a64e962442b
2006-10-11 00:26:21 -04:00
Ron Dreslinski
04f71f1226 When turning asserts into if's don't forget to invert.
src/mem/cache/base_cache.cc:
    When turning asserts into if's don't forget to invert.
    Must be too sleepy.

--HG--
extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
2006-10-11 00:19:31 -04:00
Ron Dreslinski
23bbd14426 Writebacks can be pulled out from under the BusRequest when snoops of uprgades to owned blocks hit in the WB buffer
--HG--
extra : convert_revision : f0502836a79ce303150daa7e571badb0bce3a97a
2006-10-11 00:13:53 -04:00
Ron Dreslinski
c9102b08fa Only issue responses if we aren;t already blocked
--HG--
extra : convert_revision : 511c0bcd44b93d5499eefa8399f36ef8b6607311
2006-10-10 23:53:10 -04:00
Ron Dreslinski
ca694ca7b1 Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/bus.cc:
    SCCS merged

--HG--
extra : convert_revision : 18608114350c466a56ab499ae523b01fcb2f6ef2
2006-10-10 23:37:14 -04:00
Gabe Black
8353b1e21f Make the bus is occupied for none broadcast packets as well.
--HG--
extra : convert_revision : aef3c625172e92be8f29c4c57077fefee43046bb
2006-10-10 23:28:33 -04:00
Ron Dreslinski
477a3b0b61 Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/bus.cc:
    SCCS merged

--HG--
extra : convert_revision : eaae105025635c37af06cf72bb061ce82def9dc9
2006-10-10 22:52:52 -04:00
Ron Dreslinski
1de8eae43a Debugging info
src/base/traceflags.py:
    Add new flags for cacheport
src/mem/bus.cc:
    Add debugging info
src/mem/cache/base_cache.cc:
    Add debuggin info

--HG--
extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
2006-10-10 22:50:36 -04:00
Gabe Black
59dd317cb5 Put in an accounting mechanism and an assert to make sure something doesn't try to send another packet while it's still waiting for the bus.
--HG--
extra : convert_revision : 4a2b83111e49f71ca27e05c98b55bc3bac8d9f53
2006-10-10 22:10:08 -04:00
Gabe Black
404b2a951d Fixed a corner case and simplified the logic in Packet::intersect.
--HG--
extra : convert_revision : b57c31ca7c220e701d34e02bb07ce392370e4428
2006-10-10 17:49:31 -04:00
Ron Dreslinski
27c59dc370 Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 7b7a1b03ffed36bce49595962ea57c08d1d1a4ad
2006-10-10 17:32:24 -04:00
Ron Dreslinski
aff3d92c00 Some more code cleanup
src/mem/cache/base_cache.cc:
    Add sanity checks
src/mem/cache/base_cache.hh:
    Fix for retry mechanism

--HG--
extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
2006-10-10 17:25:50 -04:00
Gabe Black
549412b333 Changed the bus to use a bool to keep track of retries rather than a pointer
src/mem/tport.cc:
    minor formatting tweak

--HG--
extra : convert_revision : 7391d142815c5876fcc0f991bd053e6a1781c101
2006-10-10 17:24:03 -04:00
Gabe Black
5f9aca531d Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : aa59d3169d84bcd13b8c97f22b52aeef43dc33c3
2006-10-10 17:18:09 -04:00
Ron Dreslinski
995146ead7 Fix some more mem leaks, still some left
Update retry mechanism

src/mem/cache/base_cache.cc:
    Rework the retry mechanism
src/mem/cache/base_cache.hh:
    Rework the retry mechanism
    Try to fix memory bug
src/mem/cache/cache_impl.hh:
    Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
    Fix mem leak on writebacks

--HG--
extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
2006-10-10 17:10:56 -04:00
Gabe Black
012556ecf9 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 4036e8447fb3038d93285c6582900210d7d88d67
2006-10-10 15:56:18 -04:00
Ron Dreslinski
9e008d73d5 Fix cshr Retry's
Fix Upgrades being blocked by slave

--HG--
extra : convert_revision : cca98a38e32233145163577500f1362cd807ab15
2006-10-10 15:53:25 -04:00
Gabe Black
3a9eb598c3 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 6027c395af044858465eafd3ea78bcfe4c923bcc
2006-10-10 15:04:55 -04:00
Ron Dreslinski
fe8b912c03 Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 87f83c4edf6ea51adc767d98265d1e74c0fbb46f
2006-10-10 02:36:04 -04:00
Ron Dreslinski
3fa5e4b6b8 Yet another fix to the HasData command attribute.
--HG--
extra : convert_revision : dcf0d7eafa5168591c2b374b452821ca34dde7f9
2006-10-10 02:33:30 -04:00
Ron Dreslinski
b40798070b Actually set the HasData attribute on Read Responses
--HG--
extra : convert_revision : 129dadbf8091ab00fb7f16eace59df265fc3718c
2006-10-10 02:21:03 -04:00