Gabe Black
647edea970
ARM: Fix the constant describing the number of floating point registers.
2010-06-02 12:58:04 -05:00
Gabe Black
2f3102f1ef
ARM: Add templates for VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
739f23c64c
ARM: Add base classes for VFP load/store multiple.
2010-06-02 12:58:04 -05:00
Gabe Black
cb631d87c3
ARM: Add floating point load/store microops.
2010-06-02 12:58:04 -05:00
Gabe Black
3a11412c99
ARM: Add an fp version of one of the microop indexed registers.
2010-06-02 12:58:04 -05:00
Gabe Black
d5aee75efe
ARM: Move the mmap region to where Linux actually has it.
2010-06-02 12:58:04 -05:00
Gabe Black
a8eb9d521c
ARM: Eliminate the unused rhi and rlo operands.
2010-06-02 12:58:03 -05:00
Gabe Black
b02c7f1bcd
ARM: Move the macro mem constructor out of the isa desc.
...
This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
2010-06-02 12:58:03 -05:00
Gabe Black
7b62e9ad71
ARM: Make macroops panic if executed directly.
...
The macroop should never be executed, only it's microops will.
2010-06-02 12:58:03 -05:00
Ali Saidi
8fadf2691d
ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs.
2010-06-02 12:58:03 -05:00
Gabe Black
f18040a205
ARM: Split out the "basic" templates and format.
...
--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
2010-06-02 12:58:03 -05:00
Gabe Black
c175f1b993
ARM: Remove unnecessary cruft from includes.isa.
2010-06-02 12:58:03 -05:00
Gabe Black
e29ec7d2ed
ARM: Move the inst2string function out of the isa_desc.
...
Delete the now empty formats/util.isa.
2010-06-02 12:58:03 -05:00
Gabe Black
ae135228fc
ARM: Get rid of the unused ArmGenericCodeSubs.
2010-06-02 12:58:03 -05:00
Gabe Black
8c012e9571
ARM: Make the predecoder print out the ExtMachInst it gathered when traced.
2010-06-02 12:58:03 -05:00
Gabe Black
458bd025d4
ARM: Remove special naming for the new version of multiply.
2010-06-02 12:58:03 -05:00
Gabe Black
2196f75a25
ARM: Hook the new multiply instructions into all the decoders.
2010-06-02 12:58:03 -05:00
Gabe Black
33da368e99
ARM: Implement all integer multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
50229be27f
ARM: Add templates for multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
3430b34cff
ARM: Add base classes for multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
c7d2f43641
ARM: Decode plain binary immediate thumb data processing instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
dcf218155d
ARM: Define a new "movt" data processing instruction.
2010-06-02 12:58:03 -05:00
Gabe Black
b615ed1470
ARM: Hook the new branch instructions into the 32 bit thumb decoder.
2010-06-02 12:58:03 -05:00
Gabe Black
274badd201
ARM: Hook the new branch instructions into the 16 bit thumb decoder.
2010-06-02 12:58:03 -05:00
Gabe Black
b6b2f8891a
ARM: Eliminate the old style branch instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
d082705b01
ARM: Hook the new branch instructions into the ARM decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
9869343636
ARM: Implement branch instructions external to the decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
a6c1c8debb
ARM: Add new templates for branch instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
ef3972eaae
ARM: Implement new base classes for branches.
2010-06-02 12:58:02 -05:00
Gabe Black
769f3406fe
ARM: Replace the interworking branch base class with a special operand.
2010-06-02 12:58:02 -05:00
Gabe Black
b6e7029dd5
ARM: Fix PC operand handling.
2010-06-02 12:58:02 -05:00
Gabe Black
7eb3ea2798
ARM: Remove the special naming from the new version of data processing instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
4f08b52af2
ARM: Get rid of unnecessary flag calculating functions.
2010-06-02 12:58:02 -05:00
Gabe Black
bf903ec9a1
ARM: Get rid of the unused Jump format.
2010-06-02 12:58:02 -05:00
Gabe Black
36ca0658a4
ARM: Get rid of obsoleted predicated inst formats, etc.
2010-06-02 12:58:02 -05:00
Gabe Black
7939b48265
ARM: Implement disassembly for the new data processing classes.
2010-06-02 12:58:02 -05:00
Gabe Black
b66e3aec43
ARM: Hook the external data processing instructions into the Thumb decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
beb759912b
ARM: Move the modified_imm function from all ARM instructions to just data processing ones.
2010-06-02 12:58:02 -05:00
Gabe Black
8136cb3605
ARM: Hook the new external data processing instructions to the ARM decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
bf45d44cbe
ARM: Implement data processing instructions external to the decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
c02f9cdddf
ARM: Add new base classes for data processing instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
1e7b317a98
ARM: Hook up 32 bit thumb load/store multiple.
2010-06-02 12:58:02 -05:00
Gabe Black
64d6b6ebfd
ARM: Hook up 16 bit thumb load/store multiple.
2010-06-02 12:58:02 -05:00
Gabe Black
51bde086d5
ARM: Reimplement load/store multiple external to the decoder.
...
--HG--
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
2010-06-02 12:58:02 -05:00
Gabe Black
93a3714816
ARM: Move the templates for predicated instructions into a separate file.
...
This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.
--HG--
rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa
2010-06-02 12:58:01 -05:00
Gabe Black
04300e33d4
ARM: Remove the special naming for the new memory instructions.
...
These are the only memory instructions now.
2010-06-02 12:58:01 -05:00
Gabe Black
deb6e8f805
ARM: Eliminate the old memory formats which are no longer used.
2010-06-02 12:58:01 -05:00
Gabe Black
1905024766
ARM: Eliminate decoding for the very deprecated FPA instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
55465844dc
ARM: Make the addressing mode 3 loads/stores use the externally defined instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
36b6ca2ce3
ARM: Pull double memory instructions out of the decoder.
2010-06-02 12:58:01 -05:00
Gabe Black
79b288f7b5
ARM: Force the condition code for 16 bit thumb instructions to be unconditional.
...
Before, because 16 bit thumb instructions didn't set the upper 16 bits of the
ExtMachInst, that field would be interpretted as "equals".
2010-06-02 12:58:01 -05:00
Gabe Black
a86491fbf2
ARM: Decode 16 bit thumb PC relative memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
dc8af1b211
ARM: Decode 16 bit thumb immediate addressed memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
4bbd73649d
ARM: Decode 16 bit thumb register addressed memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
462cf6f49b
ARM: Make single stores decode to the new external store instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
3b0f3b1ee2
ARM: Add a .w to the disassembly of 32 bit thumb instructions.
...
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.
2010-06-02 12:58:01 -05:00
Gabe Black
fde3c8f41d
ARM: Make 32 bit thumb use the new, external load instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
3b93015304
ARM: Define the store instructions from outside the decoder.
...
--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
2010-06-02 12:58:01 -05:00
Gabe Black
81fdced83f
ARM: Define the load instructions from outside the decoder.
2010-06-02 12:58:01 -05:00
Gabe Black
321d3a6e8c
ARM: Implement a new set of base classes for non macro memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
8933857af7
ARM: Create a "decoder" directory for the files implementing the decoder.
...
--HG--
rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa
rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa
rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa
2010-06-02 12:58:01 -05:00
Gabe Black
4ebd44dc4f
ARM: Flesh out the 32 bit thumb store single instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
386424ccb5
ARM: Implement the 32 bit thumb load word instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
292b8a3c91
ARM: Add an operand for accessing the current PC.
2010-06-02 12:58:00 -05:00
Gabe Black
003346077f
ARM: Flesh out 32 bit thumb load word decoding.
2010-06-02 12:58:00 -05:00
Gabe Black
0d4c4cacab
ARM: Implement some 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
bd8812cf99
ARM: Replace the "never" condition with the "unconditional" condition.
2010-06-02 12:58:00 -05:00
Gabe Black
af91d27271
ARM: Add a base class for 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
bfe1a194dd
ARM: Add a function to decode 32 bit thumb immediate values.
2010-06-02 12:58:00 -05:00
Gabe Black
0116655674
ARM: Expand the decoding for 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
cef2e8ecee
ARM: Stub out the 32 bit Thumb portion of the decoder.
2010-06-02 12:58:00 -05:00
Gabe Black
659f8d021f
ARM: Add bitfields for 32 bit thumb.
2010-06-02 12:58:00 -05:00
Gabe Black
bc6ae010c9
ARM: Decode VFP instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
7b8525287d
ARM: Stub out the 16 bit thumb decoder.
2010-06-02 12:58:00 -05:00
Gabe Black
aaa619ea23
ARM: Add thumb bitfields to the ExtMachInst and the isa definition.
2010-06-02 12:58:00 -05:00
Gabe Black
a1838f2c79
ARM: Make the decoder handle thumb instructions separately.
...
--HG--
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa
2010-06-02 12:58:00 -05:00
Gabe Black
0dffd8ce79
ARM: Add a thumb bit bitfield.
2010-06-02 12:58:00 -05:00
Gabe Black
96be7e16c1
ARM: Make the predecoder handle Thumb instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
f49cdb4f5d
ARM: Make sure ExtMachInst is used consistently instead of regular MachInst.
2010-06-02 12:58:00 -05:00
Gabe Black
330d9d4dbc
ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst.
2010-06-02 12:58:00 -05:00
Gabe Black
a59d219989
ARM: Add a bit to the ExtMachInst to select thumb mode.
2010-06-02 12:58:00 -05:00
Gabe Black
4ddeceba96
ARM: Allow ARM processes to start in Thumb mode.
2010-06-02 12:58:00 -05:00
Gabe Black
3951afd2fa
ARM: Detect thumb mode elf images.
2010-06-02 12:58:00 -05:00
Gabe Black
ebb273bb7b
ARM: Add a new base class for instructions that can do an interworking branch.
2010-06-02 12:57:59 -05:00
Gabe Black
9ef82c0bc4
ARM: Track the current ISA mode using the PC.
2010-06-02 12:57:59 -05:00
Gabe Black
1c0d9806e5
ARM: Fix custom writer/reader code for non indexed operands.
2010-06-02 12:57:59 -05:00
Gabe Black
4b87bc887a
ARM: Remove IsControl from operands that don't imply control transfers.
...
Also remove IsInteger from CondCodes.
2010-06-02 12:57:59 -05:00
Ali Saidi
322f345b51
ARM: Adjust some copyrights
2010-06-02 12:57:59 -05:00
Nathan Binkert
c1aabe8172
style: clean up ruby's Set class
...
Further cleanup should probably be done to make this class be non-Ruby
specific and put it in src/base.
There are probably several cases where this class is used, std::bitset
could be used instead.
2010-06-01 11:38:56 -07:00
Nathan Binkert
bb589d463b
x86: put back code that I accidentally deleted
2010-05-25 20:15:44 -07:00
Nathan Binkert
13d64906c2
copyright: Change HP copyright on x86 code to be more friendly
2010-05-23 22:44:15 -07:00
Gabe Black
c5c559b6ab
SPARC: Implement the version of movcc that uses the fp condition codes.
2010-05-14 14:22:51 -07:00
Ali Saidi
72071690e7
Automated merge with ssh://m5sim.org//repo/m5
2010-05-13 23:48:06 -04:00
Maximilien Breughe
fc746c2268
BPRED: Fixed the treshold-bug in the tournament predictor.
...
Suppose the saturating counters of a branch predictor contain n bits. When the
counter is between 0 and (2^(n-1) - 1), boundaries included, the branch is
predicted as not taken. When the counter is between 2^(n-1) and (2^n - 1),
boundaries included, the branch is predicted as taken.
2010-05-13 23:45:57 -04:00
Gabe Black
c4497dbf03
X86: Make the cvti2f microop sign extend its integer source correctly.
...
The code was using the wrong bit as the sign bit. Other similar bits of code
seem to be correct.
2010-05-12 00:51:35 -07:00
Gabe Black
cc76842f83
X86: Actual change that fixes div. How did that happen?
2010-05-12 00:49:12 -07:00
Nathan Binkert
c4057a13f1
macos: MacOS has deprecated getdirentries, so just disable the code.
...
Hopefully it isn't used much
2010-05-06 08:42:21 -07:00
Nathan Binkert
f07ee128cc
compile: don't #include unnecessary stuff
...
Time from base/time.hh has a name clash with Time from Ruby's
TypeDefines.hh. Eventually Ruby's Time should go away, so instead of
fixing this properly just try to avoid the clash.
2010-05-06 08:42:18 -07:00
Gabe Black
2ee7a89209
X86: Update the base aux vector X86 processes install.
2010-05-03 00:44:08 -07:00
Gabe Black
7524fdda6a
X86: Sometimes CPUID depends on ecx, so pass that in.
2010-05-02 00:40:17 -07:00
Gabe Black
51a3d65e25
X86: Finally fix a division corner case.
...
When doing an unsigned 64 bit division with a divisor that has its most
significant bit set, the division code would spill a bit off of the end of a
uint64_t trying to shift the dividend into position. This change adds code
that handles that case specially by purposefully letting it spill and then
going ahead assuming there was a 65th one bit.
2010-05-02 00:39:29 -07:00
Nathan Binkert
82fb350f9a
stats: make simTicks and simFreq accessible from stats.hh
2010-04-18 13:23:25 -07:00
Nathan Binkert
50bf3895b0
callback: Make helper functions that create callback objects for you
...
clean up callback stuff a little bit while we're at it.
2010-04-18 13:23:25 -07:00
Nathan Binkert
12fc22571c
event: Allow EventWrapper to take an object reference
2010-04-18 13:23:24 -07:00
Nathan Binkert
4225a68a95
scons: don't maintain files in sorted order
...
This causes builds to happen in sorted order rather than in
declaration order. This gets annoying when you make a global change
and then you notice that the files that are being compiled are jumping
around the directory hierarchy.
2010-04-15 16:25:14 -07:00
Nathan Binkert
e99828b06a
tick: rename Clock namespace to SimClock
2010-04-15 16:24:12 -07:00
Nathan Binkert
f7e6f19ada
eventq: move EventQueue constructor to cc file
...
Also make copy constructor and assignment operator private.
2010-04-15 16:24:10 -07:00
Korey Sewell
b49511ae48
inorder: timing for inst forwarding
...
when insts execute, they mark the time they finish to be used for subsequent isnts
they may need forwarding of data. However, the regdepmap was using the wrong
value to index into the destination operands of the instruction to be forwarded.
Thus, in some cases, we are checking to see if the 3rd destination register
for an instruction is executed at a certain time, when there is only 1 dest. register
valid. Thus, we get a bad, uninitialized time value that will stall forwarding
causing performance loss but still the correct execution.
2010-04-10 23:31:36 -04:00
Nathan Binkert
d71f9712b3
eventq: allow an implicit cast from an EventManager to an EventQueue *
2010-04-02 15:28:22 -07:00
Nathan Binkert
f32674d9bc
eventq: Clean up some flags
...
- Make the initialized flag always available, not just in debug mode.
- Make the Initialized flag actually use several bits so it is very
unlikely that something that's uninitialized accidentally looks
initialized.
- Add an initialized() function that tells you if the current event is
indeed initialized.
- Clear the flags on delete so it can't be accidentally thought of as
initialized.
- Fix getFlags assert statement. "How did this ever work?"
2010-04-02 15:28:22 -07:00
Nathan Binkert
2ee3edba8e
eventq: Make priorities just an integer instead of an enum.
...
Symbolic names should still be used, but this makes it easier to do
things like:
Event::Priority MyObject_Pri = Event::Default_Pri + 1
Remember that higher numbers are lower priority (should we fix this?)
2010-04-02 15:28:21 -07:00
Nathan Binkert
01dffaa32f
refcnt: no default copy contructor or copy operator
...
We shouldn't allow these because the default versions will copy
the reference count which is definitely not what we want.
2010-04-02 11:20:32 -07:00
Nathan Binkert
141f61d83a
ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base
2010-04-02 11:20:32 -07:00
Nathan Binkert
f1c3f3044b
ruby: get "using namespace" out of headers
...
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
2010-04-02 11:20:32 -07:00
Nathan Binkert
be10204729
style: another ruby style pass
2010-03-31 16:56:45 -07:00
Nathan Binkert
60ae1d2b10
style: cleanup the Ruby Tester
2010-03-29 20:39:02 -04:00
Korey Sewell
1c98bc5a56
m5: merge inorder updates
2010-03-27 02:23:00 -04:00
Korey Sewell
ac316d45e8
inorder: write-hints bug fix
...
make sure to only read 1 src reg. for write-hint and any other similar
'store' instruction. Reading the source reg when its not necessary
can cause the simulator to read from uninitialized values
2010-03-27 01:40:05 -04:00
Timothy M. Jones
6b293c73fd
CPU: Added comments to address translation classes.
2010-03-25 12:43:52 +00:00
Nathan Binkert
a2652a048a
ruby: continue style pass
2010-03-23 22:49:43 -07:00
Steve Reinhardt
f066bfc2f5
cpu: get rid of uncached access "events"
...
These recordEvent() calls could cause crashes since they
access the req pointer after it's potentially been
deleted during a failed translation call. (Similar
problem to the traceData bug fixed in the previous cset.)
Moving them above the translation call (as was done
recentlyi in cset 8b2b8e5e7d35) avoids the crash
but doesn't work, since at that point we don't know if
the access is uncached or not.
It's not clear why these calls are there, and no one
seems to use them, so we'll just delete them. If they
are needed, they should be moved to somewhere that's
guaranteed to be after the translation completes but
before the request is possibly deleted, e.g., in
finishTranslation().
2010-03-23 08:50:59 -07:00
Steve Reinhardt
4d77ea7a57
cpu: fix exec tracing memory corruption bug
...
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.
It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical. Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.
This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition. It also moves those calls above
the translation calls to eliminate the crashes.
2010-03-23 08:50:57 -07:00
Nathan Binkert
5ab13e2deb
ruby: style pass
2010-03-22 18:43:53 -07:00
Korey Sewell
2620e08722
inorder: import name for addtl. bpred stats
2010-03-22 17:19:48 -04:00
Maximilien Breughe
0170e851de
inorder: fix squash bug in branch predictor
2010-03-22 16:59:12 -04:00
Korey Sewell
4ac245737d
inorder: fix address list bug
2010-03-22 15:38:28 -04:00
Brad Beckmann
66632539b6
ruby: improved isReadWrite fix me comment
2010-03-22 11:19:17 -07:00
Brad Beckmann
b55e69ccac
ruby: Removed the unnecessary MachineType message fields
2010-03-21 21:22:22 -07:00
Brad Beckmann
898f1fc4a4
ruby: Reorganized Ruby topology and protocol files
...
--HG--
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/protocols/MESI_CMP_directory.py
rename : configs/ruby/MI_example.py => configs/ruby/protocols/MI_example.py
rename : configs/ruby/MOESI_CMP_directory.py => configs/ruby/protocols/MOESI_CMP_directory.py
rename : configs/ruby/MOESI_CMP_token.py => configs/ruby/protocols/MOESI_CMP_token.py
rename : configs/ruby/MOESI_hammer.py => configs/ruby/protocols/MOESI_hammer.py
rename : configs/ruby/networks/MeshDirCorners.py => src/mem/ruby/network/topologies/MeshDirCorners.py
2010-03-21 21:22:22 -07:00
Brad Beckmann
f3cdc0d5a3
ruby: Disable adaptive routing by for faster simulation perf.
2010-03-21 21:22:21 -07:00
Brad Beckmann
f9408f984f
ruby: Changed the default set size to 1
...
Previously, the set size was set to 4. This was mostly do to the fact that a
crazy graduate student use to create networks with 256 l2 cache banks. Now it
is far more likely that users will create systems with less than 64 of any
particular controller type. Therefore Ruby should be optimized for a set size
of 1.
2010-03-21 21:22:21 -07:00
Brad Beckmann
61f1d9a3d7
ruby: Reordered protocol buffers
...
Reordered vnet priorities to agree with PerfectSwitch for protocols MI_example,
MOESI_CMP_token, and MOESI_hammer
2010-03-21 21:22:21 -07:00
Brad Beckmann
4f044605e8
ruby: Adds configurable bit selection for numa mapping
2010-03-21 21:22:21 -07:00
Brad Beckmann
8b15ed7ebf
ruby: Added flag to disable mem_vec allocation
...
The RubySystem flag no_mem_vec will disable Ruby from allocating it's memory
data array.
2010-03-21 21:22:21 -07:00
Brad Beckmann
92cfd1cac7
ruby: Ruby support for sparse memory
...
The patch includes direct support for the MI example protocol.
2010-03-21 21:22:21 -07:00
Brad Beckmann
b5e4c3cbf2
ruby: Finally removed bash code cira. 2001ish!
2010-03-21 21:22:21 -07:00
Brad Beckmann
6d22db4eaa
ruby: Ruby support for LLSC
2010-03-21 21:22:21 -07:00
Brad Beckmann
f53287f9ad
ruby: Minor dma latency initialization fix
2010-03-21 21:22:21 -07:00
Tushar Krishna
7c20d5511a
ruby: Fix multiple wakeups in Ruby Eventqueue
...
Fix bug in Ruby Event queue to avoid multiple wakeups of same consumer in
same cycle
2010-03-21 21:22:21 -07:00
Brad Beckmann
103f5a2c94
ruby: Removed the obsolete file specified network files
2010-03-21 21:22:21 -07:00
Brad Beckmann
d464087101
ruby: Added copyright to many Ruby *.py files
2010-03-21 21:22:20 -07:00
Brad Beckmann
378fbce911
ruby: Fixed small data msg bug in MOESI_hammer-dir
2010-03-21 21:22:20 -07:00
Brad Beckmann
4ee3b0da45
TimingSimpleCPU: Fixed uncacacheable request read bug
...
Previously the recording of an uncached read occurred after the request was
possibly deleted within the translateTiming function.
2010-03-21 21:22:20 -07:00
Brad Beckmann
0368ef915a
ruby: Removed the no longer used rubymem files
2010-03-21 21:22:20 -07:00
Brad Beckmann
c48a735336
ruby: Fix MOESI_hammer cache profiler calls for L2 misses
2010-03-21 21:22:20 -07:00
Brad Beckmann
391b4e64e6
ruby: Removed deprecated stats from the main profiler
2010-03-21 21:22:20 -07:00
Nathan Binkert
86207a69e4
orion: Make declarations match definition
2010-03-16 08:15:16 -07:00
Nathan Binkert
edb59ed263
ruby: Fix copyrights on files
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Mostly files missed during import or screwed up during import
2010-03-14 20:58:45 -07:00
Nathan Binkert
0bbf63f17a
slicc: Change the code generation so that the generated code is easier to read
2010-03-12 18:42:56 -08:00
Nathan Binkert
c8f296bca0
packet: add a method to set the size
2010-03-12 17:31:08 -08:00
Nathan Binkert
671faf3316
eventq: rearrange a little bit so I can add some stuff
2010-03-12 17:31:04 -08:00
Nathan Binkert
402f42ebfa
eventq: remove some unused includes
2010-03-12 17:31:02 -08:00
Nathan Binkert
fce7c820f4
bugfix: since pow() causes a bug don't use it
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It's a power of two anyway, so why use it in the first place.
2010-03-12 15:11:09 -08:00
Nathan Binkert
140785d24c
ruby: get rid of std-includes.hh
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Do not use "using namespace std;" in headers
Include header files as needed
2010-03-10 18:33:11 -08:00
Nathan Binkert
1badec39a9
ruby: remove calc_host.diff since we don't use it
2010-03-10 16:22:27 -08:00
Nathan Binkert
226eaf9ddf
ruby: get rid of the ioutil stuff since it isn't used anymore
2010-03-10 16:22:26 -08:00
Nathan Binkert
cf86532857
slicc: have a central mechanism for creating a code_formatter.
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This makes it easier to add global variables like protocol
2010-03-10 16:22:26 -08:00
Nathan Binkert
1068ca85d0
scons: import ply to work around scons sys.path weirdness
2010-03-10 15:39:34 -08:00
Nathan Binkert
25aac791de
SmartDict: Make SmartDict an attrdict
2010-02-28 19:28:09 -08:00
Nathan Binkert
ebdd004eb2
uart: use integer versions of time instead of messing around with floats
2010-02-28 19:28:09 -08:00
Nathan Binkert
f0b4259e98
cpu_models: get rid of cpu_models.py and move the stuff into SCons
2010-02-26 18:14:48 -08:00
Nathan Binkert
ac106767c8
isa_parser: Make SCons import the isa_parser
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this is instead of forking a new interpreter
2010-02-26 18:14:48 -08:00
Nathan Binkert
629e8df196
isa_parser: move the operand map stuff into the ISAParser class.
2010-02-26 18:14:48 -08:00
Nathan Binkert
4db57edade
isa_parser: move more support functions into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
5ad139375e
isa_parser: move more stuff into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
4ef6e129d6
isa_parser: move the formatMap and exportContext into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
4e105f6fe1
isa_parser: Make stack objects class members instead of globals
2010-02-26 18:14:48 -08:00
Nathan Binkert
b4178b1ae7
isa_parser: add a debug variable that changes how errors are reported.
...
This allows us to get tracebacks in certain cases where they're more
useful than our error message.
2010-02-26 18:14:48 -08:00
Nathan Binkert
40a05f04fb
isa_parser: Use an exception to flag error
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This allows the error to propagate more easily
2010-02-26 18:14:48 -08:00
Nathan Binkert
f82a92925c
isa_parser: Move more stuff into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
f7a627338c
isa_parser: move code around to prepare for putting more stuff in the class
2010-02-26 18:14:48 -08:00
Nathan Binkert
eb4ce01056
isa_parser: simple fixes, formatting and style
2010-02-26 18:14:48 -08:00
Nathan Binkert
a9f6c8edc3
events: Give EventWrapped a default name and description
2010-02-26 18:09:41 -08:00
Lisa Hsu
7f3cd9a9fd
cache stats: account for writebacks and/or device occupancy in the cache.
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Plus, a minor bugfix that neglects to update blk->contextSrc in certain cases on a cache insert.
2010-02-24 13:46:55 -08:00
Lisa Hsu
1d3228481f
cache: Make caches sharing aware and add occupancy stats.
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On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).
2010-02-23 09:34:22 -08:00
Lisa Hsu
be4cf50c5a
stats: this makes some fixes to AverageStat and AverageVector.
...
Also, make Formulas work on AverageVector. First, Stat::Average (and thus
Stats::AverageVector) was broken when coming out of a checkpoint and on resets,
this fixes that. Formulas also didn't work with AverageVector, but added
support for that.
2010-02-23 09:33:18 -08:00
Lisa Hsu
2ad386f104
cache: pull CacheSet out of LRU so that other tags can use associative sets.
2010-02-23 09:33:09 -08:00
Timothy M. Jones
a5feaa6a69
BaseDynInst: Preserve the faults returned from read and write.
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When implementing timing address translations instead of atomic, I
forgot to preserve the faults that are returned from the read and
write calls. This patch reinstates them.
2010-02-20 20:11:58 +00:00
Timothy M. Jones
29e8bcead5
O3PCU: Split loads and stores that cross cache line boundaries.
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When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.
This modifies the LSQSenderState class to record both packets in a split
load or store.
Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
2010-02-12 19:53:20 +00:00
Timothy M. Jones
7fe9f92cfc
BaseDynInst: Make the TLB translation timing instead of atomic.
...
This initiates a timing translation and passes the read or write on to the
processor before waiting for it to finish. Once the translation is finished,
the instruction's state is updated via the 'finish' function. A new
DataTranslation class is created to handle this.
The idea is taken from the implementation of timing translations in
TimingSimpleCPU by Gabe Black. This patch also separates out the timing
translations from this CPU and uses the new DataTranslation class.
2010-02-12 19:53:19 +00:00
Timothy M. Jones
dd60902152
Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.
2010-02-12 19:53:19 +00:00
Brad Beckmann
64999b4343
ruby: fixed data block assignment fix
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Fixed data block assignment to not delete if not internally allocated.
2010-02-10 16:40:54 -08:00
Brad Beckmann
714865e4a4
ruby: Initialize sender in MI_example-dir
2010-02-10 16:40:54 -08:00
Brad Beckmann
a407675106
ruby: Fixed slicc to initialize the m_is_blocking flag
2010-02-10 16:40:54 -08:00
Brad Beckmann
1d4c3ecdc3
ruby: Added FS support to the simple mesh topology
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Added full-system support to the simple mesh toplogy by allowing dma contrllers
to be attached to router zero in the network.
2010-02-01 14:27:16 -08:00
Brad Beckmann
db2ecbb6b6
ruby: Set default protocol back to MI_example
2010-02-01 11:07:38 -08:00
Korey Sewell
c7f6e2661c
inorder: double delete inst bug
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Make sure that instructions are dereferenced/deleted twice by marking they are
on the remove list
2010-01-31 18:30:59 -05:00
Korey Sewell
9357e353fc
inorder: inst count mgmt
2010-01-31 18:30:48 -05:00
Korey Sewell
be6724f7e7
inorder: implement split stores
2010-01-31 18:30:43 -05:00
Korey Sewell
6939482c49
inorder: implement split loads
2010-01-31 18:30:35 -05:00
Korey Sewell
ea8909925f
inorder: add activity stats
2010-01-31 18:30:24 -05:00
Korey Sewell
f3bc2df663
inorder: object cleanup in destructors
2010-01-31 18:30:08 -05:00
Korey Sewell
1a89e8f4cb
inorder: user per-thread dummy insts/reqs
2010-01-31 18:29:59 -05:00
Korey Sewell
002f1b8b7e
inorder: add execution unit stats
2010-01-31 18:29:49 -05:00
Korey Sewell
82c5a754e6
inorder: recvRetry bug fix
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- on certain retry requests you can get an assertion failure
- fix by allowing the request to literally "Retry" itself
if it wasnt successful before, and then block any requests
through cache port while waiting for the cache to be
made available for access
2010-01-31 18:29:18 -05:00
Korey Sewell
349d86c0e4
inorder-stats: add prereq to basic stat
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only show requests processed when the resource is actually in use
2010-01-31 18:29:06 -05:00
Korey Sewell
0b29c2d057
inorder: ctxt switch stats
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- m5 line enforcement on use_def.cc,hh
2010-01-31 18:28:59 -05:00
Korey Sewell
ffa9ecb1fa
inorder: pipeline stage stats
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add idle/run/utilization stats for each pipeline stage
2010-01-31 18:28:51 -05:00
Korey Sewell
4d749472e3
inorder: enforce stage bandwidth
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each stage keeps track of insts_processed on a per_thread basis but we should
be keeping that on a total basis inorder to enforce stage width limits
2010-01-31 18:28:31 -05:00
Korey Sewell
b4e0ef7837
inorder: set thread status'
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set Active/Suspended/Halted status for threads. useful for system when determining
if/when to exit simulation
2010-01-31 18:28:12 -05:00