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290 commits

Author SHA1 Message Date
Andreas Hansson
10b70d5452 stats: Update stats for unified cache configuration 
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
 2012-10-30 09:35:32 -04:00
Andreas Hansson
b387d8e213 stats: Update the stats to reflect the 1GHz default system clock 
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
 2012-10-25 13:15:59 -04:00
Andreas Hansson
8fe556338d stats: Update stats to reflect use of SimpleDRAM 
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
 2012-10-25 13:14:42 -04:00
Andreas Hansson
a4329af937 stats: Update stats for DMA port send 
This patch updates the stats after removing the zero-time send used in
the DMA port.
 2012-10-23 04:49:48 -04:00
Nilay Vaish
de3b3ed140 regressions: update stats for eio tests 2012-10-16 14:47:31 -05:00
Nilay Vaish
b6b5cde132 regressions: update stats due to change to ruby memory system 2012-10-15 19:13:59 -05:00
Andreas Hansson
d52adc4eb6 Stats: Update stats for cache timings in cycles 
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
 2012-10-15 08:12:21 -04:00
Andreas Hansson
d17f5084ed Stats: Update memtest stats after setting clock 
This patch updates the memtest stats to reflect the addition of a
clock other than the default one.
 2012-10-15 08:10:52 -04:00
Andreas Hansson
54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width 
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
 2012-10-15 08:09:54 -04:00
Andreas Hansson
a850fc916f Stats: Update stats for use of two-level builder 
This patch updates the name of the l2 stats.
 2012-10-15 08:08:06 -04:00
Nilay Vaish
0de0ce106a Regression Tests: Update statistics 2012-10-02 14:35:46 -05:00
Ali Saidi
91e74beee6 ARM: update stats for bp and squash fixes. 2012-09-25 11:49:41 -05:00
Andreas Hansson
4f8ad7aa05 Stats: Update stats for twosys-tsunami after setting CPU clock 
This patch updates the stats to reflect the addition of a clock
period other than the default 1 Tick.
 2012-09-24 18:03:43 -04:00
Andreas Hansson
6427342318 SimpleDRAM: A basic SimpleDRAM regression 
--HG--
rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py
rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg
rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
 2012-09-21 11:48:14 -04:00
Andreas Hansson
efea870fce TrafficGen: Add a basic traffic generator regression 
This patch adds a basic regression for the traffic generator. The
regression also serves as an example of the file formats used. More
complex regressions that make use of a DRAM controller model will
follow shortly.
 2012-09-21 11:48:11 -04:00
Andreas Hansson
d2b57a7473 Stats: Update stats to reflect SimpleMemory bandwidth 
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
 2012-09-18 10:30:04 -04:00
Andreas Hansson
ae1652b813 Stats: Remove the reference stats that are no longer present 
This patch simply removes the commitCommittedInsts and
commitCommittedOps from the reference statistics, following their
removal from the CPU.
 2012-09-13 08:02:55 -04:00
Nilay Vaish
fe5deb4a22 x86 Regressions: Update stats due to register predication 2012-09-11 09:34:40 -05:00
Nilay Vaish
5cdf221d8c Regression: Updates due to changes to Ruby memory controller 2012-09-10 12:44:03 -05:00
Andreas Hansson
0b1108c7a3 Ruby: Bump the stats after recent memory controller changes 
This patch simply bumps the stats to avoid having failing
regressions. Someone with more insight in the changes should verify
that these differences all make sense.
 2012-09-10 11:57:47 -04:00
Andreas Hansson
d628344574 Device: Update stats for PIO and PCI latency change 
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
 2012-09-10 11:57:37 -04:00
Joel Hestness
4124ea09f8 stats: Update Ruby regressions for memory controller fix 2012-09-05 20:53:34 -05:00
Nilay Vaish
1032bc72ed Regression: updates ruby.stats due to change in virtual network 2012-08-25 15:49:07 -05:00
Ali Saidi
73e9e923d0 stats: Update stats for syscall emulation Linux kernel changes. 2012-08-15 10:38:05 -04:00
Ali Saidi
19cc023cf5 stats: fix some miss-committed changes from the icache change 2012-07-28 13:48:04 -04:00
Ali Saidi
b1a58933e0 stats: update stats for icache change not allowing dirty data 2012-07-27 16:08:05 -04:00
Steve Reinhardt
42596d27e9 test: Update eio ref outputs due to recent changes 
Actual stats updates covering period since original ref outputs
were clobbered.
 2012-07-23 00:39:12 -04:00
Steve Reinhardt
882a4b65bd test: Restore eio ref files clobbered in rev 8800b05e1cb3. 
Apparently Nate did a wholesale update of stats files using
a binary compiled without eio, resulting in broken refernce
outputs.
 2012-07-23 00:33:05 -04:00
Nilay Vaish
2590a7dd0a Regression: Update stats due to changes to x86 cpuid instruction 2012-07-22 20:31:24 -05:00
Nilay Vaish
019ced8d85 Regression: update ruby.stats file 2012-07-12 08:39:20 -05:00
Brad Beckmann
b00fe08cc9 regress: ruby stat additions and config changes 2012-07-10 22:51:55 -07:00
Andreas Hansson
fda338f8d3 Stats: Updates due to bus changes 
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
 2012-07-09 12:35:41 -04:00
Ali Saidi
3965ecc36b Stats: Update stats for RAS and LRU fixes. 2012-06-29 11:19:03 -04:00
Ali Saidi
c49e739352 all: Update stats for memory per master and total fix. 2012-06-05 01:23:16 -04:00
Gabe Black
6437f3f4ee X86: Update stats for the CPUID change. 2012-06-04 10:43:11 -07:00
Nilay Vaish
0bff8eb210 X86 Regression: update stats due to cc register split 2012-05-22 11:38:04 -05:00
Ali Saidi
e62beaaa8f ARM: update stats for clock frequency fix. 2012-05-10 18:04:29 -05:00
Nathan Binkert
4a644767c5 stats: update stats for no_value -> nan 
Lots of accumulated older changes too.
 2012-05-09 11:52:14 -07:00
Nilay Vaish
e8f56bdf45 Regression: Move x86 fs ruby simulation from quick to long 
--HG--
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
 2012-05-03 23:18:13 -05:00
Nilay Vaish
8966e6d36d Regression: Stats update for X86 Ruby FS test 
The kernel originally used to generate the stats is different from the one
at use on zizzer. This patch updates the stats with the correct kernel in
use.
 2012-04-30 03:47:22 -05:00
Nilay Vaish
86f248e2a7 Regression: Add a test for x86 timing full system ruby simulation 2012-04-25 22:43:36 -05:00
Andreas Hansson
4bd61abb51 Stats: Update with use of std::map for ordered iteration in Ruby 
This patch updates the stats to reflect the changes due to the use of
std::map instead of the hash map order-dependent iteration in Ruby.
 2012-04-12 08:35:56 -04:00
Brad Beckmann
697fd8987b regress: ruby random tester and hammer stats updates 2012-04-06 16:16:24 -07:00
Ali Saidi
3c666083c6 ARM: Update stats for IT and conditional branch changes 2012-03-21 10:36:45 -05:00
Ali Saidi
470051345a ARM: Update stats for CBNZ fix. 2012-03-09 15:33:07 -05:00
Ali Saidi
927bba9d60 ARM: Update stats for valgrind fix and replace config.inis which are out of date. 2012-03-09 09:59:29 -05:00
Geoffrey Blake
da0d67c3d6 CheckerCPU: Make some basic regression tests for CheckerCPU 
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
 2012-03-09 09:59:28 -05:00
Andreas Hansson
c0b9f324bf Stats: Fix the realview regression stats after nvmem move 
This patch updates the realview regressions stats to reflect that nvmem
moved in the object hierarchy and is now under system.realview.
 2012-03-02 09:18:50 -05:00
Steve Reinhardt
13e14ba93c EIO: update stats (mostly order change, some renames) 2012-02-29 01:51:39 -05:00
Ali Saidi
0d46708dc2 bp: fix up stats for changes to branch predictor 2012-02-13 12:30:30 -06:00