Commit graph

5358 commits

Author SHA1 Message Date
Andreas Hansson
07cf9d914b MEM: Separate queries for snooping and address ranges
This patch simplifies the address-range determination mechanism and
also unifies the naming across ports and devices. It further splits
the queries for determining if a port is snooping and what address
ranges it responds to (aiming towards a separation of
cache-maintenance ports and pure memory-mapped ports). Default
behaviours are such that most ports do not have to define isSnooping,
and master ports need not implement getAddrRanges.
2012-01-17 12:55:09 -06:00
Andreas Hansson
142380a373 MEM: Remove Port removeConn and MemObject deletePortRefs
Cleaning up and simplifying the ports and going towards a more strict
elaboration-time creation and binding of the ports.
2012-01-17 12:55:09 -06:00
Andreas Hansson
6315e5bbb5 MEM: Remove the notion of the default port
This patch removes the default port and instead relies on the peer
being set to NULL initially. The binding check (i.e. is a port
connected or not) will eventually be moved to the init function of the
modules.
2012-01-17 12:55:09 -06:00
Andreas Hansson
de34e49d15 MEM: Simplify ports by removing EventManager
This patch removes the inheritance of EventManager from the ports and
moves all responsibility for event queues to the owner. Eventually the
event manager should be the interface block, which could either be the
structural owner or a subblock like a LSQ in the O3 CPU for example.
2012-01-17 12:55:09 -06:00
Andreas Hansson
b3f930c884 CPU: Moving towards a more general port across CPU models
This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.
2012-01-17 12:55:08 -06:00
Andreas Hansson
f85286b3de MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort      > PortProxy
TranslatingPort     > SETranslatingPortProxy
VirtualPort         > FSTranslatingPortProxy

--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17 12:55:08 -06:00
Andreas Hansson
43a45edcf0 Ruby: Change the access permissions for MOESI hammer
This patch changes the access permission for the WB_E_W state from
Busy to Read_Write to avoid having issues in follow-on patches with
functional accesses going through Ruby. This change was made after
consultation with all involved parties and is more of a work-around
than a fix.
2012-01-17 12:55:07 -06:00
Andreas Hansson
41af57f9fb MEM: Add the system port as a central access point
The system port is used as a globally reachable access point to the
memory subsystem. The benefit of using an actual port is that the
usual infrastructure is used to resolve any access and thus makes the
overall system able to handle distributed memories in any
configuration, and also makes the accesses agnostic to the address
map. This patch only introduces the port and does not actually use it
for anything.
2012-01-17 12:55:07 -06:00
Andreas Hansson
13ef7a5647 MEM: Differentiate functional cache accesses from CPU and memory
This patch changes the functionalAccess member function in the cache
model such that it is aware of what port the access came from, i.e. if
it came from the CPU side or from the memory side. By adding this
information, it is possible to respect the 'forwardSnoops' flag for
snooping requests coming from the memory side and not forward
them. This fixes an outstanding issue with the IO bus getting accesses
that have no valid destination port and also cleans up future changes
to the bus model.
2012-01-17 12:55:07 -06:00
Steve Reinhardt
7a3a37307a Alpha: warn_once about broken PAL breakpoints.
A recent changeset (aae12ce9f34c) removed support for
PAL-mode breakpoints in Alpha, since it was awkward
and likely unused.  This patch lets a user know if they
potentially run into this limitation.
2012-01-16 19:01:27 -08:00
Steve Reinhardt
1585cfb5b5 debug: fix AllFlags::disable()
Looks like copy-and-paste bug, apparently I'm the first
person to ever use this since it's plainly broken.
2012-01-16 19:00:59 -08:00
Maximilien Breughe
a7394ad680 inorder: MDU deadlock fix 2012-01-12 10:15:00 -05:00
Deyuan Guo
4a59cf00b4 mips: compatibility between MIPS_SE and cross compiler from CodeSorcery 2012-01-12 09:59:01 -05:00
Deyuan Guo
31b6941a52 mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FS 2012-01-12 09:59:00 -05:00
Deyuan Guo
a40ec5671f mips: Fix decoder of two float-convert instructions 2012-01-12 09:58:59 -05:00
Deyuan Guo
7f782a6c79 mips: definition of MIPS64_QNAN in registers.hh 2012-01-12 09:58:58 -05:00
Nilay Vaish
0e6d6a5e25 PerfectCacheMemory: Remove references to CacheMsg
The definition for the class CacheMsg was removed long back. Some declaration
had still survived, which was recently removed. Since the PerfectCacheMemory
class relied on this particular declaration, its absence let to compilation
breaking down. Hence this patch.
2012-01-12 00:35:57 -06:00
Ali Saidi
c40ae2c3fb Packet: Put back part of the assert 2012-01-11 19:27:11 -05:00
Ali Saidi
bc1c21274e Packet: Remove meaningless assert statement 2012-01-11 19:24:13 -05:00
Nilay Vaish
bf59a9298f Ruby: Resurrect Cache Warmup Capability
This patch resurrects ruby's cache warmup capability. It essentially
makes use of all the infrastructure that was added to the controllers,
memories and the cache recorder.
2012-01-11 13:48:48 -06:00
Nilay Vaish
3f8065290a Ruby Debug Flags: Remove one, add another
The flag RubyStoreBuffer is being removed, instead RubySystem is being added
2012-01-11 13:42:00 -06:00
Nilay Vaish
2d3cae02f5 Ruby Port: Add a list of cpu ports attached to this port 2012-01-11 13:39:58 -06:00
Nilay Vaish
17fc60ee88 Ruby EventQueue: Remove unused functions 2012-01-11 13:31:04 -06:00
Nilay Vaish
8b3ad17cc3 Ruby Sparse Memory: Add function for collating blocks
This patch adds function to the Sparse Memory so that the blocks can be
recorded in a cache trace. The blocks are added to the cache recorder
which can later write them into a file.
2012-01-11 13:29:54 -06:00
Nilay Vaish
c3109f7775 Ruby: Add infrastructure for recording cache contents
This patch changes CacheRecorder, CacheMemory, CacheControllers
so that the contents of a cache can be recorded for checkpointing
purposes.
2012-01-11 13:29:15 -06:00
Nilay Vaish
ab0347a1c6 Ruby Memory Vector: Functions for collating and populating pages
This patch adds functions to the memory vector class that can be used for
collating memory pages to raw trace and for populating pages from a raw
trace.
2012-01-11 11:46:23 -06:00
Nilay Vaish
bd739a75b9 Ruby: remove the files related to the tracer
The Ruby Tracer is out of date with the changes that are being carried
out to support checkpointing. Hence, it needs to be removed.
2012-01-10 18:35:45 -06:00
Nilay Vaish
70cb16ba14 MOESI Hammer: Remove a couple of bugs
A couple of bugs were observed while building checkpointing support in Ruby.
This patch changes transitions to remove those errors.
2012-01-10 17:28:44 -06:00
Nilay Vaish
adff204c97 Sparse Memory: Simplify the structure for an entry
The SparseMemEntry structure includes just one void* pointer. It seems
unnecessary that we have a structure for this. The patch removes the
structure and makes use of a typedef on void* instead.
2012-01-10 10:20:32 -06:00
Ali Saidi
cfa1d26b43 Automated merge with ssh://repo.gem5.org/gem5 2012-01-10 10:18:08 -06:00
Ali Saidi
8f18898e85 config: Fix json output for Python lt 2.6. 2012-01-10 10:17:33 -06:00
Nilay Vaish
9957035a42 DPRINTF: Improve some dprintf messages. 2012-01-10 10:15:02 -06:00
Nilay Vaish
acbc03ae46 X86: Add memory fence to I/O instructions 2012-01-09 20:13:31 -06:00
Anders Handler
b587d511c3 CPU: Remove Alpha-specific PC alignment check. 2012-01-09 20:05:07 -05:00
Ali Saidi
e308208f30 Config: Fix issue with JSON output 2012-01-09 20:04:28 -05:00
Geoffrey Blake
e826d23a2e Packet: Add derived class FunctionalPacket to enable partial functional reads
This adds the derived class FunctionalPacket to fix a long standing
deficiency in the Packet class where it was unable to handle finding data to
partially satisfy a functional access.  Made this a derived class as
functional accesses are used only in certain contexts and to not add any
additional overhead to the existing Packet class.
2012-01-09 18:10:05 -06:00
Dam Sunwoo
bda1125e88 stats: fix Vector2d to display stats correctly when y_subname is not specified.
Vector2d stats with no y_subname were not displayed as the VectorPrint subname was not initialized correctly to reflect the empty field.
2012-01-09 18:08:20 -06:00
Prakash Ramrakhyani
51aa7e4a03 sim: Enable sampling of run-time for code-sections marked using pseudo insts.
This patch adds a mechanism to collect run time samples for specific portions
of a benchmark, using work_begin and work_end pseudo instructions.It also enhances
the histogram stat to report geometric mean.
2012-01-09 18:08:20 -06:00
Ali Saidi
525d1e46dc O3: Remove some asserts that no longer seem to be valid. 2012-01-09 18:08:20 -06:00
Ali Saidi
68d387ec80 config: support outputing a pickle of the configuration tree 2012-01-09 18:08:20 -06:00
Min Kyu Jeong
c94e5256d9 mem: Change DPRINTF prints more useful destination port number.
Old code prints 0 for destination since pkt->getDest() returns 0 for
pkt->getDest() == Packet::Broadcast, which is always true.
2012-01-09 18:08:20 -06:00
Ali Saidi
d2c26f402c O3: Add support of function tracing with O3 CPU. 2012-01-09 18:08:20 -06:00
Ali Saidi
bcb71963eb ARM: Add support for running multiple systems 2012-01-09 18:08:20 -06:00
Ali Saidi
80a6907927 ARM: Add support for initparam m5 op 2012-01-09 18:08:20 -06:00
Dam Sunwoo
3f9e352de4 Base: Fixed shift amount in genrand() to work with large numbers
The previous version didn't work correctly with max integer values (2^31-1 for
32-bit, 2^63-1 for 64bit version), causing "shift" to become -1.  For smaller
numbers, it wouldn't have caused functional errors, but would have resulted in
more than necessary loops in the while loop.  Special-cased cases when (max + 1
== 0) to prevent the ceilLog2 functions from failing.
2012-01-09 18:08:20 -06:00
Andreas Hansson
59b7cad3ec SWIG: Make gem5 compile and link with swig 2.0.4
To make gem5 compile and run with swig 2.0.4 a few minor fixes are
necessary, the fail label issues by swig must not be treated as an
error by gcc (tested with gcc 4.2.1), and the vector wrappers must
have SWIGPY_SLICE_ARG defined which happens in pycontainer.swg,
included through std_container.i. By adding the aforementioned include
to the vector wrappers everything seems to work.
2012-01-09 18:08:20 -06:00
Andreas Hansson
c2dbfc1d6c MAC: Make gem5 compile and run on MacOSX 10.7.2
Adaptations to make gem5 compile and run on OSX 10.7.2, with a stock
gcc 4.2.1 and the remaining dependencies from macports, i.e. python
2.7,.2 swig 2.0.4, mercurial 2.0. The changes include an adaptation of
the SConstruct to handle non-library linker flags, and Darwin-specific
code to find the memory usage of gem5. A number of Ruby files relied
on ambigious uint (without the 32 suffix) which caused compilation
errors.
2012-01-09 18:08:20 -06:00
Nilay Vaish
10c2e8ae9a Ruby Cache: Add param for marking caches as instruction only 2012-01-07 07:38:53 -06:00
Gabe Black
241cc0c840 Another merge with the main repository. 2012-01-07 02:16:37 -08:00
Gabe Black
ec936364b7 Merge with the main repository again. 2012-01-07 02:15:35 -08:00
Gabe Black
36a822f08e Merge with main repository. 2012-01-07 02:10:34 -08:00
Nilay Vaish
ce941fd2ae AbstractController: Remove some of the unused functions
--HG--
extra : rebase_source : 78df7398a609f1db8a2592cd2d1bdc9156d1b8c3
2012-01-06 05:11:07 -06:00
Nilay Vaish
6da125cc3c Ruby Set: Move NUMBER_WORDS_PER_SET to Set.hh
This constant is currently in System.hh, but is only used in Set.hh. It
is being moved to Set.hh to remove this artificial dependence of Set.hh
on System.hh.

--HG--
extra : rebase_source : 683c43a5eeaec4f5f523b3ea32953a07f65cfee7
2012-01-06 05:11:07 -06:00
Nilay Vaish
daa4c7526a eventq: add a function for replacing head of the queue
This patch adds a function for replacing the event at the head of the queue
with another event. This helps in running a different set of events. Events
already scheduled can processed by replacing the original head event back.
This function has been specifically added to support cache warmup and
cooldown required for creating and restoring checkpoints.

--HG--
extra : rebase_source : ed6e2905720b6bfdefd020fab76235ccf33d28d1
2012-01-05 11:02:56 -06:00
Nilay Vaish
d3aa01eed9 MESI Coherence Protocol: Fix L2 miss statistics
This patch removes calls to uu_ProfileMiss from transitions where the request
is satisfied by the L2 cache controller.

--HG--
extra : rebase_source : e59fe7c6cd5795c0019cf178dd3b062d73cc2ff5
2012-01-05 11:00:45 -06:00
Nilay Vaish
bd23a37198 X86 TLB: Move a DPRINTF to its correct place
The DPRINTF for doing protection checks appears after the checks have been
carried out. It is possible that the function returns while the checks are
being carried, in which case the printf is missed out. This patch moves the
DPRINTF before the checks.

--HG--
extra : rebase_source : 172896057e593022444d882ea93323a5d9f77a89
2012-01-05 11:00:32 -06:00
Nilay Vaish
ea94029ea5 Ruby: Shuffle some of the included files
This patch adds and removes included files from some of the files so as to
organize remove some false dependencies and include some files directly
instead of transitively.

--HG--
extra : rebase_source : 09b482ee9ae00b3a204ace0c63550bc3ca220134
2011-12-31 18:44:51 -06:00
Nilay Vaish
734ef9a209 SLICC: Use pointers for directory entries
SLICC uses pointers for cache and TBE entries but not for directory entries.
This patch changes the protocols, SLICC and Ruby memory system so that even
directory entries are referenced using pointers.

--HG--
extra : rebase_source : abeb4ac78033d003153751f216fd1948251fcfad
2011-12-31 16:38:30 -06:00
Ali Saidi
94ce971278 IO: Fix bug in DMA Device where receiving a snoop on DMA port would cause a panic.
--HG--
extra : rebase_source : 8152d4fa7d7354c9f150a450ae0710e95141ba4b
2011-12-15 00:09:46 -05:00
Nathan Binkert
6ef9691035 gcc: fix unused variable warnings from GCC 4.6.1
--HG--
extra : rebase_source : f9e22de341493a25ac6106c16ac35c61c128a080
2011-12-13 11:49:27 -08:00
Ali Saidi
9b52717a92 Trace: FIx issue with creation of trace file with output dir overhaul.
--HG--
extra : rebase_source : c1ab57ea8805703d97cdee4f32410821a2d2a9db
2011-12-01 17:36:22 -08:00
Brad Beckmann
8daad28a90 MOESI_hammer: fixed L2 to L1 infinite stalls and deadlock
--HG--
extra : rebase_source : 90f217f28e195a8cee5d64b25c913b452d818676
2011-12-01 10:08:52 -08:00
Brad Beckmann
cecbdb6d79 physmem: Improved fatal message for size mismatch
--HG--
extra : rebase_source : 16da1c63263f8fd6fef9a842c577343cd6246a35
2011-12-01 10:08:52 -08:00
Chris Emmons
9aea847f58 VNC: Add support for capturing frame buffer to file each time it is changed.
When a change in the frame buffer from the VNC server is detected, the new
frame is stored out to the m5out/frames_*/ directory.  Specifiy the flag
"--frame-capture" when running configs/example/fs.py to enable this behavior.

--HG--
extra : rebase_source : d4e08e83f4fa6ff79f3dc9c433fc1f0487e057fc
2011-12-01 00:15:26 -08:00
Chris Emmons
5bde1d359f Output: Add hierarchical output support and cleanup existing codebase.
--HG--
extra : rebase_source : 3301137733cdf5fdb471d56ef7990e7a3a865442
2011-12-01 00:15:25 -08:00
Ali Saidi
5d50ee420d SE: Don't warn when not extending stack as it's too noisy with O3.
--HG--
extra : rebase_source : e56d1551d42d46b5f357cd63f9891715b664f6fc
2011-12-01 00:15:25 -08:00
Chander Sudanthi
61c14da751 O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.

--HG--
extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-12-01 00:15:22 -08:00
Mitchell Hayenga
fa753c1454 Device: Make changes necessary to support a coherent page walker cache.
Adds the flag 'recvSnoops' which enables pagewalkers using DmaPorts,
to properly configure snoops.

--HG--
extra : rebase_source : 64207bef62c3268ddff2236ee4adae873812325f
2011-12-01 00:15:22 -08:00
Ali Saidi
946f7f0f55 ARM: Add support for having a TLB cache.
--HG--
extra : rebase_source : 7a5780ab74d7c294682738c7ccb3ce8d56c6fd63
2011-12-01 00:15:22 -08:00
Ali Saidi
5901c5223f ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .
Squashes the subsequent instructions in O3 pipe after the service call, so that
they see the effect of the system call when re-executed. This isn't really an issue
with FS mode, but can show up in SE mode.

--HG--
extra : rebase_source : 613a69fe1d9834261e25a8cd340aa6b47578e1fe
2011-12-01 00:15:22 -08:00
Ali Saidi
1444103998 O3: Add stat that counts how many cycles the O3 cpu was quiesced.
--HG--
extra : rebase_source : 043b9307eef3c5b87f8e6370765641e016ed1fa7
2011-12-01 00:15:22 -08:00
Gabe Black
93fb460fad X86: Fix a bad segmentation check for the stack segment.
--HG--
extra : rebase_source : 755f4f6eae52f88ed516a1f1ac9e2565725d89c1
2011-12-01 00:17:14 -05:00
Gabe Black
87b66c9ae3 SPARC: Minor style fix.
I forgot to fix this as well per Ali's feedback.

--HG--
extra : rebase_source : e70d031cb5f91e2212a1a73ea1769bf0549b826c
2011-11-28 04:35:55 -05:00
Andreas Hansson
64ccfecf95 SPARC: Fixing a minor copy-paste bug using the wrong variable
There was a bug in the mm_disk implementation where a copy paste error
resulted in the d32 variable not being initialised (as it incorrectly
was used instead of d16), and gcc 4.5 complaining.

--HG--
extra : rebase_source : 9515e87b188b9eac189da8034cb13c3bf7d9e20b
2011-11-28 04:34:18 -05:00
Gabe Black
e7d0c999a1 SPARC: Isolate FP operations enough to prevent code/rounding mode reordering.
--HG--
extra : rebase_source : ee79ab89c5a707c1294f38abb84c60f8ef64196c
2011-11-27 22:00:58 -05:00
Gabe Black
13552dc304 Compiler: Add an M5_NO_INLINE define.
--HG--
extra : rebase_source : 1f5e8b7bb6b0a8bb4f951b6d7189964d96ed5df1
2011-11-27 22:00:57 -05:00
Tushar Krishna
88e91cafc6 Topology: bug fix in external link initialization
--HG--
extra : rebase_source : c226cd1e5e5ed4d4c64fa9427de4905bd8335e34
2011-11-23 16:34:13 -05:00
Tushar Krishna
eff430a972 Remove standard_1level_CMP-protocol.sm include statement from Network
--HG--
extra : rebase_source : 51a2dd4bb643e3dc5b0218a6190cf5c1989f9691
2011-11-22 20:11:18 -05:00
Gabe Black
49a2d54e1a X86: Fix the constant detecting three byte opcodes in the predecoder.
--HG--
extra : rebase_source : b64c3d2348cb73177024695fb6e205d51bf1cda9
2011-11-20 05:10:05 -08:00
Gabe Black
85424bef19 SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
Gabe Black
de21bb93ea SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 2011-11-18 01:33:28 -08:00
Nilay Vaish
f3b4d10a05 Ruby: Process packet instead of RubyRequest in Sequencer
This patch changes the implementation of Ruby's recvTiming() function so
that it pushes a packet in to the Sequencer instead of a RubyRequest. This
requires changes in the Sequencer's makeRequest() and issueRequest()
functions, as they also need to operate on a Packet instead of RubyRequest.
2011-11-14 17:44:35 -06:00
Gabe Black
ec32d85f9d Power: Add a stubbed out stacktrace.cc 2011-11-13 12:40:15 -08:00
Gabe Black
ff4ba82610 POWER: Add a stub implementation of initCPU. 2011-11-13 12:40:15 -08:00
Gabe Black
1a8f1809fa Power: Add a stub kernel_stats.hh. 2011-11-13 12:40:15 -08:00
Gabe Black
5fcd11eaa5 SE/FS: Get rid of FULL_SYSTEM in dev. 2011-11-13 02:05:32 -08:00
Gabe Black
362a53e572 SE/FS: Get rid of FULL_SYSTEM in kern. 2011-11-13 02:05:32 -08:00
Gabe Black
6d68887c87 Power: Implement a stub for getArgument. 2011-11-13 02:05:27 -08:00
Gabe Black
2ee59cee1b GCC: Guard some gcc flags so they're used when available and needed. 2011-11-09 21:48:28 -08:00
Gabe Black
71c4534ce9 SE/FS: Get rid of FULL_SYSTEM in mem. 2011-11-07 01:13:43 -08:00
Gabe Black
812277ac6a SE/FS: Remove FULL_SYSTEM from swig. 2011-11-07 01:06:54 -08:00
Tushar Krishna
ac993964a9 GARNET: adding a fault model for resilient on-chip network research.
This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.
2011-11-04 18:40:22 -04:00
Nilay Vaish
5ff6e05ffd MESI Protocol: Add functions for profiling misses 2011-11-04 11:26:12 -05:00
Nilay Vaish
582ea4d543 x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.
2011-11-03 22:52:21 -05:00
Nilay Vaish
fb5c095cd5 Protocol: Remove standard one and two level files 2011-11-03 22:52:02 -05:00
Nilay Vaish
a547cf34b9 Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.
2011-11-03 22:46:45 -05:00
Gabe Black
8b4a3f4070 SE/FS: Get rid of FULL_SYSTEM in sim. 2011-11-02 02:11:14 -07:00
Gabe Black
fb15604f2c SE/FS: Get FULL_SYSTEM out of base/remote_gdb.cc. 2011-11-02 01:27:45 -07:00
Gabe Black
239b33e016 SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. 2011-11-02 01:25:15 -07:00
Gabe Black
7b417d4188 SE/FS: Get rid of the last use of FULL_SYSTEM in x86. 2011-11-01 04:01:15 -07:00
Gabe Black
b6da5e2086 SE/FS: Get rid of uses of FULL_SYSTEM in Alpha. 2011-11-01 04:01:14 -07:00
Gabe Black
1268e0df1f SE/FS: Expose the same methods on the CPUs in SE and FS modes. 2011-11-01 04:01:13 -07:00
Gabe Black
eeb85a8575 SE/FS: Remove the last uses of FULL_SYSTEM from SPARC. 2011-10-31 02:58:24 -07:00
Gabe Black
8ad2b8c559 SE/FS: Make the functions available from the TC consistent between SE and FS. 2011-10-31 02:58:22 -07:00
Gabe Black
d735abe5da GCC: Get everything working with gcc 4.6.1.
And by "everything" I mean all the quick regressions.
2011-10-31 01:09:44 -07:00
Gabe Black
ef097eb69c SE/FS: Build the solaris object in both SE and FS. 2011-10-30 18:52:30 -07:00
Gabe Black
248033f31e SE/FS: Get rid of FULL_SYSTEM in MIPS. 2011-10-30 18:39:38 -07:00
Gabe Black
8009b53c41 SE/FS: Compile in system events in SE mode. 2011-10-30 17:38:11 -07:00
Gabe Black
37a437893e System: Push boot_cpu_frequency down into the subclasses that actually use it.
This parameter depends on a number of coincidences to work properly. First,
there must be an array assigned to system called "cpu" even though there's no
parameter called that. Second, the items in the "cpu" array have to have a
"clock" parameter which has a "frequency" member. This is true of the normal
CPUs, but isn't true of the memory tester CPUs. This happened to work before
because the memory tester CPUs were only used in SE mode where this parameter
was being excluded. Since everything is being pulled into a common binary,
this won't work any more. Since the boot_cpu_frequency parameter is only used
by Alpha's Linux System object (and Mips's through copy and paste), the
definition of that parameter is moved down to those objects specifically.
2011-10-30 17:38:09 -07:00
Nilay Vaish
49c64731fa Python: Remove import for random 2011-10-30 15:55:32 -05:00
Gabe Black
b144f05b53 SE/FS: Remove the last references to FULL_SYSTEM from POWER. 2011-10-30 03:55:24 -07:00
Gabe Black
6dc3cedc4e X86: Build the same files in SE and FS. 2011-10-30 03:06:40 -07:00
Gabe Black
ca77249b0c SE/FS: Build syscall_emul.cc in FS mode. 2011-10-30 03:06:37 -07:00
Gabe Black
0c81db77f2 SE/FS: Make the system object more consistent between SE and FS. 2011-10-30 02:30:55 -07:00
Gabe Black
1d8822a364 X86: Get rid of more uses of FULL_SYSTEM. 2011-10-30 00:33:02 -07:00
Gabe Black
facb40f3ff SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. 2011-10-30 00:33:02 -07:00
Gabe Black
5b433568f0 SE/FS: Build the base process class in FS. 2011-10-30 00:32:54 -07:00
Nilay Vaish
706323fa21 Merged with recent changes. 2011-10-28 13:04:33 -05:00
Nilay Vaish
cbaebb3b5e Ruby: Reorganize mapping of components
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for
mapping MachineType to GenericMachineType. These '#define's are being
eliminated and the code will now be generated by SLICC instead. Also
are being eliminated some of the unused functions from
RubySlicc_ComponentMapping.sm.
2011-10-28 13:00:35 -05:00
Steve Reinhardt
6f9d294e86 SE: move page allocation from PageTable to Process
PageTable supported an allocate() call that called back
through the Process to allocate memory, but did not have
a method to map addresses without allocating new pages.
It makes more sense for Process to do the allocation, so
this method was renamed allocateMem() and moved to Process,
and uses a new map() call on PageTable.

The remaining uses of the process pointer in PageTable
were only to get the name and the PID, so by passing these
in directly in the constructor, we can make PageTable
completely independent of Process.
2011-10-22 22:30:08 -07:00
Steve Reinhardt
4d5f2c28a8 syscall_emul: implement MAP_FIXED option to mmap() 2011-10-22 22:30:07 -07:00
Steve Reinhardt
38aef4c4c7 dev: clean up PioDevice and DmaDevive getPort() methods.
Make DmaDevice::getPort() call PioDevice::getPort() instead
of just copying and pasting the code.

Also move definitions from .hh to .cc file.
2011-10-20 13:11:56 -07:00
Steve Reinhardt
7b500f56ca SimObject: add export_method* hooks to export C++ methods to Python
Replace the (broken as of previous changeset) swig_objdecl() method
that allowed/forced you to substitute a whole new C++ struct
definition for SWIG to wrap with a set of export_method* hooks
that let you just declare a set of C++ methods (or other declarations)
that get inserted in the auto-generated struct.

Restore the System get/setMemoryMode methods, and use this mechanism
to specialize SimObject as well, eliminating teh need for sim_object.i.
Needed bits of sim_object.i are moved to the new pyobject.i.
Also sucked a little SimObject specialization into cxx_param_decl()
allowing us to get rid of src/sim/sim_object_params.hh.  Now the
generation and wrapping of the base SimObject param struct is more
in line with how derived objects are handled.

--HG--
rename : src/python/swig/sim_object.i => src/python/swig/pyobject.i
2011-10-20 13:09:10 -07:00
Steve Reinhardt
45d14e02c4 scons/swig: refactor some of the scons/SWIG code
- Move the random bits of SWIG code generation out of src/SConscript
  file and into methods on the objects being wrapped.
- Cleaned up some variable naming and added some comments to make
  the process a little clearer.
- Did a little generated file/module renaming:
   - vptype_Foo now Foo_vector
   - init_Foo is now Foo_init
  This makes it easier to see all the Foo-related files in a
  sorted directory listing.
- Made cxx_predecls and swig_predecls normal SimObject classmethods.
- Got rid of swig_objdecls hook, even though this breaks the System
  objects get/setMemoryMode method exports.  Will be fixing this in
  a future changeset.
2011-10-20 13:08:49 -07:00
Nathan Binkert
d8cc8d3ab8 scons: fix building of shared objects 2011-10-17 17:06:40 -07:00
Gabe Black
ca36c01f7e SE/FS: Make some system funcs available in SE and FS. 2011-10-16 05:06:40 -07:00
Gabe Black
464c485d0c SE/FS: Include getMemPort in FS. 2011-10-16 05:06:40 -07:00
Gabe Black
bcf664e5f9 SE/FS: Turn on the page table class in FS. 2011-10-16 05:06:40 -07:00
Gabe Black
6ba3ebae43 SE/FS: Build in the tport in FS mode. 2011-10-16 05:06:40 -07:00
Gabe Black
3595b0c5a1 SE/FS: Build/expose vport in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
79ba4b6595 SPARC: Build vtophys into SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
5ee3f586bf Power: Add a stub implementation for vtophys in SE and FS. 2011-10-16 05:06:39 -07:00
Gabe Black
baae510b56 MIPS: Build vtophys in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
1eb459a79e ARM: Build vtophys in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
b2af015b97 ARM: Turn on the page table walker on ARM in SE mode. 2011-10-16 05:06:38 -07:00
Gabe Black
dd8fed7387 Alpha: Turn on vtophys in SE mode. 2011-10-16 02:59:53 -07:00
Gabe Black
e8e9f97312 CPU: Make physPort and getPhysPort available in SE mode. 2011-10-16 02:59:53 -07:00
Gabe Black
85ca77d114 X86: Build vtophys in SE mode. 2011-10-13 02:26:21 -07:00
Gabe Black
8adc6781bf X86: Turn on the page table walker in SE mode. 2011-10-13 02:22:23 -07:00
Gabe Black
4b2e5ebead SPARC: Remove the last checks of FULL_SYSTEM. 2011-10-13 01:37:19 -07:00
Gabe Black
6b5ede5e39 SPARC: Narrow the scope of #if FULL_SYSTEM in SPARC's faults. 2011-10-13 01:11:00 -07:00
Nilay Vaish
b61e34fab8 mc146818: Correctly serialize tickEvent
'tickEvent' was not being serialized as in its place 'event' was being used.
This patch rectifies this error.
2011-10-10 17:01:33 -05:00
Gabe Black
afa7a34563 SPARC: Let the TLB have friends in FS mode. 2011-10-10 00:38:57 -07:00
Gabe Black
8eec565d0d SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC. 2011-10-10 00:31:51 -07:00
Gabe Black
5bab52d56d [mq]: sefssparcregfile.patch 2011-10-09 23:48:27 -07:00
Gabe Black
48b40cff65 Interrupts: Make the IO APIC go get the local APICs.
This is so they don't have to declare themselves to the IO APIC and don't have
to have a pointer to the platform object.
2011-10-09 04:44:02 -07:00
Gabe Black
f338d60930 SE/FS: Build the Interrupt objects in SE mode. 2011-10-09 00:15:50 -07:00
Gabe Black
bfec60ad3a Ports: Print the port name when a port is used but not attached to anything. 2011-10-08 23:24:32 -07:00
Gabe Black
d368344092 SE/FS: Put platform pointers in fewer objects.
Not all objects need a platform pointer, and having one creates a dependence
on their being a platform object. This change removes the platform pointer to
from the base device object and moves it into subclasses that actually need
it.
2011-10-04 02:26:03 -07:00
Gabe Black
e2dbe59f5d SE/FS: Remove System::platform and Platform::intrFrequency.
In order for a system object to work in SE mode and FS mode, it has to either
always require a platform object even in SE mode, or get rid of the
requirement all together. Making SE mode carry around unnecessary/unused bits
of FS seems less than ideal, so I decided to go with the second option. The
platform pointer in the System class was used for exactly one purpose, a path
for the Alpha Linux system object to get to the real time clock and read its
frequency so that it could short cut the loops_per_jiffy calculation. There
was also a copy and pasted implementation in MIPS, but since it was only there
because it was there in Alpha I still count that as one use.

This change reverses the mechanism that communicates the RTC frequency so that
the Tsunami platform object pushes it up to the AlphaSystem object. This is
slightly less specific than it could be because really only the
AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform
class was no longer necessary (and unimplemented on anything but Alpha) it was
eliminated.

After this change, a platform will need to have a system, but a system won't
have to have a platform.
2011-09-30 00:29:07 -07:00
Gabe Black
91dd72a99a X86: Remove FULL_SYSTEM from the x86 faults. 2011-09-30 00:28:40 -07:00
Gabe Black
51f7a66660 SE/FS: Build the devices in SE mode. 2011-09-30 00:28:33 -07:00
Gabe Black
35e20c7470 SE/FS: Use the new FullSystem constant where possible. 2011-09-30 00:27:16 -07:00
Gabe Black
4fcf8e9959 O3: Tidy up some DPRINTFs in the LSQ. 2011-09-27 00:25:26 -07:00
Gabe Black
44ed4849d4 Faults: Replace calls to genMachineCheckFault with M5PanicFault. 2011-09-27 00:24:43 -07:00
Gabe Black
2ed3eef9b0 Faults: Add in generic faults that work like panics, warns, etc.
These faults take varargs to their constructors which they print into a string
and pass to the M5DebugFault base class. They are basically faults wrapped
around panics, faults, warns, and warnonce-es so that they happen only at
commit.
2011-09-27 00:17:09 -07:00
Gabe Black
ea79850f90 Faults: Make the generic faults more consistent between SE and FS.
All of the classes will now be available in both modes, and only
GenericPageTableFault will continue to check the mode for conditional
compilation. It uses a process object to handle the fault in SE mode, and
for now those aren't available in FS mode.
2011-09-27 00:16:33 -07:00
Gabe Black
997cbe1c09 ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.
By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
2011-09-26 23:48:54 -07:00
Nilay Vaish
56bddab189 LSQ: Moved a couple of lines to enable O3 + Ruby
This patch makes O3 CPU work along with the Ruby memory model. Ruby
overwrites the senderState pointer with another pointer. The pointer
is restored only when Ruby gets done with the packet. LSQ makes use of
senderState just after sendTiming() returns. But the dynamic_cast returns
a NULL pointer since Ruby's senderState pointer is from a different class.
Storing the senderState pointer before calling sendTiming() does away with
the problem.
2011-09-26 12:18:32 -05:00
Gabe Black
16e0215d30 SE/FS: Define a const bool FullSystem which will equal FULL_SYSTEM.
This constant will have the same value as FULL_SYSTEM but will not be usable
by the preprocessor. It can be substituted into places where FULL_SYSTEM is
used in a C++ context and will make it easier to find which parts of the
simulator still use FULL_SYSTEM with the preprocessor using grep.
2011-09-26 02:09:04 -07:00
Gabe Black
7770239792 SCons: Add a comment I forgot to add in earlier.
This comment was supposed to be added to an earlier change as part of review
feedback, but I accidentally left it out when I pushed. Add it in now.
2011-09-24 17:03:18 -07:00
Gabe Black
9f26aaa7d7 SCons: Make the ISA parser a source for its output files like the comments say.
There was a change a while ago that refactored some scons stuff which got rid
of cpu_models.py but also accidentally got rid of the ISA parser as a source
for its target files. That meant that changes which affected the parser
wouldn't cause a rebuild unless they also changed one of the description
files. This change fixes that.
2011-09-24 16:59:11 -07:00
Gabe Black
40b6c9cb2e X86: Move the MSR lookup table out of the TLB and into its own file.
Translating MSR addresses into MSR register indices took a lot of space in the
TLB source and made looking around in that file awkward. This change moves
the lookup into its own file to get it out of the way. It also changes it from
a switch statement to a hash map which should hopefully be a little more
efficient.
2011-09-23 02:42:22 -07:00
Steve Reinhardt
84f0a1bd91 event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor.  I
forget exactly why, but this made life easier when implementing
multi-queue support.

Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.
2011-09-22 18:59:55 -07:00
Steve Reinhardt
ba79155d9d pseudo_inst: clean up workbegin/workend functions
Use exitSimLoop() function instead of explicitly scheduling
on mainEventQueue (which won't work once we go to multiple
event queues).  Also introduced a local params variable to
shorten a lot of expressions.
2011-09-22 18:59:54 -07:00
Steve Reinhardt
4a4bc2e18b params.py: enhance IpAddress param handling
Print IpAddress params in dot notation for readability.
Properly compare IpAddress objects (by value and not object identity).
Also fix up derived param classes (IpNetmask and IpWithPort)
similarly.
2011-09-22 18:58:14 -07:00
Gabe Black
9a38dc6194 MIPS: Final overhaul of MIPS faults to kill #if FULL_SYSTEM
This change is a significant reorganization of the MIPS fault code that gets
rid of duplication, fixes some bugs, doubtlessly introduces others, and adds
names for the exception code constants.
2011-09-19 06:17:21 -07:00
Gabe Black
4455fc484d MIPS, faults: Update how the PC is set. 2011-09-19 06:17:21 -07:00
Gabe Black
0d9ee17012 MIPS: Get rid of skipFaultInstruction and setRestartAddress.
Neither of these functions were used.
2011-09-19 06:17:21 -07:00
Gabe Black
5ea09771be MIPS: Use inheritance to consolidate class definitions. 2011-09-19 06:17:21 -07:00
Gabe Black
7d19ff170d MIPS: Always compile in setExceptionState, including in SE mode.
Also fix the newly exposed and preexisting compile errors. This code hasn't
been exposed in a while, and it's not up to date with the rest of gem5.
2011-09-19 06:17:21 -07:00
Gabe Black
48b6636d01 MIPS: Consolidate TLB related faults.
Pass in a bool to indicate if the fault is from a store instead of having two
different classes. The classes were also misleadingly named since loads are
also processed by the DTB but should return ITB faults since they aren't
stores. The TLB may be returning the wrong fault in this case, but I haven't
looked at it closely.
2011-09-19 06:17:20 -07:00
Gabe Black
efcded334c MIPS: Get rid of the unused "count" field in FaultVals. 2011-09-19 06:17:20 -07:00
Gabe Black
ffeab06378 MIPS: Move the genMachineCheckFault function near MachineCheckFault.
Since they're so closely linked, they should be next to each other in the
file.
2011-09-19 06:17:20 -07:00
Gabe Black
59d7fc6b26 MIPS: Consolidate the two AddressErrorFault variants. 2011-09-19 06:17:20 -07:00
Gabe Black
717d4ae930 Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.
These functions aren't called anywhere and are probably only theoretically
useful.
2011-09-19 06:17:20 -07:00
Gabe Black
110c59b414 MIPS: Get rid of cruft in the fault classes.
Get rid of Fault classes left over from when this file was copied from Alpha,
and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of
the old IntegerOverflowFault stub. The Integer version is what's actually in
the manual, but the Arithmetic version had the implementation.
2011-09-19 06:17:19 -07:00
Gabe Black
7e704c9f51 MIPS: Add constructors to the fault classes. 2011-09-19 06:17:19 -07:00
Gabe Black
27388c0fe0 MIPS: Use the CRTP to streamline the Fault class definitions.
CRTP stands for the curiously recurring template pattern.
2011-09-19 06:17:19 -07:00
Gabe Black
59a5605fff SPARC: Remove #if FULL_SYSTEMs from the ISA description. 2011-09-19 06:17:19 -07:00
Gabe Black
f21ae529fb MIPS: Get rid of #if style config checks in the ISA description. 2011-09-19 06:14:02 -07:00
Gabe Black
4ad36a4684 MIPS: Guard SystemCallFault::invoke consistently.
Make sure it's declared iff it's also defined.
2011-09-19 06:09:15 -07:00
Gabe Black
49967ed268 MIPS: Get rid of the unused (and partially defined) CacheError fault. 2011-09-19 05:53:54 -07:00
Gabe Black
3eca0a2bc9 Endianness: Make it easier to check the compiled in guest endianness.
It was technically possible but clumsy to determine what endianness a guest
was configured with using the state in byteswap.hh. This change makes that
information available more directly.

Also get rid of unused (and mildly redundant) ByteOrderDiffers constant.
2011-09-19 05:19:45 -07:00
Gabe Black
978e41eab0 Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.
The remaining ones are more complicated and may require adjustments in other
parts of the simulator.
2011-09-19 03:40:30 -07:00
Gabe Black
44659cb608 PseudoInst: Make all the pseudo insts available in SE and FS. 2011-09-19 03:39:58 -07:00
Gabe Black
7701c5b1ec X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.
The decoder now checks the value of FULL_SYSTEM in a switch statement to
decide whether to return a real syscall instruction or one that triggers
syscall emulation (or a panic in FS mode). The switch statement should devolve
into an if, and also should be optimized out since it's based on constant
input.
2011-09-19 02:53:37 -07:00
Gabe Black
10c2e37f60 Syscall: Make the syscall function available in both SE and FS modes.
In FS mode the syscall function will panic, but the interface will be
consistent and code which calls syscall can be compiled in. This will allow,
for instance, instructions that use syscall to be built unconditionally but
then not returned by the decoder.
2011-09-19 02:46:48 -07:00
Gabe Black
83aa47adca PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts. 2011-09-19 02:40:19 -07:00
Gabe Black
9eda6b1d88 Pseudoinst: Add an initParam pseudo inst function. 2011-09-18 23:26:39 -07:00
Ali Saidi
6caea472a9 IGbE: Clean up debug printing and proprly account for copied bytes.
Some DPRINTFs were printing uninitalized values because the DPRINTFs were
always being printed even when the features they were printing weren't
being used. This change moves the DPRINTFs into the appropriate if blocks
and initializes the state variables correctly.

There also is a case where the offset into the packet could be calculated
incorrectly during a DMA that is fixed.
2011-09-13 12:06:13 -05:00
Daniel Johnson
cbb23a1d3c ARM: update TLB to set request packet ASID field 2011-09-13 12:06:13 -05:00
Daniel Johnson
52d30813ca Mem: Allow ASID to be set after request is created. 2011-09-13 12:06:13 -05:00
Chander Sudanthi
7c479d7349 CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault.  This patch
enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13 12:06:13 -05:00
Daniel Johnson
09a6e424ec ARM: Implement numcpus bits in L2CTLR register. 2011-09-13 12:06:13 -05:00
Ali Saidi
0c29a97ba9 Prefetch: Don't prefetch if address is in the write queue.
Check that we're not currently writing back an address the prefetcher is trying
to prefetch before issuing it. We previously checked the mshrQueue and the cache
itself, but forgot to check the writeBuffer. This fixes a memory corrucption
issue with an L2 prefetcher.
2011-09-13 12:06:13 -05:00
Ali Saidi
649c239cee LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-13 12:58:08 -04:00
Deyuan Guo
bb921b1459 MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote
debugging.

Testing:

Build gem5 for MIPS_SE and make gem5 wait at beginning:
modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc;
scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU
----
Build GDB-7.3 mips-cross:
./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/
make
make install
----
Run:
./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches
./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello
(gdb) target remote :7000
(gdb) info registers
(gdb) disassemble
(gdb) si
(gdb) break main
(gdb) c
(gdb) quit
Testing done.
2011-09-10 03:45:25 -07:00
Gabe Black
6a2b223112 PseudoInst: Add compiler guards to pseudo_inst.hh. 2011-09-10 02:31:15 -07:00
Gabe Black
49a7ed0397 StaticInst: Merge StaticInst and StaticInstBase.
Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
2011-09-09 02:40:11 -07:00
Gabe Black
b7b545bc38 Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
2011-09-09 02:30:01 -07:00
Gabe Black
a1ad9e652a Stack: Tidy up some comments, a warning, and make stack extension consistent.
Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
2011-09-09 01:01:43 -07:00
Gabe Black
f370ac5c18 ISA parser: Don't look for operands in strings. 2011-09-08 03:21:14 -07:00
Gabe Black
f4dc64655f ISA parser: Match /* */ and // style comments.
Comments should not be scanned for operands, and we should look for both /* */
style and // style.
2011-09-08 03:20:05 -07:00
Gabe Black
87d687e242 X86: Make sure instruction flags are set properly even on 32 bit machines.
The way flag bits were being set for microops in x86 ended up implicitly
calling the bitset constructor which was truncating flags beyond the width of
an unsigned long. This change sets the bits in chunks which are always small
enough to avoid being truncated. On 64 bit machines this should reduce to be
the same as before, and on 32 bit machines it should work properly and not be
unreasonably inefficient.
2011-09-05 18:36:26 -07:00
Gabe Black
3bd0b9654c X86,TLB: Make sure the "delayedResponse" variable is always set.
When an instruction is translated in the x86 TLB, a variable called
delayedResponse is passed back and forth which tracks whether a translation
could be completed immediately, or if there's going to be callback that will
finish things up. If a read was to the internal memory space, memory mapped
registers used to implement things like MSRs, the function hadn't yet gotten
to where delayedResponse was set to false, it's default. That meant that the
value was never set, and the TLB could start waiting for a callback that would
never come. This change simply moves the assignment to above where control
can divert to translateInt().
2011-09-05 02:48:57 -07:00
Lisa Hsu
365966304e TLB: comments and a helpful warning.
Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why.  Add a little warn() to explain it a bit.  Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage().
2011-09-02 17:04:00 -07:00
Lisa Hsu
f6a2ef22ff Fix build for gcc-4.2 opt/fast
Even though the code is safe, compiler flags a warning here, which are treated as errors for fast/opt. I know it's redundant but it has no side effects and fixes the compile.
2011-09-01 15:25:54 -07:00
Lisa Hsu
ae12ae3023 Functional Accesses: Update states to support Broadcast/Snooping protocols.
In the current implementation of Functional Accesses, it's very hard to
implement broadcast or snooping protocols where the memory has no idea if it
has exclusive access to a cache block or not. Without this knowledge, making
sure the RW vs. RO permissions are right are next to impossible. So we add a
new state called Backing_Store to enable the conveyance that this is the backup
storage for a block, so that it can be written if it is the only possibly RW
block in the system, or written even if there is another RW block in the
system, without causing problems.

Also, a small change to actually set the m_name field for each Controller so
that debugging can be easier. Now you can access a controller's name just by
controller->getName().
2011-09-01 11:41:44 -07:00
Nilay Vaish
ebda5c14a5 SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.
2011-08-29 06:34:40 -05:00
Nilay Vaish
1bbca50491 Ruby: Remove some unused code 2011-08-29 05:10:23 -05:00
Nilay Vaish
a08cc94936 Ruby: Eliminate modulo op for computing set size. 2011-08-26 12:27:58 -05:00
Ali Saidi
c9d5985b82 ARM: Mark some variables uncacheable until boot all CPUs are enabled.
There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).
2011-08-19 15:08:08 -05:00
Ali Saidi
c9c2d979b8 Mem: Put prefetcher notify call before packet is deleted. 2011-08-19 15:08:08 -05:00
Ali Saidi
2fd2b44b86 ARM: Add VExpress_E support with PCIe to gem5 2011-08-19 15:08:08 -05:00
Ali Saidi
d2a0a2ec22 ARM: Add support for Versatile Express boards 2011-08-19 15:08:08 -05:00
Ali Saidi
23755eb434 ARM: Make GIC function that should only be called by GIC protected. 2011-08-19 15:08:08 -05:00
Ali Saidi
243223ae63 IDE: Fix issues with new PIIX kernel driver and our model.
The driver can read the IDE config register as a 32 bit register since
some adapters use bit 18 as a disable channel bit. If the size isn't
set in a PRD it should be 64K according to the SPEC (and driver) not
128K.
2011-08-19 15:08:08 -05:00
Ali Saidi
b94f841969 ARM: Add support for DIV/SDIV instructions. 2011-08-19 15:08:07 -05:00
Ali Saidi
b6203360ef LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
This patch improves performance by as much as 10% on some spec benchmarks.
2011-08-19 15:08:07 -05:00
Geoffrey Blake
5f425b8bd1 Fix bugs due to interaction between SEV instructions and O3 pipeline
SEV instructions were originally implemented to cause asynchronous squashes
via the generateTCSquash() function in the O3 pipeline when updating the
SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system
that would lead to a pipeline either going inactive indefinitely or not being
able to commit squashed instructions. Fixed SEV instructions to behave like
interrupts and cause synchronous sqaushes inside the pipeline, eliminating
the race conditions. Also fixed up the semantics of the WFE instruction to
behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1
or unmasked interrupts are pending.
2011-08-19 15:08:07 -05:00
Mrinmoy Ghosh
d0e0485902 LSQ: Add some better dprintfs for storeset predictor. 2011-08-19 15:08:05 -05:00
Mrinmoy Ghosh
0db95030fc LSQ: Fix a few issues with the storeset predictor.
Two issues are fixed in this patch:
1. The load and store pc passed to the predictor are passed in reverse order.
2. The flag indicating that a barrier is inflight was never cleared when
   the barrier was squashed instead of committed. This made all load insts
   dependent on a non-existent barrier in-flight.
2011-08-19 15:08:05 -05:00
Thomas Grass
3f1ae35c6d Stats: Add a sparse histogram stat object. 2011-08-19 15:08:05 -05:00
Giacomo Gabrielli
676a530b77 O3: Squash the violator and younger instructions instead not all insts.
Change the way instructions are squashed on memory ordering violations
to squash the violator and younger instructions, not all instructions
that are younger than the instruction they violated (no reason to throw
away valid work).
2011-08-19 15:08:05 -05:00
Geoffrey Blake
f778c46b5e ARM: Add per-cpu local timers for ARM.
Cortex-A9 processors can have a local timer and watchdog counter. It
is enabled by default in Linux and up to this point we've had to disable
them since a model wasn't available. This change allows a default
MP ARM Linux configuration to boot.
2011-08-19 15:08:05 -05:00
Prakash Ramrakhani
efd91d2237 ARM: Add per-processor interrupt support to GIC. 2011-08-19 15:08:05 -05:00
Ali Saidi
9b356adf54 ARM: Fix a memory leak with the table walker. 2011-08-19 15:08:05 -05:00
Ali Saidi
6779bd3e5d Prefetcher: Fix some memory leaks with the prefetcher. 2011-08-19 15:08:05 -05:00
Ali Saidi
b3a058f220 ARM: quiet what can be a very noise CLCD controller. 2011-08-19 15:08:05 -05:00
Gabe Black
f2c89a01d1 InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively. 2011-08-16 02:47:15 -07:00
Gabe Black
78a4636a13 O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively. 2011-08-16 02:46:57 -07:00
Nilay Vaish
769c1844f0 Ruby: Initialize some variables. 2011-08-15 12:56:47 -05:00
Gabe Black
0e6dc00497 O3: When squashing, restore the macroop that should be used for fetching. 2011-08-14 17:41:34 -07:00
Gabe Black
ec204f003c O3: Add a pointer to the macroop for a microop in the dyninst. 2011-08-14 04:08:14 -07:00
Gabe Black
1b9de61a71 X86: Use IsSquashAfter if an instruction could affect fetch translation.
Control register operands are set up so that writing to them is serialize
after, serialize before, and non-speculative. These are probably overboard,
but they should usually be safe. Unfortunately there are times when even these
aren't enough. If an instruction modifies state that affects fetch, later
serialized instructions which come after it might have already gone through
fetch and decode by the time it commits. These instructions may have been
translated incorrectly or interpretted incorrectly and need to be destroyed.
This change modifies instructions which will or may have this behavior so that
they use the IsSquashAfter flag when necessary.
2011-08-13 23:03:11 -07:00
Gabe Black
e0043f8dbe O3: At the end of an instruction, force fetchAddr to something sensible.
It's possible (though until now very unlikely) for fetchAddr to get out of
sync with the actual PC of the current instruction. This change forcefull
resets fetchAddr at the end of every instruction.
2011-08-13 13:36:37 -07:00
Gabe Black
96df6bedb7 O3: Stop using the current macroop no matter why you're leaving it.
Until now, the only reason a macroop would be left was because it ended at a
microop marked as the last microop. In O3 with branch prediction, it's
possible for the branch predictor to have entries which originally came from
different instructions which happened to have the same RIP. This could
theoretically happen in many ways, but it was encountered specifically when
different programs in different address spaces ran one after the other in
X86_FS.

What would happen in that case was that the macroop would continue to be
looped over and microops fetched from it until it reached the last microop
even though the macropc had moved out from under it. If things lined up
properly, this could mean that the end bytes of an instruction actually fell
into the instruction sized block of memory after the one in the predecoder.
The fetch loop implicitly assumes that the last instruction sized chunk of
memory processed was the last one needed for the instruction it just finished
executing. It would then tell the predecoder to move to an offset within the
bytes it was given that is larger than those bytes, and that would trip an
assert in the x86 predecoder.

This change fixes this problem by making fetch stop processing the current
macroop if the address it should be fetching from changed when the PC is
updated. That happens when the last microop was reached because the instruction
handled it properly, and it also catches the case where the branch predictor
makes fetch do a macro level branch when it shouldn't.

The check of isLastMicroop is retained because otherwise, a macroop that
branches back to itself would act like a single, long macroop instead of
multiple instances of the same microop. There may be situations (which may
turn out to be purely hypothetical) where that matters.

This also fixes a relatively minor issue where the curMacroop variable would
be set to NULL immediately after seeing that a microop was the last one before
curMacroop was used to build the dyninst. The traceData structure would have a
NULL pointer to the macroop for that microop.
2011-08-09 11:30:43 -07:00
Gabe Black
3989f41261 O3: When waiting to handle an interrupt, let everything drain out.
Before this change, the commit stage would wait until the ROB and store queue
were empty before recognizing an interrupt. The fetch stage would stop
generating instructions at an appropriate point, so commit would then wait
until a valid time to interrupt the instruction stream. Instructions might be
in flight after fetch but not the in the ROB or store queue (in rename, for
instance), so this change makes commit wait until all in flight instructions
are finished.
2011-08-09 03:37:43 -07:00
Nilay Vaish
821dfc1289 BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
2011-08-08 10:50:13 -05:00
Gabe Black
5c0e6e6092 O3: Get rid of the unused addToRemoveList function. 2011-08-07 15:41:10 -07:00
Gabe Black
a9b7931156 O3: Let squashed and deferred instructions issue.
Let squahsed and deferred instructions issue so they don't accumulate and clog
up the CPU.
2011-08-07 15:41:07 -07:00
Ali Saidi
4d83b8a799 O3: Fix uninitialized variable in the tournament branch predictor. 2011-08-07 09:21:49 -07:00
Gabe Black
16882b0483 Translation: Use a pointer type as the template argument.
This allows regular pointers and reference counted pointers without having to
use any shim structures or other tricks.
2011-08-07 09:21:48 -07:00
Nilay Vaish
720c0be620 Ruby: Remove files and includes not in use 2011-08-03 18:25:30 -05:00
Gabe Black
6230668f5e O3: Get rid of the raw ExtMachInst constructor on DynInsts.
This constructor assumes that the ExtMachInst can be decoded directly into a
StaticInst that's useful to execute. With the advent of microcoded
instructions that's no longer true.
2011-08-02 11:51:16 -07:00
Gabe Black
1c68c32cc9 Scons: Make some Action objects fit the abreviated output format. 2011-08-02 03:22:11 -07:00
Nilay Vaish
1b49c56679 Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
2011-08-02 00:10:08 -05:00
Gabe Black
206c2e9a0e O3: Implement memory mapped IPRs for O3. 2011-07-31 19:21:17 -07:00
Gabe Black
a42c6ae48d O3: Fix corner case squashing into the microcode ROM.
When fetching from the microcode ROM, if the PC is set so that it isn't in the
cache block that's been fetched the CPU will get stuck. The fetch stage
notices that it's in the ROM so it doesn't try to fetch from the current PC.
It then later notices that it's outside of the current cache block so it skips
generating instructions expecting to continue once the right bytes have been
fetched. This change lets the fetch stage attempt to generate instructions,
and only checks if the bytes it's going to use are valid if it's really going
to use them.
2011-07-30 23:22:53 -07:00
Nilay Vaish
b4152e250d SLICC: Put functions of a controller in its .cc file
Currently, functions associated with a controller go into separate files.
This patch puts all the functions in the controller's .cc file. This should
hopefully take away some time from compilation.
2011-07-27 20:20:53 -05:00
Ali Saidi
147095cb08 Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
Prefetch requests issued from the L2 or below wouldn't check if valid data is
present higher in the system. If a prefetch into the L2 occured at the same
time as writeback from a higher-level cache the dirty data could be replaced
in by unmodified data in memory.
2011-07-15 11:53:35 -05:00
Giacomo Gabrielli
69ef57fd0f O3: Create a pipeline activity viewer for the O3 CPU model.
Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
2011-07-15 11:53:35 -05:00
Wade Walker
8870a5820a ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
2011-07-15 11:53:34 -05:00
Wade Walker
e6672d1f29 ARM: Add two unimplemented miscellaneous registers.
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
2011-07-15 11:53:34 -05:00
Nilay Vaish
dbde1502cd X86: implements copyRegs() function
This patch implements the copyRegs() function for the x86 architecture.
The patch assumes that no side effects other than TLB invalidation need
to be considered while copying the registers. This may not hold true in
future.
2011-07-11 16:52:52 -05:00
Gabe Black
a7dcd19fa0 ISA: Get rid of the unused mem_acc_type template parameter. 2011-07-11 04:47:06 -07:00
Mrinmoy Ghosh
3396fd9e84 Branch predictor: Fixes the tournament branch predictor.
Branch predictor could not predict a branch in a nested loop because:
 1. The global history was not updated after a mispredict squash.
 2. The global history was updated in the fetch stage. The choice predictors
    that were updated  used the changed global history. This is incorrect, as
    it incorporates the state of global history after the branch in
    encountered. Fixed update to choice predictor using the global history
    state before the branch happened.
 3. The global predictor table was also updated using the global history state
    before the branch happened as above.

Additionally, parameters to initialize ctr and history size were reversed.
2011-07-10 12:56:08 -05:00
Geoffrey Blake
c7e7b89058 O3: Fix up pipelining icache accesses in fetch stage to function properly
Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to
icache to work with recent changes to main repository.
Also added in ability for fetch stage to delay issuing the fault carrying
nop when a pipeline fetch causes a fault and no fetch bandwidth is available
until the next cycle.
2011-07-10 12:56:08 -05:00
Ali Saidi
f8538f7456 IO: Handle case where ISA Fake device is being used as a fake memory. 2011-07-10 12:56:08 -05:00
Ali Saidi
60579e8d74 O3: Make sure fetch doesn't go off into the weeds during speculation. 2011-07-10 12:56:08 -05:00
Ali Saidi
9751a1d3e7 Config: Add support for a Self.all proxy object 2011-07-10 12:56:08 -05:00
Daniel Johnson
83f91db2cc ARM: Fix mp interrupt bug in GIC.
Missing "!" made multiprocessor interrupts operate incorrectly.
2011-07-10 12:56:08 -05:00
Korey Sewell
678376f0ba alpha:hwrei:rollback for o3
change hwrei back to being a non-control instruction so O3-FS mode will work
add squash in inorder that will catch a hwrei (or any other genric instruction)
that isnt a control inst but changes the PC. Additional testing still needs to be done
for inorder-FS mode but this change will free O3 development back up in the interim
2011-07-07 21:32:49 -04:00
Brad Beckmann
255f82a783 ruby: added generic dma machine 2011-07-06 18:45:15 -07:00
Brad Beckmann
4f83390781 MOESI_hammer: Fixed uniprocessor DMA bug 2011-07-06 18:44:42 -07:00
Nathan Binkert
da1eaaca0e slicc: add a protocol statement and an include statement
All protocols must specify their name
The include statement allows any file to include another file.
2011-07-05 18:30:05 -07:00
Nathan Binkert
831e9b3b7a slicc: cleanup slicc code and make it less verbose 2011-07-05 18:30:05 -07:00
Nathan Binkert
3d252f8e5f grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently.  This makes implementing an include statement as part
of a grammar possible.
2011-07-05 18:30:04 -07:00
Gabe Black
87b657278d ISAs: Streamline some spots where Mem is used in the ISA descriptions. 2011-07-05 16:52:57 -07:00
Gabe Black
63a934d152 ISA parser: Define operand types with a ctype directly. 2011-07-05 16:52:15 -07:00
Gabe Black
f16179eb21 ISA parser: Simplify operand type handling.
This change simplifies the code surrounding operand type handling and makes it
depend only on the ctype that goes with each operand type. Future changes will
allow defining operand types by their ctypes directly, convert the ISAs over
to that style of definition, and then remove support for the old style. These
changes are to make it easier to use non-builtin types like classes or
structures as the type for operands.
2011-07-05 16:48:18 -07:00
Nilay Vaish
9b85b4b19a Merged with Gabe's recent changes. 2011-07-03 11:38:25 -05:00
Nilay Vaish
5e0851d554 Network_test: Conform it with functional access changes in Ruby
Addition of functional access support to Ruby necessitated some changes to
the way coherence protocols are written. I had forgotten to update the
Network_test protocol. This patch makes those updates.
2011-07-03 11:33:46 -05:00
Gabe Black
3a1428365a ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
2011-07-02 22:35:04 -07:00
Gabe Black
2e7426664a ExecContext: Get rid of the now unused read/write templated functions. 2011-07-02 22:34:58 -07:00
Gabe Black
aade13769f ISA: Use readBytes/writeBytes for all instruction level memory operations. 2011-07-02 22:34:29 -07:00
Gabe Black
2f72d6a1f4 X86: Fix store microops so they don't drop faults in timing mode.
If a fault was returned by the CPU when a store initiated it's write, the
store instruction would ignore the fault. This change fixes that.
2011-07-02 22:31:22 -07:00
Nilay Vaish
45b411fc5f Ruby: Commit files missing from previous commit
The previous commit on functional access support in Ruby did not have
some of the files required. This patch adds those files to the repository.
2011-07-01 16:29:33 -05:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
c86f849d5a Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
2011-06-30 19:49:26 -05:00
Nilay Vaish
f4cfd65d29 arch: print next upc correctly
The patch corrects the print statement which prints the current and
the next pc. Instead of the next upc, the next pc was being printed.
2011-06-28 18:27:38 -05:00
Joel Hestness
d50aec8d9a Ruby: remove unused functions in CacheMemory: get/setMemoryValue 2011-06-24 15:47:35 -05:00
Deyaun Guo
5aaddc129e mips: fix nmsub and nmadd definitions
the -/+ signs were flipped for nmsub_s, nmsub_d, and nmadd_d
2011-06-22 23:35:21 -04:00
Gabe Black
efb9f7c2ae X86: Eliminate an unused argument for building store microops. 2011-06-21 19:28:14 -07:00
Gabe Black
affad29932 InOder: Fix a compile error. 2011-06-20 02:29:14 -07:00
Korey Sewell
477e7039b3 inorder: clear reg. dep entry after removing from list
this will safeguard future code from trying to remove
from the list twice. That code wouldnt break but would
waste time.
2011-06-19 21:43:42 -04:00
Korey Sewell
b963b339b9 inorder: se: squash after syscalls 2011-06-19 21:43:42 -04:00
Korey Sewell
eedd04e894 inorder: cleanup dprintfs in cache unit 2011-06-19 21:43:42 -04:00
Korey Sewell
078f914e69 inorder: SE mode TLB faults
handle them like we do in FS mode, by blocking the TLB until the fault
is handled by the fault->invoke()
2011-06-19 21:43:42 -04:00
Korey Sewell
3cb23bd3a2 inorder:tracing: fix fault tracing bug 2011-06-19 21:43:42 -04:00
Korey Sewell
fe3a2aa4a3 inorder: se compile fixes 2011-06-19 21:43:42 -04:00
Korey Sewell
e572c01120 inorder: add necessary debug flag header files 2011-06-19 21:43:41 -04:00
Korey Sewell
59686795e3 mips: mark unaligned access flag as true 2011-06-19 21:43:41 -04:00
Korey Sewell
91a88ae8ce inorder: clear fetchbuffer on traps
implement clearfetchbufferfunction
extend predecoder to use multiple threads and clear those on trap
2011-06-19 21:43:41 -04:00
Korey Sewell
2dae0e8735 inorder: use separate float-reg bits function in dyninst
this will make sure we get the correct view of a FP register
2011-06-19 21:43:41 -04:00
Korey Sewell
8c0def8d03 inorder: use trapPending flag to manage traps 2011-06-19 21:43:41 -04:00
Korey Sewell
5ef0b7a9db inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
2011-06-19 21:43:41 -04:00
Korey Sewell
716e447da8 inorder: handle serializing instructions
including IPR accesses and store-conditionals. These class of instructions will not
execute correctly in a superscalar machine
2011-06-19 21:43:41 -04:00
Korey Sewell
83a0fd24f7 alpha: fix warn_once for prefetches 2011-06-19 21:43:40 -04:00
Korey Sewell
33a6020f2e alpha: naming for dtb faults
Just "dfault" gets confusing while debugging. Why not
differentiate whether it's an access violation or page
fault
2011-06-19 21:43:40 -04:00