Commit graph

40 commits

Author SHA1 Message Date
Nilay Vaish
c47001de8c stats: x86: updates due to patch on vex 2015-07-18 15:07:35 -05:00
Andreas Sandberg
a0cbf55411 stats: Update pc-switcheroo stats
The pc-switcheroo test cases has slightly different timing after
decoupling draining from the SimObject hierarchy. This is expected
since objects aren't drained in the exact same order as before.
2015-07-07 09:51:05 +01:00
Andreas Hansson
25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00
Andreas Hansson
80cd107e51 stats: Update stats to reflect cache changes 2015-05-05 03:22:39 -04:00
Nilay Vaish
42fe2df354 stats: x86: updates due to change in div latency 2015-04-29 22:35:23 -05:00
Steve Reinhardt
0cf36d9409 stats: update for previous changeset
Very small differences in IQ-specific O3 stats.
2015-04-22 20:22:29 -07:00
Nilay Vaish
99fb8f8140 stats: changes to due to recent set of patches 2015-03-09 09:39:09 -05:00
Andreas Hansson
8909843a76 stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 05:04:20 -05:00
Andreas Hansson
fc8cb1fa76 stats: Update stats to reflect x86 table walker changes 2015-01-22 05:00:57 -05:00
Nilay Vaish
e76442e203 stats: changes due to recent changesets. 2015-01-10 18:06:43 -06:00
Gabe Black
d0284544ec stats: x86: Update stats for the CPUID change. 2015-01-07 00:31:09 -08:00
Andreas Hansson
df8df4fd0a stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
2014-12-23 09:31:20 -05:00
Andreas Hansson
6489598fb4 stats: Bump stats for fixes, mostly TLB and WriteInvalidate 2014-12-02 06:08:25 -05:00
Andreas Hansson
b0aa5a326d stats: Bump stats after static analysis fixes
Fixing up the uninitialised values changes two of the x86 Linux boot
regressions slightly.
2014-11-24 09:03:39 -05:00
Gabe Black
2d2a5aa410 x86: Update stats for the new Linux delay port. 2014-11-21 17:22:19 -08:00
Gabe Black
994c44035d x86: Update the stats for the x86 FS o3 boot test. 2014-11-17 00:16:36 -08:00
Ali Saidi
93c0307d41 tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-29 23:18:29 -05:00
Nilay Vaish
1efe42fa97 stats: updates due to changes to x86, stale configs. 2014-10-11 16:18:51 -05:00
Andreas Hansson
0746e92cd3 stats: Add DRAM power statistics to reference output 2014-10-09 17:52:13 -04:00
Andreas Hansson
c4e91289ae stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
2014-09-20 17:18:53 -04:00
Andreas Hansson
a217eba078 stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
2014-09-03 07:42:59 -04:00
Steve Reinhardt
5b08e211ab stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM.  At the other extreme, X86 70.twolf is 0.8%
slower.
2014-06-22 14:33:09 -07:00
Nilay Vaish
2a8088f5ae stats: changes due to recent o3 patch. 2014-05-24 21:30:46 -05:00
Steve Reinhardt
72403cb595 tests: update t1000 & pc-switcheroo-full stats
committed reference config.json files too
2014-05-12 17:22:17 -04:00
Andreas Hansson
57e5401d95 stats: Bump stats for the fixes, and mostly DRAM controller changes 2014-05-09 18:58:50 -04:00
Andreas Hansson
0c75581d03 stats: updates for pc-switcheroo-full due to o3 smt fix 2014-04-22 03:12:15 -04:00
Nilay Vaish
3bc5cfcc03 stats: updates due to o3 smt fix
+ changes to one ruby regression config.ini file.
2014-04-19 09:16:14 -05:00
Andreas Hansson
8b4b1dcb86 stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
2014-03-23 11:12:19 -04:00
Nilay Vaish
5abbb84f02 stats: updates due to branch predictor warming 2014-02-16 11:40:34 -06:00
Ali Saidi
f3585c841e stats: update stats for cache occupancy and clock domain changes 2014-01-24 15:29:33 -06:00
Nilay Vaish
2823982a3c stats: updates due to changes to ticksToCycles() 2013-11-26 17:05:25 -06:00
Andreas Hansson
ccfdc533b9 stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
2013-11-01 11:56:34 -04:00
Steve Reinhardt
10e6450120 test: update stats
Update stats for recent changes.  Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
2013-10-16 10:44:12 -04:00
Andreas Sandberg
0438bf9389 stats: Update x86 stats after x87 fixes
The updates to the x87 caused the stats for several regressions to
change. This was mainly caused by the addition of a working 32-bit and
80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
Andreas Hansson
b63631536d stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.
2013-08-19 03:52:36 -04:00
Andreas Hansson
5a15909bac stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
2013-06-27 05:49:51 -04:00
Andreas Hansson
beee57070a stats: Bump x86 stats
This patch bumps the x86 stats to reflect the recent fixes.
2013-06-24 14:17:22 -04:00
Andreas Hansson
74553c7d3f stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00
Nilay Vaish
af2e83c7f1 x86, regressions: updates stats
This is due to op class, function call, walker patches.
2013-05-21 11:41:27 -05:00
Nilay Vaish
c2d799c6b0 x86: regressions: add switcher full test 2013-04-23 00:03:09 -05:00