|
|
|
|
@ -1,84 +1,84 @@
|
|
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
sim_seconds 5.112156 # Number of seconds simulated
|
|
|
|
|
sim_ticks 5112155738500 # Number of ticks simulated
|
|
|
|
|
final_tick 5112155738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
|
|
|
sim_seconds 5.112152 # Number of seconds simulated
|
|
|
|
|
sim_ticks 5112152263500 # Number of ticks simulated
|
|
|
|
|
final_tick 5112152263500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
|
|
|
host_inst_rate 1511003 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_op_rate 3093560 # Simulator op (including micro ops) rate (op/s)
|
|
|
|
|
host_tick_rate 38615908446 # Simulator tick rate (ticks/s)
|
|
|
|
|
host_mem_usage 595640 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 132.38 # Real time elapsed on the host
|
|
|
|
|
sim_insts 200033669 # Number of instructions simulated
|
|
|
|
|
sim_ops 409539941 # Number of ops (including micro ops) simulated
|
|
|
|
|
host_inst_rate 1496341 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_op_rate 3063337 # Simulator op (including micro ops) rate (op/s)
|
|
|
|
|
host_tick_rate 38234881791 # Simulator tick rate (ticks/s)
|
|
|
|
|
host_mem_usage 596704 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 133.70 # Real time elapsed on the host
|
|
|
|
|
sim_insts 200066624 # Number of instructions simulated
|
|
|
|
|
sim_ops 409580050 # Number of ops (including micro ops) simulated
|
|
|
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
|
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
|
|
|
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_read::cpu.inst 852224 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_read::cpu.data 10636736 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_read::cpu.inst 854656 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_read::cpu.data 10616192 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_read::total 11517696 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read::cpu.inst 852224 # Number of instructions bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read::total 852224 # Number of instructions bytes read from this memory
|
|
|
|
|
system.physmem.bytes_written::writebacks 9281152 # Number of bytes written to this memory
|
|
|
|
|
system.physmem.bytes_written::total 9281152 # Number of bytes written to this memory
|
|
|
|
|
system.physmem.bytes_read::total 11499584 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read::cpu.inst 854656 # Number of instructions bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read::total 854656 # Number of instructions bytes read from this memory
|
|
|
|
|
system.physmem.bytes_written::writebacks 9265728 # Number of bytes written to this memory
|
|
|
|
|
system.physmem.bytes_written::total 9265728 # Number of bytes written to this memory
|
|
|
|
|
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::cpu.inst 13316 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::cpu.data 166199 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::cpu.inst 13354 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::cpu.data 165878 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::total 179964 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_writes::writebacks 145018 # Number of write requests responded to by this memory
|
|
|
|
|
system.physmem.num_writes::total 145018 # Number of write requests responded to by this memory
|
|
|
|
|
system.physmem.num_reads::total 179681 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.num_writes::writebacks 144777 # Number of write requests responded to by this memory
|
|
|
|
|
system.physmem.num_writes::total 144777 # Number of write requests responded to by this memory
|
|
|
|
|
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::cpu.inst 166705 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::cpu.data 2080675 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::cpu.inst 167181 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::cpu.data 2076658 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::total 2253002 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read::cpu.inst 166705 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read::total 166705 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_write::writebacks 1815507 # Write bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_write::total 1815507 # Write bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::writebacks 1815507 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::total 2249460 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read::cpu.inst 167181 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read::total 167181 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_write::writebacks 1812491 # Write bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_write::total 1812491 # Write bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::writebacks 1812491 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::cpu.inst 166705 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::cpu.data 2080675 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::cpu.inst 167181 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::cpu.data 2076658 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::total 4068508 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::total 4061951 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
|
|
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
|
|
|
|
system.cpu.numCycles 10224315447 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.numCycles 10224308491 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.committedInsts 200033669 # Number of instructions committed
|
|
|
|
|
system.cpu.committedOps 409539941 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.num_int_alu_accesses 374549395 # Number of integer alu accesses
|
|
|
|
|
system.cpu.committedInsts 200066624 # Number of instructions committed
|
|
|
|
|
system.cpu.committedOps 409580050 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.num_int_alu_accesses 374583182 # Number of integer alu accesses
|
|
|
|
|
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
|
|
|
system.cpu.num_func_calls 2308749 # number of times a function call or return occured
|
|
|
|
|
system.cpu.num_conditional_control_insts 39994798 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu.num_int_insts 374549395 # number of integer instructions
|
|
|
|
|
system.cpu.num_func_calls 2308871 # number of times a function call or return occured
|
|
|
|
|
system.cpu.num_conditional_control_insts 40001057 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu.num_int_insts 374583182 # number of integer instructions
|
|
|
|
|
system.cpu.num_fp_insts 0 # number of float instructions
|
|
|
|
|
system.cpu.num_int_register_reads 682628451 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 323525110 # number of times the integer registers were written
|
|
|
|
|
system.cpu.num_int_register_reads 682688853 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 323557399 # number of times the integer registers were written
|
|
|
|
|
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
|
|
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
|
|
|
|
system.cpu.num_cc_register_reads 233820400 # number of times the CC registers were read
|
|
|
|
|
system.cpu.num_cc_register_writes 157313425 # number of times the CC registers were written
|
|
|
|
|
system.cpu.num_mem_refs 35680406 # number of memory refs
|
|
|
|
|
system.cpu.num_load_insts 27249300 # Number of load instructions
|
|
|
|
|
system.cpu.num_store_insts 8431106 # Number of store instructions
|
|
|
|
|
system.cpu.num_idle_cycles 9770368815.449127 # Number of idle cycles
|
|
|
|
|
system.cpu.num_busy_cycles 453946631.550873 # Number of busy cycles
|
|
|
|
|
system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.idle_fraction 0.955601 # Percentage of idle cycles
|
|
|
|
|
system.cpu.Branches 43145649 # Number of branches fetched
|
|
|
|
|
system.cpu.op_class::No_OpClass 175370 0.04% 0.04% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntAlu 373417675 91.18% 91.22% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntMult 144551 0.04% 91.26% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntDiv 122974 0.03% 91.29% # Class of executed instruction
|
|
|
|
|
system.cpu.num_cc_register_reads 233837170 # number of times the CC registers were read
|
|
|
|
|
system.cpu.num_cc_register_writes 157316360 # number of times the CC registers were written
|
|
|
|
|
system.cpu.num_mem_refs 35666925 # number of memory refs
|
|
|
|
|
system.cpu.num_load_insts 27243229 # Number of load instructions
|
|
|
|
|
system.cpu.num_store_insts 8423696 # Number of store instructions
|
|
|
|
|
system.cpu.num_idle_cycles 9770324986.701103 # Number of idle cycles
|
|
|
|
|
system.cpu.num_busy_cycles 453983504.298896 # Number of busy cycles
|
|
|
|
|
system.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.idle_fraction 0.955598 # Percentage of idle cycles
|
|
|
|
|
system.cpu.Branches 43152131 # Number of branches fetched
|
|
|
|
|
system.cpu.op_class::No_OpClass 172748 0.04% 0.04% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntAlu 373476362 91.18% 91.23% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntMult 144577 0.04% 91.26% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntDiv 123058 0.03% 91.29% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
|
|
|
|
|
@ -105,69 +105,69 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl
|
|
|
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::MemRead 27249300 6.65% 97.94% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::MemWrite 8431106 2.06% 100.00% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::MemRead 27240640 6.65% 97.94% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::MemWrite 8423696 2.06% 100.00% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::total 409540976 # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::total 409581081 # Class of executed instruction
|
|
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
|
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
|
system.cpu.dcache.tags.replacements 1623460 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 20193083 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 1623972 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 12.434379 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.replacements 1621913 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 20181070 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 1622425 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 12.438831 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.dcache.tags.tag_accesses 88892257 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 88892257 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 12028370 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 12028370 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8103548 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 8103548 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 58901 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::total 58901 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 20131918 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 20131918 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 20190819 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 20190819 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 906001 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 906001 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 317188 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 317188 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 403060 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::total 403060 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1223189 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 1223189 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1626249 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 1626249 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 12934371 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 12934371 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8420736 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 8420736 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 21355107 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 21355107 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 21817068 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 21817068 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070046 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.070046 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037667 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.037667 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872498 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872498 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.074540 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.074540 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.tags.tag_accesses 88836495 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 88836495 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 12023306 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 12023306 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8096585 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 8096585 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 58898 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::total 58898 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 20119891 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 20119891 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 20178789 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 20178789 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 905254 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 905254 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 316711 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 316711 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 402759 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::total 402759 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1221965 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 1221965 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1624724 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 1624724 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 12928560 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 12928560 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8413296 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 8413296 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 21341856 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 21341856 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 21803513 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 21803513 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070020 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.070020 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037644 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.037644 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872420 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872420 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.057257 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.057257 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.074517 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.074517 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
@ -176,49 +176,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks::writebacks 1536867 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 1536867 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::writebacks 1535795 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 1535795 # number of writebacks
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.013943 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.total_refs 12520 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.529067 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101318572500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013943 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313371 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313371 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.replacements 7755 # number of replacements
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014024 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.total_refs 12942 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.sampled_refs 7769 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.665851 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454103000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014024 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313376 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313376 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tag_accesses 53161 # Number of tag accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.data_accesses 53161 # Number of data accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12521 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 12521 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12521 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::total 12521 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12521 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::total 12521 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428108 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428108 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428108 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428108 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428108 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428108 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tag_accesses 52772 # Number of tag accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.data_accesses 52772 # Number of data accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12943 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 12943 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12943 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::total 12943 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12943 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::total 12943 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8962 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 8962 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8962 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::total 8962 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8962 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::total 8962 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21905 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21905 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21905 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 21905 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21905 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 21905 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409130 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409130 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409130 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409130 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409130 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409130 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
@ -227,50 +227,50 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
|
|
|
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2457 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::total 2457 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.icache.tags.replacements 791846 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 243645674 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 792358 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 307.494433 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.replacements 792213 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 510.662957 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 243675024 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 792725 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 307.389100 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.warmup_cycle 148913080500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.662957 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.icache.tags.tag_accesses 245230404 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 245230404 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 243645674 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 243645674 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 243645674 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 243645674 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 243645674 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 243645674 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 792365 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 792365 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 792365 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 792365 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 792365 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 792365 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 244438039 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 244438039 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 244438039 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 244438039 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 244438039 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 244438039 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.003242 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.003242 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.003242 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.tags.tag_accesses 245260488 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 245260488 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 243675024 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 243675024 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 243675024 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 243675024 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 243675024 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 243675024 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 792732 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 792732 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 792732 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 792732 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 792732 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 792732 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 244467756 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 244467756 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 244467756 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 244467756 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 244467756 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 244467756 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
@ -280,37 +280,36 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements
|
|
|
|
|
system.cpu.itb_walker_cache.tags.tagsinuse 3.026443 # Cycle average of tags in use
|
|
|
|
|
system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5102148365500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026443 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements
|
|
|
|
|
system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # Cycle average of tags in use
|
|
|
|
|
system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5102144858000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026546 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189159 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189159 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.tag_accesses 29024 # Number of tag accesses
|
|
|
|
|
system.cpu.itb_walker_cache.tags.data_accesses 29024 # Number of data accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7640 # number of ReadReq hits
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 7640 # number of ReadReq hits
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.itb_walker_cache.tags.tag_accesses 28899 # Number of tag accesses
|
|
|
|
|
system.cpu.itb_walker_cache.tags.data_accesses 28899 # Number of data accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7765 # number of ReadReq hits
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 7765 # number of ReadReq hits
|
|
|
|
|
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
|
|
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
|
|
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.itb_walker_cache.demand_hits::total 7642 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7642 # number of overall hits
|
|
|
|
|
system.cpu.itb_walker_cache.overall_hits::total 7642 # number of overall hits
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4580 # number of ReadReq misses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 4580 # number of ReadReq misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4580 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_misses::total 4580 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4580 # number of overall misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_misses::total 4580 # number of overall misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7767 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.itb_walker_cache.demand_hits::total 7767 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7767 # number of overall hits
|
|
|
|
|
system.cpu.itb_walker_cache.overall_hits::total 7767 # number of overall hits
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
@ -319,12 +318,12 @@ system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222
|
|
|
|
|
system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374795 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374795 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374734 # miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total 0.374734 # miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374734 # miss rate for overall accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total 0.374734 # miss rate for overall accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.364566 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.364566 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.364507 # miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total 0.364507 # miss rate for demand accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.364507 # miss rate for overall accesses
|
|
|
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total 0.364507 # miss rate for overall accesses
|
|
|
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
@ -333,115 +332,115 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan
|
|
|
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks
|
|
|
|
|
system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks
|
|
|
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 545 # number of writebacks
|
|
|
|
|
system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks
|
|
|
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.tags.replacements 106199 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 64825.456332 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 3461789 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 170310 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 20.326399 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.replacements 106219 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 64823.931621 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 3459892 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 170177 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 20.331138 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 51911.006068 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132276 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.288805 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.026704 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109660 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132289 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2455.813692 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873502 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.792375 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037999 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159058 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.989158 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20721 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39577 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 32245523 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 32245523 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 779035 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1276188 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 2065891 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1540463 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 1540463 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037473 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159285 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63958 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 32213022 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 32213022 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6661 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2896 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 779364 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1275206 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 2064127 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1538797 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 1538797 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 180020 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 180020 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 779035 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 1456208 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2245911 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 779035 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 1456208 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2245911 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 179775 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 179775 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6661 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 779364 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 1454981 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2243902 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6661 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 779364 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 1454981 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2243902 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 32232 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 134899 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 134899 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13355 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 32163 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 45524 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1807 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 1807 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 134650 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 134650 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 167131 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 180454 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 13355 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 166813 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 180174 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 167131 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 180454 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 792352 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308420 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 2111446 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1540463 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 1540463 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314919 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 314919 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 792352 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1623339 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2426365 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 792352 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1623339 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2426365 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.021575 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428361 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428361 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102955 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.074372 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102955 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.074372 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 13355 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 166813 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 180174 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6662 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2901 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 792719 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307369 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 2109651 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1538797 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 1538797 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314425 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 314425 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6662 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2901 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 792719 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1621794 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2424076 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6662 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2901 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 792719 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1621794 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2424076 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016847 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024601 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.021579 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987972 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987972 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428242 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428242 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016847 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.074327 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016847 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.074327 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
@ -450,46 +449,46 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.writebacks::writebacks 98351 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 98351 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::writebacks 98110 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 98110 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 15972684 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 15972684 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1540463 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 314924 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 314924 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584730 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531797 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 34148029 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50711360 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227719225 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 279553721 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 48008 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4020658 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.108192 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 15971499 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 15971499 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1538797 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 314430 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 314430 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585464 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32527803 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9455 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20381 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 34143103 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50734848 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227551993 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730816 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 279337657 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 48002 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4017293 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.011855 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.108231 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::3 3973030 98.82% 98.82% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::3 3969670 98.81% 98.81% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::4 47623 1.19% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::total 4020658 # Request fanout histogram
|
|
|
|
|
system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteReq 57692 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteResp 10972 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::total 4017293 # Request fanout histogram
|
|
|
|
|
system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteResp 11004 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::MessageReq 1696 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::MessageResp 1696 # Transaction distribution
|
|
|
|
|
@ -505,18 +504,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27940 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::total 20044316 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count::total 20142954 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
@ -529,48 +528,48 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13970 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::total 10028276 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iocache.tags.replacements 47573 # number of replacements
|
|
|
|
|
system.iocache.tags.tagsinuse 0.042450 # Cycle average of tags in use
|
|
|
|
|
system.iobus.pkt_size::total 13062828 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iocache.tags.replacements 47568 # number of replacements
|
|
|
|
|
system.iocache.tags.tagsinuse 0.042441 # Cycle average of tags in use
|
|
|
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
|
|
|
system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042450 # Average occupied blocks per requestor
|
|
|
|
|
system.iocache.tags.warmup_cycle 4994875215009 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor
|
|
|
|
|
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
|
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
|
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
|
|
|
system.iocache.tags.tag_accesses 428652 # Number of tag accesses
|
|
|
|
|
system.iocache.tags.data_accesses 428652 # Number of data accesses
|
|
|
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses
|
|
|
|
|
system.iocache.ReadReq_misses::total 908 # number of ReadReq misses
|
|
|
|
|
system.iocache.tags.tag_accesses 428607 # Number of tag accesses
|
|
|
|
|
system.iocache.tags.data_accesses 428607 # Number of data accesses
|
|
|
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
|
|
|
|
|
system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
|
|
|
|
|
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
|
|
|
|
|
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
|
|
|
|
|
system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 908 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 908 # number of overall misses
|
|
|
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 903 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 903 # number of overall misses
|
|
|
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
|
|
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
|
|
|
@ -590,49 +589,49 @@ system.iocache.cache_copies 0 # nu
|
|
|
|
|
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
|
|
|
|
system.iocache.writebacks::total 46667 # number of writebacks
|
|
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.membus.trans_dist::ReadReq 13903768 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 13903768 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteReq 13911 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteResp 13911 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::Writeback 145018 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadReq 13903764 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 13903764 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteReq 13943 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteResp 13943 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::Writeback 144777 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 134621 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 134616 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeReq 2545 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeResp 2093 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 134369 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 134364 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::MessageResp 1696 # Transaction distribution
|
|
|
|
|
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463319 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205751 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141923 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.iocache.mem_side::total 141923 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 28351066 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462529 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205089 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141913 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.iocache.mem_side::total 141913 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 28350394 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825408 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43250105 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034880 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::total 6034880 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size::total 49291769 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17791872 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43216633 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034560 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::total 6034560 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size::total 49257977 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
|
|
|
system.membus.snoop_fanout::samples 375347 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::samples 374838 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::1 375347 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::1 374838 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::total 375347 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::total 374838 # Request fanout histogram
|
|
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
|
|
|
|
|
Gabe Black