stats: x86: updates due to patch on vex
This commit is contained in:
Nilay Vaish
parent
0ef3dcc27b
commit
c47001de8c
File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 5.141168 # Nu
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sim_ticks 5141168437500 # Number of ticks simulated
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final_tick 5141168437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 561125 # Simulator instruction rate (inst/s)
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host_op_rate 1115525 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 11816760555 # Simulator tick rate (ticks/s)
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host_mem_usage 973408 # Number of bytes of host memory used
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host_seconds 435.07 # Real time elapsed on the host
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host_inst_rate 195369 # Simulator instruction rate (inst/s)
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host_op_rate 388397 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4114294038 # Simulator tick rate (ticks/s)
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host_mem_usage 1021404 # Number of bytes of host memory used
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host_seconds 1249.59 # Real time elapsed on the host
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sim_insts 244131065 # Number of instructions simulated
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sim_ops 485336254 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -133,9 +133,9 @@ system.physmem.writePktSize::3 0 # Wr
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 81462 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 89320 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::0 89319 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 4643 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 843 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 844 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 184 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
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@ -189,10 +189,10 @@ system.physmem.wrQLenPdf::20 4383 # Wh
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system.physmem.wrQLenPdf::21 4398 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5113 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 5221 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 6010 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5388 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5226 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4638 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 6008 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5387 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5227 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4640 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4893 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4936 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4337 # What write queue length does an incoming req see
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@ -229,20 +229,20 @@ system.physmem.wrQLenPdf::60 9 # Wh
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system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 41437 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 273.022082 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 164.972231 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 298.458037 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 16767 40.46% 40.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 10137 24.46% 64.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 4304 10.39% 75.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2528 6.10% 81.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::samples 41433 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 273.048440 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 164.990010 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 298.466349 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 16764 40.46% 40.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 10136 24.46% 64.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 4303 10.39% 75.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2529 6.10% 81.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1659 4.00% 85.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1139 2.75% 88.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 786 1.90% 90.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 657 1.59% 91.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 3460 8.35% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 41437 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 41433 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4254 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 22.404325 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 181.210886 # Reads before turning the bus around for writes
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@ -283,12 +283,12 @@ system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Wr
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system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4254 # Writes before turning the bus around for reads
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system.physmem.totQLat 1082395298 # Total ticks spent queuing
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system.physmem.totMemAccLat 2869457798 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totQLat 1082376548 # Total ticks spent queuing
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system.physmem.totMemAccLat 2869439048 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 476550000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 11356.58 # Average queueing delay per DRAM burst
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system.physmem.avgQLat 11356.38 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 30106.58 # Average memory access latency per DRAM burst
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system.physmem.avgMemAccLat 30106.38 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 1.01 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s
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@ -299,21 +299,21 @@ system.physmem.busUtilRead 0.01 # Da
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system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 9.18 # Average write queue length when enqueuing
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system.physmem.readRowHits 76601 # Number of row buffer hits during reads
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system.physmem.writeRowHits 58731 # Number of row buffer hits during writes
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system.physmem.readRowHits 76603 # Number of row buffer hits during reads
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system.physmem.writeRowHits 58733 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 80.37 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 72.10 # Row buffer hit rate for writes
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system.physmem.avgGap 29060364.94 # Average gap between requests
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system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 152477640 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 82953750 # Energy for precharge commands per rank (pJ)
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system.physmem_0.actEnergy 152447400 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 82937250 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 356538000 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 270228960 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 250406807040 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 95253378300 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 2241273732750 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 2587796116440 # Total energy per rank (pJ)
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system.physmem_0.averagePower 667.867379 # Core power per rank (mW)
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system.physmem_0.actBackEnergy 95253368040 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 2241273741750 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 2587796068440 # Total energy per rank (pJ)
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system.physmem_0.averagePower 667.867367 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 3687953773966 # Time in different power states
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system.physmem_0.memoryStateTime::REF 128019840000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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@ -324,14 +324,14 @@ system.physmem_1.preEnergy 87503625 # En
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system.physmem_1.readEnergy 386872200 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 257631840 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 250406807040 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 95644179990 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 2237947569750 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 2584891350525 # Total energy per rank (pJ)
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system.physmem_1.averagePower 667.974891 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 3687410747240 # Time in different power states
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system.physmem_1.actBackEnergy 95642577720 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 2237948975250 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 2584891153755 # Total energy per rank (pJ)
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system.physmem_1.averagePower 667.974840 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 3687413088990 # Time in different power states
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system.physmem_1.memoryStateTime::REF 128019840000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 18840857760 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 18838516010 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
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@ -459,17 +459,17 @@ system.cpu0.dcache.overall_misses::cpu1.data 297649
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system.cpu0.dcache.overall_misses::cpu2.data 1159923 # number of overall misses
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system.cpu0.dcache.overall_misses::total 2062841 # number of overall misses
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system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2308605500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12073568500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_latency::total 14382174000 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12073522500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_latency::total 14382128000 # number of ReadReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2733996493 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4762186878 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::total 7496183371 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4762162878 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_latency::total 7496159371 # number of WriteReq miss cycles
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system.cpu0.dcache.demand_miss_latency::cpu1.data 5042601993 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_latency::cpu2.data 16835755378 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_latency::total 21878357371 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_latency::cpu2.data 16835685378 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_latency::total 21878287371 # number of demand (read+write) miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu1.data 5042601993 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu2.data 16835755378 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_latency::total 21878357371 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_latency::cpu2.data 16835685378 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_latency::total 21878287371 # number of overall miss cycles
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 5034107 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::cpu1.data 2741577 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::cpu2.data 5078638 # number of ReadReq accesses(hits+misses)
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@ -511,17 +511,17 @@ system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063379
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system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136727 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::total 0.094912 # miss rate for overall accesses
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system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13908.518842 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14643.077097 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::total 10802.472326 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14643.021307 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::total 10802.437775 # average ReadReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40378.031207 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34712.346949 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::total 23035.198406 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34712.172010 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::total 23035.124656 # average WriteReq miss latency
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system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21577.705954 # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17505.989700 # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::total 13205.181172 # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17505.916913 # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::total 13205.138922 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16941.437710 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14514.545688 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::total 10605.934908 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14514.485339 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::total 10605.900974 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 198021 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_mshrs 23048 # number of cycles access was blocked
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@ -569,20 +569,20 @@ system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 189368
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system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 209170 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.overall_mshr_uncacheable_misses::total 398538 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2142200000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5924742500 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8066942500 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5924733500 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8066933500 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2581607993 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4076188379 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6657796372 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4076164379 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6657772372 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 949074500 # number of SoftPFReq MSHR miss cycles
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system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2819608000 # number of SoftPFReq MSHR miss cycles
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system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3768682500 # number of SoftPFReq MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4723807993 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10000930879 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_latency::total 14724738872 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10000897879 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_latency::total 14724705872 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5672882493 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12820538879 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::total 18493421372 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12820505879 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency::total 18493388372 # number of overall MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30610037000 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33210281500 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63820318500 # number of ReadReq MSHR uncacheable cycles
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@ -608,20 +608,20 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063034
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system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087132 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_miss_rate::total 0.047631 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12909.952150 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13489.666580 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13330.704465 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13489.646089 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13330.689592 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39030.706091 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38753.300239 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38860.396974 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38753.072065 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38860.256890 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14839.955280 # average SoftPFReq mshr miss latency
|
||||
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14474.596631 # average SoftPFReq mshr miss latency
|
||||
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14564.900232 # average SoftPFReq mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20354.485766 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18370.927552 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18963.790909 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18370.866933 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18963.748409 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19163.136607 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17344.131083 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17864.294512 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17344.086440 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17864.262635 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164538.245286 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162011.647080 # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163213.720165 # average ReadReq mshr uncacheable latency
|
||||
|
|
@ -632,11 +632,11 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164769.126780
|
|||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162777.138213 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163723.644922 # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.tags.replacements 878678 # number of replacements
|
||||
system.cpu0.icache.tags.replacements 878679 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 510.838296 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 128369667 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 879190 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 146.009016 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.total_refs 128369666 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 879191 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 146.008849 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 149037485500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 260.884696 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_blocks::cpu1.inst 143.250304 # Average occupied blocks per requestor
|
||||
|
|
@ -651,41 +651,41 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 148
|
|||
system.cpu0.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.icache.tags.tag_accesses 130155693 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 130155693 # Number of data accesses
|
||||
system.cpu0.icache.tags.tag_accesses 130155694 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 130155694 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 85680859 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 39485533 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu2.inst 3203275 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 128369667 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu2.inst 3203274 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 128369666 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 85680859 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::cpu1.inst 39485533 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::cpu2.inst 3203275 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::total 128369667 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::cpu2.inst 3203274 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::total 128369666 # number of demand (read+write) hits
|
||||
system.cpu0.icache.overall_hits::cpu0.inst 85680859 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::cpu1.inst 39485533 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::cpu2.inst 3203275 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::total 128369667 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::cpu2.inst 3203274 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::total 128369666 # number of overall hits
|
||||
system.cpu0.icache.ReadReq_misses::cpu0.inst 290083 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::cpu1.inst 179832 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::cpu2.inst 436910 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::total 906825 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::cpu2.inst 436911 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::total 906826 # number of ReadReq misses
|
||||
system.cpu0.icache.demand_misses::cpu0.inst 290083 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::cpu1.inst 179832 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::cpu2.inst 436910 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::total 906825 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::cpu2.inst 436911 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::total 906826 # number of demand (read+write) misses
|
||||
system.cpu0.icache.overall_misses::cpu0.inst 290083 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::cpu1.inst 179832 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::cpu2.inst 436910 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::total 906825 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::cpu2.inst 436911 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::total 906826 # number of overall misses
|
||||
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2559612500 # number of ReadReq miss cycles
|
||||
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6034776488 # number of ReadReq miss cycles
|
||||
system.cpu0.icache.ReadReq_miss_latency::total 8594388988 # number of ReadReq miss cycles
|
||||
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6034803488 # number of ReadReq miss cycles
|
||||
system.cpu0.icache.ReadReq_miss_latency::total 8594415988 # number of ReadReq miss cycles
|
||||
system.cpu0.icache.demand_miss_latency::cpu1.inst 2559612500 # number of demand (read+write) miss cycles
|
||||
system.cpu0.icache.demand_miss_latency::cpu2.inst 6034776488 # number of demand (read+write) miss cycles
|
||||
system.cpu0.icache.demand_miss_latency::total 8594388988 # number of demand (read+write) miss cycles
|
||||
system.cpu0.icache.demand_miss_latency::cpu2.inst 6034803488 # number of demand (read+write) miss cycles
|
||||
system.cpu0.icache.demand_miss_latency::total 8594415988 # number of demand (read+write) miss cycles
|
||||
system.cpu0.icache.overall_miss_latency::cpu1.inst 2559612500 # number of overall miss cycles
|
||||
system.cpu0.icache.overall_miss_latency::cpu2.inst 6034776488 # number of overall miss cycles
|
||||
system.cpu0.icache.overall_miss_latency::total 8594388988 # number of overall miss cycles
|
||||
system.cpu0.icache.overall_miss_latency::cpu2.inst 6034803488 # number of overall miss cycles
|
||||
system.cpu0.icache.overall_miss_latency::total 8594415988 # number of overall miss cycles
|
||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 85970942 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::cpu1.inst 39665365 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3640185 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -711,14 +711,14 @@ system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004534
|
|||
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120024 # miss rate for overall accesses
|
||||
system.cpu0.icache.overall_miss_rate::total 0.007015 # miss rate for overall accesses
|
||||
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.353908 # average ReadReq miss latency
|
||||
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.401840 # average ReadReq miss latency
|
||||
system.cpu0.icache.ReadReq_avg_miss_latency::total 9477.450432 # average ReadReq miss latency
|
||||
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.432024 # average ReadReq miss latency
|
||||
system.cpu0.icache.ReadReq_avg_miss_latency::total 9477.469755 # average ReadReq miss latency
|
||||
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14233.353908 # average overall miss latency
|
||||
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.401840 # average overall miss latency
|
||||
system.cpu0.icache.demand_avg_miss_latency::total 9477.450432 # average overall miss latency
|
||||
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.432024 # average overall miss latency
|
||||
system.cpu0.icache.demand_avg_miss_latency::total 9477.469755 # average overall miss latency
|
||||
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14233.353908 # average overall miss latency
|
||||
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.401840 # average overall miss latency
|
||||
system.cpu0.icache.overall_avg_miss_latency::total 9477.450432 # average overall miss latency
|
||||
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.432024 # average overall miss latency
|
||||
system.cpu0.icache.overall_avg_miss_latency::total 9477.469755 # average overall miss latency
|
||||
system.cpu0.icache.blocked_cycles::no_mshrs 5682 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_mshrs 315 # number of cycles access was blocked
|
||||
|
|
@ -734,41 +734,41 @@ system.cpu0.icache.demand_mshr_hits::total 27624 #
|
|||
system.cpu0.icache.overall_mshr_hits::cpu2.inst 27624 # number of overall MSHR hits
|
||||
system.cpu0.icache.overall_mshr_hits::total 27624 # number of overall MSHR hits
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 179832 # number of ReadReq MSHR misses
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 409286 # number of ReadReq MSHR misses
|
||||
system.cpu0.icache.ReadReq_mshr_misses::total 589118 # number of ReadReq MSHR misses
|
||||
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 409287 # number of ReadReq MSHR misses
|
||||
system.cpu0.icache.ReadReq_mshr_misses::total 589119 # number of ReadReq MSHR misses
|
||||
system.cpu0.icache.demand_mshr_misses::cpu1.inst 179832 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.icache.demand_mshr_misses::cpu2.inst 409286 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.icache.demand_mshr_misses::total 589118 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.icache.demand_mshr_misses::cpu2.inst 409287 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.icache.demand_mshr_misses::total 589119 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.icache.overall_mshr_misses::cpu1.inst 179832 # number of overall MSHR misses
|
||||
system.cpu0.icache.overall_mshr_misses::cpu2.inst 409286 # number of overall MSHR misses
|
||||
system.cpu0.icache.overall_mshr_misses::total 589118 # number of overall MSHR misses
|
||||
system.cpu0.icache.overall_mshr_misses::cpu2.inst 409287 # number of overall MSHR misses
|
||||
system.cpu0.icache.overall_mshr_misses::total 589119 # number of overall MSHR misses
|
||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2379780500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5367725488 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.icache.ReadReq_mshr_miss_latency::total 7747505988 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5367751488 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.icache.ReadReq_mshr_miss_latency::total 7747531988 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2379780500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5367725488 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.icache.demand_mshr_miss_latency::total 7747505988 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5367751488 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.icache.demand_mshr_miss_latency::total 7747531988 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2379780500 # number of overall MSHR miss cycles
|
||||
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5367725488 # number of overall MSHR miss cycles
|
||||
system.cpu0.icache.overall_mshr_miss_latency::total 7747505988 # number of overall MSHR miss cycles
|
||||
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5367751488 # number of overall MSHR miss cycles
|
||||
system.cpu0.icache.overall_mshr_miss_latency::total 7747531988 # number of overall MSHR miss cycles
|
||||
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004534 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.112435 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.112436 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004557 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004534 # mshr miss rate for demand accesses
|
||||
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.112435 # mshr miss rate for demand accesses
|
||||
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.112436 # mshr miss rate for demand accesses
|
||||
system.cpu0.icache.demand_mshr_miss_rate::total 0.004557 # mshr miss rate for demand accesses
|
||||
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004534 # mshr miss rate for overall accesses
|
||||
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.112435 # mshr miss rate for overall accesses
|
||||
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.112436 # mshr miss rate for overall accesses
|
||||
system.cpu0.icache.overall_mshr_miss_rate::total 0.004557 # mshr miss rate for overall accesses
|
||||
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13233.353908 # average ReadReq mshr miss latency
|
||||
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13114.852421 # average ReadReq mshr miss latency
|
||||
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13151.025750 # average ReadReq mshr miss latency
|
||||
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13114.883903 # average ReadReq mshr miss latency
|
||||
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13151.047561 # average ReadReq mshr miss latency
|
||||
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13233.353908 # average overall mshr miss latency
|
||||
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13114.852421 # average overall mshr miss latency
|
||||
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13151.025750 # average overall mshr miss latency
|
||||
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13114.883903 # average overall mshr miss latency
|
||||
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13151.047561 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13233.353908 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13114.852421 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13151.025750 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13114.883903 # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13151.047561 # average overall mshr miss latency
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.numCycles 2607160707 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
@ -832,23 +832,23 @@ system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Cl
|
|||
system.cpu1.op_class::total 69696027 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu2.branchPred.lookups 29601975 # Number of BP lookups
|
||||
system.cpu2.branchPred.condPredicted 29601975 # Number of conditional branches predicted
|
||||
system.cpu2.branchPred.lookups 29601973 # Number of BP lookups
|
||||
system.cpu2.branchPred.condPredicted 29601973 # Number of conditional branches predicted
|
||||
system.cpu2.branchPred.condIncorrect 343203 # Number of conditional branches incorrect
|
||||
system.cpu2.branchPred.BTBLookups 26791839 # Number of BTB lookups
|
||||
system.cpu2.branchPred.BTBHits 26086008 # Number of BTB hits
|
||||
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu2.branchPred.BTBHitPct 97.365500 # BTB Hit Percentage
|
||||
system.cpu2.branchPred.usedRAS 612616 # Number of times the RAS was used to get a target.
|
||||
system.cpu2.branchPred.usedRAS 612615 # Number of times the RAS was used to get a target.
|
||||
system.cpu2.branchPred.RASInCorrect 69103 # Number of incorrect RAS predictions.
|
||||
system.cpu2.numCycles 155854675 # number of cpu cycles simulated
|
||||
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu2.fetch.icacheStallCycles 11239571 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu2.fetch.Insts 145909604 # Number of instructions fetch has processed
|
||||
system.cpu2.fetch.Branches 29601975 # Number of branches that fetch encountered
|
||||
system.cpu2.fetch.predictedBranches 26698624 # Number of branches that fetch has predicted taken
|
||||
system.cpu2.fetch.Cycles 143043306 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu2.fetch.icacheStallCycles 11239570 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu2.fetch.Insts 145909603 # Number of instructions fetch has processed
|
||||
system.cpu2.fetch.Branches 29601973 # Number of branches that fetch encountered
|
||||
system.cpu2.fetch.predictedBranches 26698623 # Number of branches that fetch has predicted taken
|
||||
system.cpu2.fetch.Cycles 143043279 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu2.fetch.SquashCycles 717621 # Number of cycles fetch has spent squashing
|
||||
system.cpu2.fetch.TlbCycles 104333 # Number of cycles fetch has spent waiting for tlb
|
||||
system.cpu2.fetch.MiscStallCycles 8734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
|
|
@ -857,13 +857,13 @@ system.cpu2.fetch.PendingTrapStallCycles 59780 # Nu
|
|||
system.cpu2.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions
|
||||
system.cpu2.fetch.IcacheWaitRetryStallCycles 573 # Number of stall cycles due to full MSHR
|
||||
system.cpu2.fetch.CacheLines 3640195 # Number of cache lines fetched
|
||||
system.cpu2.fetch.IcacheSquashes 178300 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu2.fetch.IcacheSquashes 178301 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu2.fetch.ItlbSquashes 3755 # Number of outstanding ITLB misses that were squashed
|
||||
system.cpu2.fetch.rateDist::samples 154824000 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::samples 154823972 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::mean 1.854554 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::stdev 3.033337 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::0 98922679 63.89% 63.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::0 98922650 63.89% 63.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::1 904691 0.58% 64.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::2 23796776 15.37% 79.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::3 606779 0.39% 80.24% # Number of instructions fetched each cycle (Total)
|
||||
|
|
@ -871,36 +871,36 @@ system.cpu2.fetch.rateDist::4 848220 0.55% 80.79% # Nu
|
|||
system.cpu2.fetch.rateDist::5 866864 0.56% 81.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::6 584872 0.38% 81.73% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::7 770506 0.50% 82.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::8 27522613 17.78% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::8 27522614 17.78% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::total 154824000 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.rateDist::total 154823972 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu2.fetch.branchRate 0.189933 # Number of branch fetches per cycle
|
||||
system.cpu2.fetch.rate 0.936190 # Number of inst fetches per cycle
|
||||
system.cpu2.decode.IdleCycles 10345116 # Number of cycles decode is idle
|
||||
system.cpu2.decode.BlockedCycles 94152744 # Number of cycles decode is blocked
|
||||
system.cpu2.decode.RunCycles 23674011 # Number of cycles decode is running
|
||||
system.cpu2.decode.IdleCycles 10345115 # Number of cycles decode is idle
|
||||
system.cpu2.decode.BlockedCycles 94152716 # Number of cycles decode is blocked
|
||||
system.cpu2.decode.RunCycles 23674012 # Number of cycles decode is running
|
||||
system.cpu2.decode.UnblockCycles 5064791 # Number of cycles decode is unblocking
|
||||
system.cpu2.decode.SquashCycles 359462 # Number of cycles decode is squashing
|
||||
system.cpu2.decode.DecodedInsts 284127557 # Number of instructions handled by decode
|
||||
system.cpu2.decode.DecodedInsts 284127567 # Number of instructions handled by decode
|
||||
system.cpu2.rename.SquashCycles 359462 # Number of cycles rename is squashing
|
||||
system.cpu2.rename.IdleCycles 12498058 # Number of cycles rename is idle
|
||||
system.cpu2.rename.BlockCycles 76923253 # Number of cycles rename is blocking
|
||||
system.cpu2.rename.serializeStallCycles 4647068 # count of cycles rename stalled for serializing inst
|
||||
system.cpu2.rename.BlockCycles 76923279 # Number of cycles rename is blocking
|
||||
system.cpu2.rename.serializeStallCycles 4647064 # count of cycles rename stalled for serializing inst
|
||||
system.cpu2.rename.RunCycles 26307426 # Number of cycles rename is running
|
||||
system.cpu2.rename.UnblockCycles 12860925 # Number of cycles rename is unblocking
|
||||
system.cpu2.rename.RenamedInsts 282811274 # Number of instructions processed by rename
|
||||
system.cpu2.rename.UnblockCycles 12860875 # Number of cycles rename is unblocking
|
||||
system.cpu2.rename.RenamedInsts 282811276 # Number of instructions processed by rename
|
||||
system.cpu2.rename.ROBFullEvents 202798 # Number of times rename has blocked due to ROB full
|
||||
system.cpu2.rename.IQFullEvents 5895071 # Number of times rename has blocked due to IQ full
|
||||
system.cpu2.rename.LQFullEvents 49763 # Number of times rename has blocked due to LQ full
|
||||
system.cpu2.rename.SQFullEvents 4758021 # Number of times rename has blocked due to SQ full
|
||||
system.cpu2.rename.RenamedOperands 337796411 # Number of destination operands rename has renamed
|
||||
system.cpu2.rename.RenameLookups 617680830 # Number of register rename lookups that rename has made
|
||||
system.cpu2.rename.int_rename_lookups 379222273 # Number of integer rename lookups
|
||||
system.cpu2.rename.SQFullEvents 4757971 # Number of times rename has blocked due to SQ full
|
||||
system.cpu2.rename.RenamedOperands 337796416 # Number of destination operands rename has renamed
|
||||
system.cpu2.rename.RenameLookups 617680837 # Number of register rename lookups that rename has made
|
||||
system.cpu2.rename.int_rename_lookups 379222279 # Number of integer rename lookups
|
||||
system.cpu2.rename.fp_rename_lookups 178 # Number of floating rename lookups
|
||||
system.cpu2.rename.CommittedMaps 324911571 # Number of HB maps that are committed
|
||||
system.cpu2.rename.UndoneMaps 12884840 # Number of HB maps that are undone due to squashing
|
||||
system.cpu2.rename.UndoneMaps 12884845 # Number of HB maps that are undone due to squashing
|
||||
system.cpu2.rename.serializingInsts 166150 # count of serializing insts renamed
|
||||
system.cpu2.rename.tempSerializingInsts 167782 # count of temporary serializing insts renamed
|
||||
system.cpu2.rename.skidInsts 24657180 # count of insts added to the skid buffer
|
||||
|
|
@ -908,18 +908,18 @@ system.cpu2.memDep0.insertedLoads 6871363 # Nu
|
|||
system.cpu2.memDep0.insertedStores 3845087 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu2.memDep0.conflictingLoads 401055 # Number of conflicting loads.
|
||||
system.cpu2.memDep0.conflictingStores 322271 # Number of conflicting stores.
|
||||
system.cpu2.iq.iqInstsAdded 280748482 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu2.iq.iqInstsAdded 280748481 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu2.iq.iqNonSpecInstsAdded 429304 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu2.iq.iqInstsIssued 278478009 # Number of instructions issued
|
||||
system.cpu2.iq.iqSquashedInstsIssued 108269 # Number of squashed instructions issued
|
||||
system.cpu2.iq.iqSquashedInstsExamined 9486121 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu2.iq.iqSquashedOperandsExamined 14384380 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu2.iq.iqSquashedInstsExamined 9486120 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu2.iq.iqSquashedOperandsExamined 14384377 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu2.iq.iqSquashedNonSpecRemoved 66849 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu2.iq.issued_per_cycle::samples 154824000 # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::samples 154823972 # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::mean 1.798675 # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::stdev 2.397594 # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::0 91620665 59.18% 59.18% # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::0 91620637 59.18% 59.18% # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::1 5352321 3.46% 62.63% # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::2 3836914 2.48% 65.11% # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::3 3858930 2.49% 67.61% # Number of insts issued each cycle
|
||||
|
|
@ -931,7 +931,7 @@ system.cpu2.iq.issued_per_cycle::8 223159 0.14% 100.00% # Nu
|
|||
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::total 154824000 # Number of insts issued each cycle
|
||||
system.cpu2.iq.issued_per_cycle::total 154823972 # Number of insts issued each cycle
|
||||
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu2.iq.fu_full::IntAlu 1768977 86.18% 86.18% # attempts to use FU when none available
|
||||
system.cpu2.iq.fu_full::IntMult 0 0.00% 86.18% # attempts to use FU when none available
|
||||
|
|
@ -1004,8 +1004,8 @@ system.cpu2.iq.FU_type_0::total 278478009 # Ty
|
|||
system.cpu2.iq.rate 1.786780 # Inst issue rate
|
||||
system.cpu2.iq.fu_busy_cnt 2052604 # FU busy when requested
|
||||
system.cpu2.iq.fu_busy_rate 0.007371 # FU busy rate (busy events/executed inst)
|
||||
system.cpu2.iq.int_inst_queue_reads 713940635 # Number of integer instruction queue reads
|
||||
system.cpu2.iq.int_inst_queue_writes 290668152 # Number of integer instruction queue writes
|
||||
system.cpu2.iq.int_inst_queue_reads 713940607 # Number of integer instruction queue reads
|
||||
system.cpu2.iq.int_inst_queue_writes 290668150 # Number of integer instruction queue writes
|
||||
system.cpu2.iq.int_inst_queue_wakeup_accesses 276821518 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu2.iq.fp_inst_queue_reads 256 # Number of floating instruction queue reads
|
||||
system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes
|
||||
|
|
@ -1024,15 +1024,15 @@ system.cpu2.iew.lsq.thread0.rescheduledLoads 750358
|
|||
system.cpu2.iew.lsq.thread0.cacheBlocked 29268 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu2.iew.iewSquashCycles 359462 # Number of cycles IEW is squashing
|
||||
system.cpu2.iew.iewBlockCycles 70735172 # Number of cycles IEW is blocking
|
||||
system.cpu2.iew.iewUnblockCycles 3134720 # Number of cycles IEW is unblocking
|
||||
system.cpu2.iew.iewDispatchedInsts 281177786 # Number of instructions dispatched to IQ
|
||||
system.cpu2.iew.iewBlockCycles 70735218 # Number of cycles IEW is blocking
|
||||
system.cpu2.iew.iewUnblockCycles 3134704 # Number of cycles IEW is unblocking
|
||||
system.cpu2.iew.iewDispatchedInsts 281177785 # Number of instructions dispatched to IQ
|
||||
system.cpu2.iew.iewDispSquashedInsts 44449 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu2.iew.iewDispLoadInsts 6871363 # Number of dispatched load instructions
|
||||
system.cpu2.iew.iewDispStoreInsts 3845087 # Number of dispatched store instructions
|
||||
system.cpu2.iew.iewDispNonSpecInsts 251829 # Number of dispatched non-speculative instructions
|
||||
system.cpu2.iew.iewIQFullEvents 166997 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu2.iew.iewLSQFullEvents 2638315 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu2.iew.iewLSQFullEvents 2638299 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu2.iew.memOrderViolationEvents 5109 # Number of memory order violations
|
||||
system.cpu2.iew.predictedTakenIncorrect 196795 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu2.iew.predictedNotTakenIncorrect 202269 # Number of branches that were predicted not taken incorrectly
|
||||
|
|
@ -1054,14 +1054,14 @@ system.cpu2.iew.wb_penalized 0 # nu
|
|||
system.cpu2.iew.wb_rate 1.776152 # insts written-back per cycle
|
||||
system.cpu2.iew.wb_fanout 0.609742 # average fanout of values written-back
|
||||
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu2.commit.commitSquashedInsts 9482299 # The number of squashed insts skipped by commit
|
||||
system.cpu2.commit.commitSquashedInsts 9482298 # The number of squashed insts skipped by commit
|
||||
system.cpu2.commit.commitNonSpecStalls 362455 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu2.commit.branchMispredicts 346445 # The number of times a branch was mispredicted
|
||||
system.cpu2.commit.committed_per_cycle::samples 153408377 # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::mean 1.771035 # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::samples 153408349 # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::mean 1.771036 # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::stdev 2.652208 # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::0 95336138 62.15% 62.15% # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::0 95336110 62.15% 62.15% # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::1 4415580 2.88% 65.02% # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::2 1307869 0.85% 65.88% # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::3 24753928 16.14% 82.01% # Number of insts commited each cycle
|
||||
|
|
@ -1073,7 +1073,7 @@ system.cpu2.commit.committed_per_cycle::8 2113838 1.38% 100.00% # N
|
|||
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::total 153408377 # Number of insts commited each cycle
|
||||
system.cpu2.commit.committed_per_cycle::total 153408349 # Number of insts commited each cycle
|
||||
system.cpu2.commit.committedInsts 137757751 # Number of instructions committed
|
||||
system.cpu2.commit.committedOps 271691665 # Number of ops (including micro ops) committed
|
||||
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -1120,10 +1120,10 @@ system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu2.commit.op_class_0::total 271691665 # Class of committed instruction
|
||||
system.cpu2.commit.bw_lim_events 2113838 # number cycles where commit BW limit reached
|
||||
system.cpu2.rob.rob_reads 432438077 # The number of ROB reads
|
||||
system.cpu2.rob.rob_writes 563770770 # The number of ROB writes
|
||||
system.cpu2.rob.rob_reads 432438048 # The number of ROB reads
|
||||
system.cpu2.rob.rob_writes 563770768 # The number of ROB writes
|
||||
system.cpu2.timesIdled 121162 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu2.idleCycles 1030675 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu2.idleCycles 1030703 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu2.quiesceCycles 4911308393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
||||
system.cpu2.committedInsts 137757751 # Number of Instructions Simulated
|
||||
system.cpu2.committedOps 271691665 # Number of Ops (including micro ops) Simulated
|
||||
|
|
@ -1330,11 +1330,11 @@ system.iocache.overall_avg_mshr_miss_latency::total 116467.334214
|
|||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 105183 # number of replacements
|
||||
system.l2c.tags.tagsinuse 64828.721241 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4684113 # Total number of references to valid blocks.
|
||||
system.l2c.tags.total_refs 4684115 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 169423 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 27.647445 # Average number of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 27.647456 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 50898.132317 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::writebacks 50898.132312 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.126487 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 1607.202570 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 5199.796885 # Average occupied blocks per requestor
|
||||
|
|
@ -1342,7 +1342,7 @@ system.l2c.tags.occ_blocks::cpu1.inst 251.414397 # Av
|
|||
system.l2c.tags.occ_blocks::cpu1.data 1573.306131 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.399418 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.itb.walker 0.004770 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 1229.783271 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 1229.783276 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.data 4062.554995 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.776644 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
|
|
@ -1362,8 +1362,8 @@ system.l2c.tags.age_task_id_blocks_1024::2 3044 #
|
|||
system.l2c.tags.age_task_id_blocks_1024::3 6984 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 54074 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.980225 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 41790314 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 41790314 # Number of data accesses
|
||||
system.l2c.tags.tag_accesses 41790330 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 41790330 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 18694 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 10376 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 14927 # number of ReadReq hits
|
||||
|
|
@ -1385,8 +1385,8 @@ system.l2c.ReadExReq_hits::cpu2.data 63793 # nu
|
|||
system.l2c.ReadExReq_hits::total 159309 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 284171 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 176684 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu2.inst 403286 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 864141 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu2.inst 403287 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 864142 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 469690 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 225324 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu2.data 620313 # number of ReadSharedReq hits
|
||||
|
|
@ -1401,9 +1401,9 @@ system.l2c.demand_hits::cpu1.inst 176684 # nu
|
|||
system.l2c.demand_hits::cpu1.data 263579 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.dtb.walker 63394 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.itb.walker 13067 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.inst 403286 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.inst 403287 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu2.data 684106 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2467689 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2467690 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 18694 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 10378 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 284171 # number of overall hits
|
||||
|
|
@ -1414,9 +1414,9 @@ system.l2c.overall_hits::cpu1.inst 176684 # nu
|
|||
system.l2c.overall_hits::cpu1.data 263579 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.dtb.walker 63394 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.itb.walker 13067 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.inst 403286 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.inst 403287 # number of overall hits
|
||||
system.l2c.overall_hits::cpu2.data 684106 # number of overall hits
|
||||
system.l2c.overall_hits::total 2467689 # number of overall hits
|
||||
system.l2c.overall_hits::total 2467690 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.dtb.walker 37 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses
|
||||
|
|
@ -1464,28 +1464,28 @@ system.l2c.UpgradeReq_miss_latency::cpu1.data 6342500
|
|||
system.l2c.UpgradeReq_miss_latency::cpu2.data 7566000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 13908500 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 2068321500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu2.data 3225795000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 5294116500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu2.data 3225771000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 5294092500 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 254232000 # number of ReadCleanReq miss cycles
|
||||
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 507297500 # number of ReadCleanReq miss cycles
|
||||
system.l2c.ReadCleanReq_miss_latency::total 761529500 # number of ReadCleanReq miss cycles
|
||||
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 507311500 # number of ReadCleanReq miss cycles
|
||||
system.l2c.ReadCleanReq_miss_latency::total 761543500 # number of ReadCleanReq miss cycles
|
||||
system.l2c.ReadSharedReq_miss_latency::cpu1.data 380479000 # number of ReadSharedReq miss cycles
|
||||
system.l2c.ReadSharedReq_miss_latency::cpu2.data 1184085000 # number of ReadSharedReq miss cycles
|
||||
system.l2c.ReadSharedReq_miss_latency::total 1564564000 # number of ReadSharedReq miss cycles
|
||||
system.l2c.ReadSharedReq_miss_latency::cpu2.data 1184076000 # number of ReadSharedReq miss cycles
|
||||
system.l2c.ReadSharedReq_miss_latency::total 1564555000 # number of ReadSharedReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.inst 254232000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 2448800500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.dtb.walker 3871500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.itb.walker 83000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.inst 507297500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.data 4409880000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 7624164500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.inst 507311500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.data 4409847000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 7624145500 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.inst 254232000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.data 2448800500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.dtb.walker 3871500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.itb.walker 83000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.inst 507297500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.data 4409880000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 7624164500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.inst 507311500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.data 4409847000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 7624145500 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 18694 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 10381 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 14927 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -1507,8 +1507,8 @@ system.l2c.ReadExReq_accesses::cpu2.data 104536 # nu
|
|||
system.l2c.ReadExReq_accesses::total 290245 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::cpu0.inst 290070 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::cpu1.inst 179832 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::cpu2.inst 409276 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::total 879178 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::cpu2.inst 409277 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::total 879179 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu0.data 484746 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.data 229888 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu2.data 633950 # number of ReadSharedReq accesses(hits+misses)
|
||||
|
|
@ -1523,9 +1523,9 @@ system.l2c.demand_accesses::cpu1.inst 179832 # nu
|
|||
system.l2c.demand_accesses::cpu1.data 295642 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu2.dtb.walker 63431 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu2.itb.walker 13068 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu2.inst 409276 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu2.inst 409277 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu2.data 738486 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2646962 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2646963 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.dtb.walker 18694 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.itb.walker 10383 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 290070 # number of overall (read+write) accesses
|
||||
|
|
@ -1536,9 +1536,9 @@ system.l2c.overall_accesses::cpu1.inst 179832 # nu
|
|||
system.l2c.overall_accesses::cpu1.data 295642 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu2.dtb.walker 63431 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu2.itb.walker 13068 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu2.inst 409276 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu2.inst 409277 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu2.data 738486 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2646962 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2646963 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000482 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000583 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000077 # miss rate for ReadReq accesses
|
||||
|
|
@ -1586,28 +1586,28 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18654.411765
|
|||
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12673.366834 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 9801.620860 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75214.425979 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79174.213975 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 40432.856510 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79173.624917 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 40432.673214 # average ReadExReq miss latency
|
||||
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80759.847522 # average ReadCleanReq miss latency
|
||||
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84690.734558 # average ReadCleanReq miss latency
|
||||
system.l2c.ReadCleanReq_avg_miss_latency::total 50643.712177 # average ReadCleanReq miss latency
|
||||
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84693.071786 # average ReadCleanReq miss latency
|
||||
system.l2c.ReadCleanReq_avg_miss_latency::total 50644.643213 # average ReadCleanReq miss latency
|
||||
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83365.249781 # average ReadSharedReq miss latency
|
||||
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 86828.847987 # average ReadSharedReq miss latency
|
||||
system.l2c.ReadSharedReq_avg_miss_latency::total 47044.652254 # average ReadSharedReq miss latency
|
||||
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 86828.188018 # average ReadSharedReq miss latency
|
||||
system.l2c.ReadSharedReq_avg_miss_latency::total 47044.381634 # average ReadSharedReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.inst 80759.847522 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.data 76374.653027 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 104635.135135 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 83000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.inst 84690.734558 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.data 81093.784480 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 42528.236265 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.inst 84693.071786 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.data 81093.177639 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 42528.130282 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.inst 80759.847522 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.data 76374.653027 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 104635.135135 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 83000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.inst 84690.734558 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.data 81093.784480 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 42528.236265 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.inst 84693.071786 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.data 81093.177639 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 42528.130282 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -1671,28 +1671,28 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 7682000
|
|||
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 12454500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 20136500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1793331500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2818365000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4611696500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2818341000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4611672500 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 222752000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 447335500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.l2c.ReadCleanReq_mshr_miss_latency::total 670087500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 447349500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.l2c.ReadCleanReq_mshr_miss_latency::total 670101500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 334839000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1048084000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2c.ReadSharedReq_mshr_miss_latency::total 1382923000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1048075000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2c.ReadSharedReq_mshr_miss_latency::total 1382914000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.inst 222752000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.data 2128170500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3501500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 73000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.inst 447335500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.data 3866449000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 6668281500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.inst 447349500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.data 3866416000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 6668262500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.inst 222752000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.data 2128170500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3501500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 73000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.inst 447335500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.data 3866449000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6668281500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.inst 447349500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.data 3866416000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 6668262500 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28284583500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30647941500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 58932525000 # number of ReadReq MSHR uncacheable cycles
|
||||
|
|
@ -1740,28 +1740,28 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22594.117647
|
|||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20861.809045 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21490.394877 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65214.425979 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69174.213975 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67578.565986 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69173.624917 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67578.214296 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70759.847522 # average ReadCleanReq mshr miss latency
|
||||
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74692.853565 # average ReadCleanReq mshr miss latency
|
||||
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73337.802342 # average ReadCleanReq mshr miss latency
|
||||
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74695.191184 # average ReadCleanReq mshr miss latency
|
||||
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73339.334574 # average ReadCleanReq mshr miss latency
|
||||
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73365.249781 # average ReadSharedReq mshr miss latency
|
||||
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76855.906724 # average ReadSharedReq mshr miss latency
|
||||
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75980.605461 # average ReadSharedReq mshr miss latency
|
||||
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 76855.246755 # average ReadSharedReq mshr miss latency
|
||||
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75980.110983 # average ReadSharedReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70759.847522 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66374.653027 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74692.853565 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71100.570063 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 69738.767805 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74695.191184 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71099.963222 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 69738.569098 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70759.847522 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66374.653027 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 94635.135135 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74692.853565 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71100.570063 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 69738.767805 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74695.191184 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71099.963222 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 69738.569098 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152038.226472 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149511.634884 # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150713.704820 # average ReadReq mshr uncacheable latency
|
||||
|
|
@ -1831,7 +1831,7 @@ system.membus.reqLayer4.occupancy 4500 # La
|
|||
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer0.occupancy 1173000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 1355053149 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.occupancy 1355052899 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer4.occupancy 39163714 # Layer occupancy (ticks)
|
||||
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -1848,47 +1848,47 @@ system.pc.south_bridge.ide.disks1.dma_write_full_pages 1
|
|||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.toL2Bus.trans_dist::ReadReq 5228129 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 7456138 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 7456139 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 13940 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 13940 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 1629241 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 974525 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 974526 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 1670 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 1670 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 290245 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 290245 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadCleanReq 879201 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadCleanReq 879202 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadSharedReq 1349341 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::MessageReq 1173 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::InvalidateReq 20232 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2636643 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2636646 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15081470 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73733 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 221081 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 18012927 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56268224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 18012930 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56268288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213600772 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 270696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 799584 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 270939276 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 270939340 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 164260 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 10415382 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::samples 10415384 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 1.028580 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.166622 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 10117713 97.14% 97.14% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 10117715 97.14% 97.14% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 297669 2.86% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 10415382 # Request fanout histogram
|
||||
system.toL2Bus.reqLayer0.occupancy 2866107499 # Layer occupancy (ticks)
|
||||
system.toL2Bus.snoop_fanout::total 10415384 # Request fanout histogram
|
||||
system.toL2Bus.reqLayer0.occupancy 2866108499 # Layer occupancy (ticks)
|
||||
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.toL2Bus.snoopLayer0.occupancy 340500 # Layer occupancy (ticks)
|
||||
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.toL2Bus.respLayer0.occupancy 884323704 # Layer occupancy (ticks)
|
||||
system.toL2Bus.respLayer0.occupancy 884325204 # Layer occupancy (ticks)
|
||||
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.toL2Bus.respLayer1.occupancy 1946611318 # Layer occupancy (ticks)
|
||||
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
File diff suppressed because it is too large
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Reference in a new issue