x86: decode instructions with vex prefix
This patch updates the x86 decoder so that it can decode instructions with vex prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3. Note that none of the instructions have been implemented yet. The implementations would be provided in due course of time.
This commit is contained in:
Nilay Vaish
parent
fc5bf6713f
commit
0ef3dcc27b
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@ -48,6 +48,8 @@ Decoder::doResetState()
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emi.rex = 0;
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emi.legacy = 0;
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emi.vex = 0;
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emi.opcode.type = BadOpcode;
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emi.opcode.op = 0;
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@ -93,6 +95,19 @@ Decoder::process()
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case PrefixState:
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state = doPrefixState(nextByte);
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break;
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case TwoByteVexState:
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state = doTwoByteVexState(nextByte);
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break;
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case ThreeByteVexFirstState:
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state = doThreeByteVexFirstState(nextByte);
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break;
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case ThreeByteVexSecondState:
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state = doThreeByteVexSecondState(nextByte);
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break;
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case OneByteOpcodeState:
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state = doOneByteOpcodeState(nextByte);
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break;
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@ -206,15 +221,68 @@ Decoder::doPrefixState(uint8_t nextByte)
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DPRINTF(Decoder, "Found Rex prefix %#x.\n", nextByte);
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emi.rex = nextByte;
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break;
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case Vex2Prefix:
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DPRINTF(Decoder, "Found VEX two-byte prefix %#x.\n", nextByte);
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emi.vex.zero = nextByte;
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nextState = TwoByteVexState;
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break;
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case Vex3Prefix:
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DPRINTF(Decoder, "Found VEX three-byte prefix %#x.\n", nextByte);
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emi.vex.zero = nextByte;
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nextState = ThreeByteVexFirstState;
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break;
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case 0:
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nextState = OneByteOpcodeState;
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break;
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default:
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panic("Unrecognized prefix %#x\n", nextByte);
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}
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return nextState;
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}
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Decoder::State
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Decoder::doTwoByteVexState(uint8_t nextByte)
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{
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assert(emi.vex.zero == 0xc5);
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consumeByte();
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TwoByteVex tbe = 0;
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tbe.first = nextByte;
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emi.vex.first.r = tbe.first.r;
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emi.vex.first.x = 1;
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emi.vex.first.b = 1;
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emi.vex.first.map_select = 1;
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emi.vex.second.w = 0;
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emi.vex.second.vvvv = tbe.first.vvvv;
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emi.vex.second.l = tbe.first.l;
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emi.vex.second.pp = tbe.first.pp;
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emi.opcode.type = Vex;
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return OneByteOpcodeState;
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}
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Decoder::State
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Decoder::doThreeByteVexFirstState(uint8_t nextByte)
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{
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consumeByte();
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emi.vex.first = nextByte;
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return ThreeByteVexSecondState;
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}
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Decoder::State
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Decoder::doThreeByteVexSecondState(uint8_t nextByte)
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{
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consumeByte();
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emi.vex.second = nextByte;
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emi.opcode.type = Vex;
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return OneByteOpcodeState;
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}
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// Load the first opcode byte. Determine if there are more opcode bytes, and
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// if not, what immediate and/or ModRM is needed.
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Decoder::State
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@ -222,7 +290,13 @@ Decoder::doOneByteOpcodeState(uint8_t nextByte)
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{
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State nextState = ErrorState;
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consumeByte();
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if (nextByte == 0x0f) {
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if (emi.vex.zero != 0) {
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DPRINTF(Decoder, "Found VEX opcode %#x.\n", nextByte);
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emi.opcode.op = nextByte;
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const uint8_t opcode_map = emi.vex.first.map_select;
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nextState = processExtendedOpcode(ImmediateTypeVex[opcode_map]);
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} else if (nextByte == 0x0f) {
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nextState = TwoByteOpcodeState;
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DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
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} else {
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@ -346,6 +420,54 @@ Decoder::processOpcode(ByteTable &immTable, ByteTable &modrmTable,
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return nextState;
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}
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Decoder::State
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Decoder::processExtendedOpcode(ByteTable &immTable)
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{
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//Figure out the effective operand size. This can be overriden to
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//a fixed value at the decoder level.
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int logOpSize;
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if (emi.vex.second.w)
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logOpSize = 3; // 64 bit operand size
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else if (emi.vex.second.pp == 1)
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logOpSize = altOp;
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else
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logOpSize = defOp;
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//Set the actual op size
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emi.opSize = 1 << logOpSize;
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//Figure out the effective address size. This can be overriden to
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//a fixed value at the decoder level.
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int logAddrSize;
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if(emi.legacy.addr)
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logAddrSize = altAddr;
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else
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logAddrSize = defAddr;
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//Set the actual address size
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emi.addrSize = 1 << logAddrSize;
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//Figure out the effective stack width. This can be overriden to
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//a fixed value at the decoder level.
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emi.stackSize = 1 << stack;
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//Figure out how big of an immediate we'll retreive based
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//on the opcode.
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const uint8_t opcode = emi.opcode.op;
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if (emi.vex.zero == 0xc5 || emi.vex.zero == 0xc4) {
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int immType = immTable[opcode];
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// Assume 64-bit mode;
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immediateSize = SizeTypeToSize[2][immType];
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}
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if (opcode == 0x77) {
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instDone = true;
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return ResetState;
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}
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return ModRMState;
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}
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//Get the ModRM byte and determine what displacement, if any, there is.
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//Also determine whether or not to get the SIB byte, displacement, or
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//immediate next.
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@ -353,8 +475,7 @@ Decoder::State
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Decoder::doModRMState(uint8_t nextByte)
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{
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State nextState = ErrorState;
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ModRM modRM;
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modRM = nextByte;
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ModRM modRM = nextByte;
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DPRINTF(Decoder, "Found modrm byte %#x.\n", nextByte);
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if (defOp == 1) {
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//figure out 16 bit displacement size
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@ -64,6 +64,7 @@ class Decoder
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static ByteTable ImmediateTypeTwoByte;
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static ByteTable ImmediateTypeThreeByte0F38;
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static ByteTable ImmediateTypeThreeByte0F3A;
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static ByteTable ImmediateTypeVex[10];
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protected:
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struct InstBytes
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@ -175,6 +176,9 @@ class Decoder
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ResetState,
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FromCacheState,
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PrefixState,
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TwoByteVexState,
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ThreeByteVexFirstState,
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ThreeByteVexSecondState,
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OneByteOpcodeState,
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TwoByteOpcodeState,
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ThreeByte0F38OpcodeState,
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@ -193,6 +197,9 @@ class Decoder
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State doResetState();
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State doFromCacheState();
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State doPrefixState(uint8_t);
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State doTwoByteVexState(uint8_t);
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State doThreeByteVexFirstState(uint8_t);
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State doThreeByteVexSecondState(uint8_t);
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State doOneByteOpcodeState(uint8_t);
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State doTwoByteOpcodeState(uint8_t);
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State doThreeByte0F38OpcodeState(uint8_t);
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@ -205,6 +212,8 @@ class Decoder
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//Process the actual opcode found earlier, using the supplied tables.
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State processOpcode(ByteTable &immTable, ByteTable &modrmTable,
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bool addrSizedImm = false);
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// Process the opcode found with VEX / XOP prefix.
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State processExtendedOpcode(ByteTable &immTable);
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protected:
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/// Caching for decoded instruction objects.
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@ -55,6 +55,8 @@ namespace X86ISA
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const uint8_t RE = Rep;
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const uint8_t RN = Repne;
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const uint8_t RX = RexPrefix;
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const uint8_t V2 = Vex2Prefix;
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const uint8_t V3 = Vex3Prefix;
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//This table identifies whether a byte is a prefix, and if it is,
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//which prefix it is.
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@ -73,7 +75,7 @@ namespace X86ISA
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/* 9*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
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/* A*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
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/* B*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
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/* C*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
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/* C*/ 0 , 0 , 0 , 0 , V3, V2, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
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/* D*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
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/* E*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
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/* F*/ LO, 0 , RN, RE, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
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@ -282,4 +284,74 @@ namespace X86ISA
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/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
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};
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const Decoder::ByteTable Decoder::ImmediateTypeVex[10] =
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{
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// Table for opcode map 1
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{
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//LSB
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// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
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/* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 1 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 2 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 4 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 6 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 7 */ BY, BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* A */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* C */ 0 , 0 , BY, 0 , BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
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},
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// Table for opcode map 2
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{
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//LSB
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// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
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/* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 1 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 2 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 4 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 6 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 7 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* A */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* C */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
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},
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// Table for opcode map 3
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{
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//LSB
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// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
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/* 0 */ 0 , 0 , 0 , 0 , BY, BY, BY, 0 , BY, BY, BY, BY, BY, BY, BY, BY,
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/* 1 */ 0 , 0 , 0 , 0 , BY, BY, BY, BY, BY, BY, 0 , 0 , 0 , BY, 0 , 0 ,
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/* 2 */ BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 4 */ BY, BY, BY, 0 , BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 6 */ BY, BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 7 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* A */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* C */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY,
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/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
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},
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{}, {}, {}, {}, {}, {}, {}
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};
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}
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@ -87,3 +87,12 @@ def bitfield STACKSIZE stackSize;
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def bitfield MODE mode;
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def bitfield MODE_MODE mode.mode;
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def bitfield MODE_SUBMODE mode.submode;
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def bitfield VEX_R vex.first.r;
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def bitfield VEX_X vex.first.x;
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def bitfield VEX_B vex.first.b;
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def bitfield VEX_MAP vex.first.map_select;
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def bitfield VEX_W vex.second.w;
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def bitfield VEX_VVVV vex.second.vvvv;
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def bitfield VEX_L vex.second.l;
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def bitfield VEX_PP vex.second.pp;
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@ -49,6 +49,7 @@ decode LEGACY_LOCK default Unknown::unknown()
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##include "two_byte_opcodes.isa"
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##include "three_byte_0f38_opcodes.isa"
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##include "three_byte_0f3a_opcodes.isa"
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##include "vex_opcodes.isa"
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}
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//Lock prefix
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##include "locked_opcodes.isa"
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1431
src/arch/x86/isa/decoder/vex_opcodes.isa
Normal file
1431
src/arch/x86/isa/decoder/vex_opcodes.isa
Normal file
File diff suppressed because it is too large
Load diff
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@ -71,7 +71,8 @@ namespace X86ISA
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const ExtMachInst NoopMachInst M5_VAR_USED = {
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0x0, // No legacy prefixes.
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0x0, // No rex prefix.
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{ OneByteOpcode, 0x90 }, // One opcode byte, 0x90.
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0x0, // No two / three byte escape sequence
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{ OneByteOpcode, 0x90 }, // One opcode byte, 0x90.
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0x0, 0x0, // No modrm or sib.
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0, 0, // No immediate or displacement.
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8, 8, 8, // All sizes are 8.
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@ -41,6 +41,7 @@ paramOut(CheckpointOut &cp, const string &name, ExtMachInst const &machInst)
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// Prefixes
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paramOut(cp, name + ".legacy", (uint8_t)machInst.legacy);
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paramOut(cp, name + ".rex", (uint8_t)machInst.rex);
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paramOut(cp, name + ".vex", (uint32_t)machInst.vex);
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// Opcode
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paramOut(cp, name + ".opcode.type", (uint8_t)machInst.opcode.type);
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@ -75,6 +76,10 @@ paramIn(CheckpointIn &cp, const string &name, ExtMachInst &machInst)
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paramIn(cp, name + ".rex", temp8);
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machInst.rex = temp8;
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uint32_t temp32;
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paramIn(cp, name + ".vex", temp32);
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machInst.vex = temp32;
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// Opcode
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paramIn(cp, name + ".opcode.type", temp8);
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machInst.opcode.type = (OpcodeType)temp8;
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@ -67,7 +67,10 @@ namespace X86ISA
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AddressSizeOverride,
|
||||
Lock,
|
||||
Rep,
|
||||
Repne
|
||||
Repne,
|
||||
Vex2Prefix,
|
||||
Vex3Prefix,
|
||||
XopPrefix,
|
||||
};
|
||||
|
||||
BitUnion8(LegacyPrefixVector)
|
||||
|
|
@ -104,12 +107,55 @@ namespace X86ISA
|
|||
Bitfield<0> b;
|
||||
EndBitUnion(Rex)
|
||||
|
||||
BitUnion(uint32_t, ThreeByteVex)
|
||||
Bitfield<7,0> zero;
|
||||
SubBitUnion(first, 15, 8)
|
||||
// Inverted one-bit extension of ModRM reg field
|
||||
Bitfield<15> r;
|
||||
// Inverted one-bit extension of SIB index field
|
||||
Bitfield<14> x;
|
||||
// Inverted one-bit extension, r/m field or SIB base field
|
||||
Bitfield<13> b;
|
||||
// Opcode map select
|
||||
Bitfield<12, 8> map_select;
|
||||
EndSubBitUnion(first)
|
||||
SubBitUnion(second, 23, 16)
|
||||
// Default operand size override for a general purpose register to
|
||||
// 64-bit size in 64-bit mode; operand configuration specifier for
|
||||
// certain YMM/XMM-based operations.
|
||||
Bitfield<23> w;
|
||||
// Source or destination register selector, in ones' complement
|
||||
// format
|
||||
Bitfield<22, 19> vvvv;
|
||||
// Vector length specifier
|
||||
Bitfield<18> l;
|
||||
// Implied 66, F2, or F3 opcode extension
|
||||
Bitfield<17, 16> pp;
|
||||
EndSubBitUnion(second)
|
||||
EndBitUnion(ThreeByteVex)
|
||||
|
||||
BitUnion16(TwoByteVex)
|
||||
Bitfield<7,0> zero;
|
||||
SubBitUnion(first, 15, 8)
|
||||
// Inverted one-bit extension of ModRM reg field
|
||||
Bitfield<15> r;
|
||||
// Source or destination register selector, in ones' complement
|
||||
// format
|
||||
Bitfield<14, 11> vvvv;
|
||||
// Vector length specifier
|
||||
Bitfield<10> l;
|
||||
// Implied 66, F2, or F3 opcode extension
|
||||
Bitfield<9, 8> pp;
|
||||
EndSubBitUnion(first)
|
||||
EndBitUnion(TwoByteVex)
|
||||
|
||||
enum OpcodeType {
|
||||
BadOpcode,
|
||||
OneByteOpcode,
|
||||
TwoByteOpcode,
|
||||
ThreeByte0F38Opcode,
|
||||
ThreeByte0F3AOpcode
|
||||
ThreeByte0F3AOpcode,
|
||||
Vex,
|
||||
};
|
||||
|
||||
static inline const char *
|
||||
|
|
@ -126,6 +172,8 @@ namespace X86ISA
|
|||
return "three byte 0f38";
|
||||
case ThreeByte0F3AOpcode:
|
||||
return "three byte 0f3a";
|
||||
case Vex:
|
||||
return "vex";
|
||||
default:
|
||||
return "unrecognized!";
|
||||
}
|
||||
|
|
@ -160,6 +208,10 @@ namespace X86ISA
|
|||
//Prefixes
|
||||
LegacyPrefixVector legacy;
|
||||
Rex rex;
|
||||
// We use the following field for encoding both two byte and three byte
|
||||
// escape sequences
|
||||
ThreeByteVex vex;
|
||||
|
||||
//This holds all of the bytes of the opcode
|
||||
struct
|
||||
{
|
||||
|
|
@ -191,11 +243,13 @@ namespace X86ISA
|
|||
operator << (std::ostream & os, const ExtMachInst & emi)
|
||||
{
|
||||
ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
|
||||
"vex/xop = %#x,\n\t"
|
||||
"op = {\n\t\ttype = %s,\n\t\top = %#x,\n\t\t},\n\t"
|
||||
"modRM = %#x,\n\tsib = %#x,\n\t"
|
||||
"immediate = %#x,\n\tdisplacement = %#x\n\t"
|
||||
"dispSize = %d}\n",
|
||||
(uint8_t)emi.legacy, (uint8_t)emi.rex,
|
||||
(uint32_t)emi.vex,
|
||||
opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op,
|
||||
(uint8_t)emi.modRM, (uint8_t)emi.sib,
|
||||
emi.immediate, emi.displacement, emi.dispSize);
|
||||
|
|
|
|||
Loading…
Reference in a new issue