stats: Update pc-switcheroo stats
The pc-switcheroo test cases has slightly different timing after decoupling draining from the SimObject hierarchy. This is expected since objects aren't drained in the exact same order as before.
This commit is contained in:
Andreas Sandberg
parent
ed38e3432c
commit
a0cbf55411
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@ -20,7 +20,7 @@ eventq_index=0
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init_param=0
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intel_mp_pointer=system.intel_mp_pointer
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intel_mp_table=system.intel_mp_table
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kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
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kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
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kernel_addr_check=true
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load_addr_mask=18446744073709551615
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load_offset=0
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@ -29,7 +29,7 @@ mem_ranges=0:134217727
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memories=system.physmem
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mmap_using_noreserve=false
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num_work_ids=16
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readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
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readfile=/work/gem5/outgoing/gem5/tests/halt.sh
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smbios_table=system.smbios_table
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symbolfile=
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work_begin_ckpt_count=0
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@ -1586,7 +1586,7 @@ table_size=65536
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[system.pc.south_bridge.ide.disks0.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
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image_file=/work/gem5/dist/disks/linux-x86.img
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read_only=true
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[system.pc.south_bridge.ide.disks1]
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@ -1609,7 +1609,7 @@ table_size=65536
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[system.pc.south_bridge.ide.disks1.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
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image_file=/work/gem5/dist/disks/linux-bigswap2.img
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read_only=true
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[system.pc.south_bridge.int_lines0]
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@ -1,13 +1,13 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Apr 22 2015 08:10:29
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gem5 started Apr 22 2015 10:12:51
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gem5 executing on phenom
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command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
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gem5 compiled Jul 6 2015 14:29:04
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gem5 started Jul 6 2015 20:46:38
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gem5 executing on e104799-lin
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command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5/outgoing/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
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info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
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0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 5154239928000 because m5_exit instruction encountered
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Exiting @ tick 5130108675000 because m5_exit instruction encountered
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@ -4,11 +4,11 @@ sim_seconds 5.130109 # Nu
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sim_ticks 5130108675000 # Number of ticks simulated
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final_tick 5130108675000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 175723 # Simulator instruction rate (inst/s)
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host_op_rate 347336 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2210269457 # Simulator tick rate (ticks/s)
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host_mem_usage 810456 # Number of bytes of host memory used
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host_seconds 2321.03 # Real time elapsed on the host
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host_inst_rate 172691 # Simulator instruction rate (inst/s)
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host_op_rate 341343 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2172133567 # Simulator tick rate (ticks/s)
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host_mem_usage 759908 # Number of bytes of host memory used
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host_seconds 2361.78 # Real time elapsed on the host
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sim_insts 407858109 # Number of instructions simulated
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sim_ops 806179275 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -20,7 +20,7 @@ eventq_index=0
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init_param=0
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intel_mp_pointer=system.intel_mp_pointer
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intel_mp_table=system.intel_mp_table
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kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9
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kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
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kernel_addr_check=true
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load_addr_mask=18446744073709551615
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load_offset=0
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@ -29,7 +29,7 @@ mem_ranges=0:134217727
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memories=system.physmem
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mmap_using_noreserve=false
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num_work_ids=16
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readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
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readfile=/work/gem5/outgoing/gem5/tests/halt.sh
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smbios_table=system.smbios_table
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symbolfile=
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work_begin_ckpt_count=0
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@ -1639,7 +1639,7 @@ table_size=65536
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[system.pc.south_bridge.ide.disks0.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img
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image_file=/work/gem5/dist/disks/linux-x86.img
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read_only=true
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[system.pc.south_bridge.ide.disks1]
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@ -1662,7 +1662,7 @@ table_size=65536
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[system.pc.south_bridge.ide.disks1.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
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image_file=/work/gem5/dist/disks/linux-bigswap2.img
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read_only=true
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[system.pc.south_bridge.int_lines0]
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@ -2,7 +2,7 @@
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"name": null,
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"sim_quantum": 0,
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"system": {
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"kernel": "/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9",
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"kernel": "/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9",
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"mmap_using_noreserve": false,
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"kernel_addr_check": true,
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"bridge": {
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@ -103,7 +103,10 @@
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},
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"symbolfile": "",
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"l2c": {
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"is_top_level": false,
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"cpu_side": {
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"peer": "system.toL2Bus.master[0]",
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"role": "SLAVE"
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},
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"prefetcher": null,
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"clk_domain": "system.cpu_clk_domain",
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"write_buffers": 8,
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@ -138,19 +141,15 @@
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"addr_ranges": [
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"0:18446744073709551615"
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],
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"assoc": 8,
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"is_read_only": false,
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"prefetch_on_access": false,
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"path": "system.l2c",
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"name": "l2c",
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"type": "BaseCache",
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"sequential_access": false,
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"cpu_side": {
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"peer": "system.toL2Bus.master[0]",
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"role": "SLAVE"
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},
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"two_queue": false
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"assoc": 8
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},
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"readfile": "/home/stever/hg/m5sim.org/gem5/tests/halt.sh",
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"readfile": "/work/gem5/outgoing/gem5/tests/halt.sh",
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"intel_mp_table": {
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"oem_table_addr": 0,
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"name": "intel_mp_table",
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@ -631,7 +630,10 @@
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"cxx_class": "LinuxX86System",
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"load_offset": 0,
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"iocache": {
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"is_top_level": true,
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"cpu_side": {
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"peer": "system.iobus.master[19]",
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"role": "SLAVE"
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},
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"prefetcher": null,
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"clk_domain": "system.clk_domain",
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"write_buffers": 8,
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@ -666,17 +668,13 @@
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"addr_ranges": [
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"0:134217727"
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],
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"assoc": 8,
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"is_read_only": false,
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"prefetch_on_access": false,
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"path": "system.iocache",
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"name": "iocache",
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"type": "BaseCache",
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"sequential_access": false,
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"cpu_side": {
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"peer": "system.iobus.master[19]",
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"role": "SLAVE"
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},
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"two_queue": false
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"assoc": 8
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},
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"intel_mp_pointer": {
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"imcr_present": true,
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@ -1185,7 +1183,7 @@
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"eventq_index": 0,
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"cxx_class": "RawDiskImage",
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"path": "system.pc.south_bridge.ide.disks0.image.child",
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"image_file": "/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img",
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"image_file": "/work/gem5/dist/disks/linux-x86.img",
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"type": "RawDiskImage"
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},
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"path": "system.pc.south_bridge.ide.disks0.image",
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@ -1213,7 +1211,7 @@
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"eventq_index": 0,
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"cxx_class": "RawDiskImage",
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"path": "system.pc.south_bridge.ide.disks1.image.child",
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"image_file": "/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img",
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"image_file": "/work/gem5/dist/disks/linux-bigswap2.img",
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"type": "RawDiskImage"
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},
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"path": "system.pc.south_bridge.ide.disks1.image",
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@ -1791,7 +1789,10 @@
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"role": "MASTER"
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},
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"icache": {
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"is_top_level": true,
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"cpu_side": {
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"peer": "system.cpu0.icache_port",
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"role": "SLAVE"
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},
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"prefetcher": null,
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"clk_domain": "system.cpu_clk_domain",
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"write_buffers": 8,
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@ -1826,17 +1827,13 @@
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"addr_ranges": [
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"0:18446744073709551615"
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],
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"assoc": 1,
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"is_read_only": true,
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"prefetch_on_access": false,
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"path": "system.cpu0.icache",
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"name": "icache",
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"type": "BaseCache",
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"sequential_access": false,
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"cpu_side": {
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"peer": "system.cpu0.icache_port",
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"role": "SLAVE"
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},
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"two_queue": false
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"assoc": 1
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},
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"interrupts": {
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"int_master": {
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@ -1901,7 +1898,10 @@
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"progress_interval": 0,
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"branchPred": null,
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"dcache": {
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"is_top_level": true,
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"cpu_side": {
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"peer": "system.cpu0.dcache_port",
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"role": "SLAVE"
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},
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"prefetcher": null,
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"clk_domain": "system.cpu_clk_domain",
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"write_buffers": 8,
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@ -1936,17 +1936,13 @@
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"addr_ranges": [
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"0:18446744073709551615"
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],
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"assoc": 4,
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"is_read_only": false,
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"prefetch_on_access": false,
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"path": "system.cpu0.dcache",
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"name": "dcache",
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"type": "BaseCache",
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"sequential_access": false,
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"cpu_side": {
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"peer": "system.cpu0.dcache_port",
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"role": "SLAVE"
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},
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"two_queue": false
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"assoc": 4
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},
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"isa": [
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{
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@ -2109,11 +2105,11 @@
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"count": 6,
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"opList": [
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{
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"issueLat": 1,
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"opClass": "IntAlu",
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"opLat": 1,
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"name": "opList",
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"pipelined": true,
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"eventq_index": 0,
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"opClass": "IntAlu",
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList0.opList",
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"type": "OpDesc"
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@ -2129,21 +2125,21 @@
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"count": 2,
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"opList": [
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{
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"issueLat": 1,
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"opClass": "IntMult",
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"opLat": 3,
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"name": "opList0",
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"pipelined": true,
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"eventq_index": 0,
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"opClass": "IntMult",
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList1.opList0",
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"type": "OpDesc"
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},
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{
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"issueLat": 19,
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"opLat": 20,
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"name": "opList1",
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"eventq_index": 0,
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"opClass": "IntDiv",
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"opLat": 1,
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"name": "opList1",
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"pipelined": false,
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"eventq_index": 0,
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList1.opList1",
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"type": "OpDesc"
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@ -2159,31 +2155,31 @@
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"count": 4,
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"opList": [
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{
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"issueLat": 1,
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"opClass": "FloatAdd",
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"opLat": 2,
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"name": "opList0",
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"pipelined": true,
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"eventq_index": 0,
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"opClass": "FloatAdd",
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList2.opList0",
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"type": "OpDesc"
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},
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{
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"issueLat": 1,
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"opClass": "FloatCmp",
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"opLat": 2,
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"name": "opList1",
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"pipelined": true,
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"eventq_index": 0,
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"opClass": "FloatCmp",
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList2.opList1",
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"type": "OpDesc"
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},
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{
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"issueLat": 1,
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"opClass": "FloatCvt",
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"opLat": 2,
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"name": "opList2",
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"pipelined": true,
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"eventq_index": 0,
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"opClass": "FloatCvt",
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList2.opList2",
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"type": "OpDesc"
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@ -2199,31 +2195,31 @@
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"count": 2,
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"opList": [
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{
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"issueLat": 1,
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"opClass": "FloatMult",
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"opLat": 4,
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"name": "opList0",
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"pipelined": true,
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"eventq_index": 0,
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"opClass": "FloatMult",
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList3.opList0",
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"type": "OpDesc"
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},
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{
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"issueLat": 12,
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"opClass": "FloatDiv",
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"opLat": 12,
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"name": "opList1",
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"pipelined": false,
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"eventq_index": 0,
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"opClass": "FloatDiv",
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList3.opList1",
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"type": "OpDesc"
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},
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{
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"issueLat": 24,
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"opClass": "FloatSqrt",
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"opLat": 24,
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"name": "opList2",
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"pipelined": false,
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"eventq_index": 0,
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"opClass": "FloatSqrt",
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList3.opList2",
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"type": "OpDesc"
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@ -2239,11 +2235,11 @@
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"count": 0,
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"opList": [
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{
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"issueLat": 1,
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"opClass": "MemRead",
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"opLat": 1,
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"name": "opList",
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"pipelined": true,
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"eventq_index": 0,
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"opClass": "MemRead",
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"cxx_class": "OpDesc",
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"path": "system.cpu2.fuPool.FUList4.opList",
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"type": "OpDesc"
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@ -2259,201 +2255,201 @@
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"count": 4,
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"opList": [
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{
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"issueLat": 1,
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"opClass": "SimdAdd",
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"opLat": 1,
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"name": "opList00",
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"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdAdd",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList00",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdAddAcc",
|
||||
"opLat": 1,
|
||||
"name": "opList01",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdAddAcc",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList01",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdAlu",
|
||||
"opLat": 1,
|
||||
"name": "opList02",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdAlu",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList02",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdCmp",
|
||||
"opLat": 1,
|
||||
"name": "opList03",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdCmp",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList03",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdCvt",
|
||||
"opLat": 1,
|
||||
"name": "opList04",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdCvt",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList04",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdMisc",
|
||||
"opLat": 1,
|
||||
"name": "opList05",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdMisc",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList05",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdMult",
|
||||
"opLat": 1,
|
||||
"name": "opList06",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdMult",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList06",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdMultAcc",
|
||||
"opLat": 1,
|
||||
"name": "opList07",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdMultAcc",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList07",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdShift",
|
||||
"opLat": 1,
|
||||
"name": "opList08",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdShift",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList08",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdShiftAcc",
|
||||
"opLat": 1,
|
||||
"name": "opList09",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdShiftAcc",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList09",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdSqrt",
|
||||
"opLat": 1,
|
||||
"name": "opList10",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdSqrt",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList10",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdFloatAdd",
|
||||
"opLat": 1,
|
||||
"name": "opList11",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdFloatAdd",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList11",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdFloatAlu",
|
||||
"opLat": 1,
|
||||
"name": "opList12",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdFloatAlu",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList12",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdFloatCmp",
|
||||
"opLat": 1,
|
||||
"name": "opList13",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdFloatCmp",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList13",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdFloatCvt",
|
||||
"opLat": 1,
|
||||
"name": "opList14",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdFloatCvt",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList14",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdFloatDiv",
|
||||
"opLat": 1,
|
||||
"name": "opList15",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdFloatDiv",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList15",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdFloatMisc",
|
||||
"opLat": 1,
|
||||
"name": "opList16",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdFloatMisc",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList16",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdFloatMult",
|
||||
"opLat": 1,
|
||||
"name": "opList17",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdFloatMult",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList17",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdFloatMultAcc",
|
||||
"opLat": 1,
|
||||
"name": "opList18",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdFloatMultAcc",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList18",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "SimdFloatSqrt",
|
||||
"opLat": 1,
|
||||
"name": "opList19",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "SimdFloatSqrt",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList5.opList19",
|
||||
"type": "OpDesc"
|
||||
|
|
@ -2469,11 +2465,11 @@
|
|||
"count": 0,
|
||||
"opList": [
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "MemWrite",
|
||||
"opLat": 1,
|
||||
"name": "opList",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "MemWrite",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList6.opList",
|
||||
"type": "OpDesc"
|
||||
|
|
@ -2489,21 +2485,21 @@
|
|||
"count": 4,
|
||||
"opList": [
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "MemRead",
|
||||
"opLat": 1,
|
||||
"name": "opList0",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "MemRead",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList7.opList0",
|
||||
"type": "OpDesc"
|
||||
},
|
||||
{
|
||||
"issueLat": 1,
|
||||
"opClass": "MemWrite",
|
||||
"opLat": 1,
|
||||
"name": "opList1",
|
||||
"pipelined": true,
|
||||
"eventq_index": 0,
|
||||
"opClass": "MemWrite",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList7.opList1",
|
||||
"type": "OpDesc"
|
||||
|
|
@ -2519,11 +2515,11 @@
|
|||
"count": 1,
|
||||
"opList": [
|
||||
{
|
||||
"issueLat": 3,
|
||||
"opClass": "IprAccess",
|
||||
"opLat": 3,
|
||||
"name": "opList",
|
||||
"pipelined": false,
|
||||
"eventq_index": 0,
|
||||
"opClass": "IprAccess",
|
||||
"cxx_class": "OpDesc",
|
||||
"path": "system.cpu2.fuPool.FUList8.opList",
|
||||
"type": "OpDesc"
|
||||
|
|
|
|||
|
|
@ -30,17 +30,15 @@ Command: 0, Timestamp: 12359, Bank: 3
|
|||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 10918, Bank: 5
|
||||
Command: 0, Timestamp: 10565, Bank: 5
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 7932, Bank: 1
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
Command: 0, Timestamp: 7170, Bank: 1
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 6831, Bank: 2
|
||||
Command: 0, Timestamp: 6448, Bank: 2
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
|
|
@ -54,9 +52,7 @@ Command: 4, Timestamp: 12458, Bank: 0
|
|||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 6838, Bank: 1
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 12183, Bank: 4
|
||||
Command: 0, Timestamp: 7090, Bank: 1
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
|
|
@ -95,10 +91,12 @@ Command: 4, Timestamp: 12458, Bank: 0
|
|||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 10421, Bank: 2
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 9326, Bank: 7
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 6448, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 6590, Bank: 6
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 22 2015 08:10:29
|
||||
gem5 started Apr 22 2015 10:40:08
|
||||
gem5 executing on phenom
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
|
||||
gem5 compiled Jul 6 2015 14:29:04
|
||||
gem5 started Jul 7 2015 09:32:35
|
||||
gem5 executing on e104799-lin
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Reference in a new issue