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@ -1,16 +1,16 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 5.112152 # Number of seconds simulated
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sim_ticks 5112152263500 # Number of ticks simulated
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final_tick 5112152263500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_ticks 5112152301500 # Number of ticks simulated
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final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1496341 # Simulator instruction rate (inst/s)
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host_op_rate 3063337 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 38234881791 # Simulator tick rate (ticks/s)
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host_mem_usage 596704 # Number of bytes of host memory used
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host_seconds 133.70 # Real time elapsed on the host
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sim_insts 200066624 # Number of instructions simulated
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sim_ops 409580050 # Number of ops (including micro ops) simulated
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host_inst_rate 1049184 # Simulator instruction rate (inst/s)
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host_op_rate 2147909 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 26808985343 # Simulator tick rate (ticks/s)
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host_mem_usage 640900 # Number of bytes of host memory used
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host_seconds 190.69 # Real time elapsed on the host
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sim_insts 200066731 # Number of instructions simulated
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sim_ops 409580371 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
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@ -50,38 +50,38 @@ system.physmem.bw_total::pc.south_bridge.ide 5546
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system.physmem.bw_total::total 4061951 # Total bandwidth to/from this memory (bytes/s)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
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system.cpu.numCycles 10224308491 # number of cpu cycles simulated
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system.cpu.numCycles 10224308568 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 200066624 # Number of instructions committed
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system.cpu.committedOps 409580050 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 374583182 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 2308871 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 40001057 # number of instructions that are conditional controls
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system.cpu.num_int_insts 374583182 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 682688853 # number of times the integer registers were read
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system.cpu.num_int_register_writes 323557399 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.committedInsts 200066731 # Number of instructions committed
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system.cpu.committedOps 409580371 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
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system.cpu.num_func_calls 2308877 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 40001070 # number of instructions that are conditional controls
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system.cpu.num_int_insts 374583495 # number of integer instructions
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system.cpu.num_fp_insts 48 # number of float instructions
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system.cpu.num_int_register_reads 682689563 # number of times the integer registers were read
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system.cpu.num_int_register_writes 323557658 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_cc_register_reads 233837170 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 157316360 # number of times the CC registers were written
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system.cpu.num_mem_refs 35666925 # number of memory refs
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system.cpu.num_load_insts 27243229 # Number of load instructions
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system.cpu.num_store_insts 8423696 # Number of store instructions
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system.cpu.num_idle_cycles 9770324986.701103 # Number of idle cycles
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system.cpu.num_busy_cycles 453983504.298896 # Number of busy cycles
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system.cpu.num_cc_register_reads 233837318 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 157316420 # number of times the CC registers were written
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system.cpu.num_mem_refs 35667022 # number of memory refs
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system.cpu.num_load_insts 27243255 # Number of load instructions
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system.cpu.num_store_insts 8423767 # Number of store instructions
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system.cpu.num_idle_cycles 9770324721.656570 # Number of idle cycles
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system.cpu.num_busy_cycles 453983846.343430 # Number of busy cycles
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system.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0.955598 # Percentage of idle cycles
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system.cpu.Branches 43152131 # Number of branches fetched
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system.cpu.op_class::No_OpClass 172748 0.04% 0.04% # Class of executed instruction
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system.cpu.op_class::IntAlu 373476362 91.18% 91.23% # Class of executed instruction
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system.cpu.Branches 43152159 # Number of branches fetched
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system.cpu.op_class::No_OpClass 172754 0.04% 0.04% # Class of executed instruction
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system.cpu.op_class::IntAlu 373476545 91.18% 91.23% # Class of executed instruction
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system.cpu.op_class::IntMult 144577 0.04% 91.26% # Class of executed instruction
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system.cpu.op_class::IntDiv 123058 0.03% 91.29% # Class of executed instruction
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system.cpu.op_class::IntDiv 123078 0.03% 91.29% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
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system.cpu.op_class::FloatCvt 16 0.00% 91.29% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction
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@ -105,18 +105,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl
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system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
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system.cpu.op_class::MemRead 27240640 6.65% 97.94% # Class of executed instruction
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system.cpu.op_class::MemWrite 8423696 2.06% 100.00% # Class of executed instruction
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system.cpu.op_class::MemRead 27240665 6.65% 97.94% # Class of executed instruction
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system.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 409581081 # Class of executed instruction
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system.cpu.op_class::total 409581402 # Class of executed instruction
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
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system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
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system.cpu.dcache.tags.replacements 1621913 # number of replacements
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system.cpu.dcache.tags.replacements 1621902 # number of replacements
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system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use
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system.cpu.dcache.tags.total_refs 20181070 # Total number of references to valid blocks.
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system.cpu.dcache.tags.sampled_refs 1622425 # Sample count of references to valid blocks.
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system.cpu.dcache.tags.avg_refs 12.438831 # Average number of references to valid blocks.
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system.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks.
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system.cpu.dcache.tags.sampled_refs 1622414 # Sample count of references to valid blocks.
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system.cpu.dcache.tags.avg_refs 12.438984 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
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@ -126,48 +126,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 282
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system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.tags.tag_accesses 88836495 # Number of tag accesses
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system.cpu.dcache.tags.data_accesses 88836495 # Number of data accesses
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system.cpu.dcache.ReadReq_hits::cpu.data 12023306 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 12023306 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 8096585 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 8096585 # number of WriteReq hits
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system.cpu.dcache.SoftPFReq_hits::cpu.data 58898 # number of SoftPFReq hits
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system.cpu.dcache.SoftPFReq_hits::total 58898 # number of SoftPFReq hits
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system.cpu.dcache.demand_hits::cpu.data 20119891 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 20119891 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 20178789 # number of overall hits
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system.cpu.dcache.overall_hits::total 20178789 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 905254 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 905254 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 316711 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 316711 # number of WriteReq misses
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system.cpu.dcache.SoftPFReq_misses::cpu.data 402759 # number of SoftPFReq misses
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system.cpu.dcache.SoftPFReq_misses::total 402759 # number of SoftPFReq misses
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system.cpu.dcache.demand_misses::cpu.data 1221965 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 1221965 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 1624724 # number of overall misses
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system.cpu.dcache.overall_misses::total 1624724 # number of overall misses
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system.cpu.dcache.ReadReq_accesses::cpu.data 12928560 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 12928560 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 8413296 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 8413296 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.tags.tag_accesses 88836888 # Number of tag accesses
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system.cpu.dcache.tags.data_accesses 88836888 # Number of data accesses
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system.cpu.dcache.ReadReq_hits::cpu.data 12023339 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 12023339 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 8096662 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 8096662 # number of WriteReq hits
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system.cpu.dcache.SoftPFReq_hits::cpu.data 58900 # number of SoftPFReq hits
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system.cpu.dcache.SoftPFReq_hits::total 58900 # number of SoftPFReq hits
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system.cpu.dcache.demand_hits::cpu.data 20120001 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 20120001 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 20178901 # number of overall hits
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system.cpu.dcache.overall_hits::total 20178901 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 905249 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 905249 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 316707 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 316707 # number of WriteReq misses
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system.cpu.dcache.SoftPFReq_misses::cpu.data 402757 # number of SoftPFReq misses
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system.cpu.dcache.SoftPFReq_misses::total 402757 # number of SoftPFReq misses
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system.cpu.dcache.demand_misses::cpu.data 1221956 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 1221956 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 1624713 # number of overall misses
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system.cpu.dcache.overall_misses::total 1624713 # number of overall misses
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|
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system.cpu.dcache.ReadReq_accesses::cpu.data 12928588 # number of ReadReq accesses(hits+misses)
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|
|
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system.cpu.dcache.ReadReq_accesses::total 12928588 # number of ReadReq accesses(hits+misses)
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|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8413369 # number of WriteReq accesses(hits+misses)
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|
|
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|
system.cpu.dcache.WriteReq_accesses::total 8413369 # number of WriteReq accesses(hits+misses)
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|
|
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|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses)
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system.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses)
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|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 21341856 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 21341856 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 21803513 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 21803513 # number of overall (read+write) accesses
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|
|
|
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070020 # miss rate for ReadReq accesses
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|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.070020 # miss rate for ReadReq accesses
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|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037644 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.037644 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872420 # miss rate for SoftPFReq accesses
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|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872420 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.057257 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.057257 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.074517 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.074517 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 21341957 # number of demand (read+write) accesses
|
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|
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system.cpu.dcache.demand_accesses::total 21341957 # number of demand (read+write) accesses
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|
|
|
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system.cpu.dcache.overall_accesses::cpu.data 21803614 # number of overall (read+write) accesses
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|
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|
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system.cpu.dcache.overall_accesses::total 21803614 # number of overall (read+write) accesses
|
|
|
|
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070019 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.070019 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037643 # miss rate for WriteReq accesses
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|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.037643 # miss rate for WriteReq accesses
|
|
|
|
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system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872416 # miss rate for SoftPFReq accesses
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|
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|
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system.cpu.dcache.SoftPFReq_miss_rate::total 0.872416 # miss rate for SoftPFReq accesses
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|
|
|
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system.cpu.dcache.demand_miss_rate::cpu.data 0.057256 # miss rate for demand accesses
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|
|
|
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system.cpu.dcache.demand_miss_rate::total 0.057256 # miss rate for demand accesses
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|
|
|
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system.cpu.dcache.overall_miss_rate::cpu.data 0.074516 # miss rate for overall accesses
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|
|
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system.cpu.dcache.overall_miss_rate::total 0.074516 # miss rate for overall accesses
|
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|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
@ -176,49 +176,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks::writebacks 1535795 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 1535795 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::writebacks 1535783 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 1535783 # number of writebacks
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.replacements 7755 # number of replacements
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014024 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.total_refs 12942 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.sampled_refs 7769 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.665851 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454103000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014024 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313376 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313376 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.013997 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.total_refs 12940 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.666881 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454141000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013997 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313375 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tag_accesses 52772 # Number of tag accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.data_accesses 52772 # Number of data accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12943 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 12943 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12943 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::total 12943 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12943 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::total 12943 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8962 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 8962 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8962 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::total 8962 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8962 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::total 8962 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21905 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21905 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21905 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 21905 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21905 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 21905 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409130 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409130 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409130 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409130 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409130 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409130 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.tag_accesses 52753 # Number of tag accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.tags.data_accesses 52753 # Number of data accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12941 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 12941 # number of ReadReq hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12941 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_hits::total 12941 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12941 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_hits::total 12941 # number of overall hits
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8957 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 8957 # number of ReadReq misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8957 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_misses::total 8957 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8957 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_misses::total 8957 # number of overall misses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21898 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21898 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21898 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 21898 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21898 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 21898 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409033 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409033 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409033 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409033 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409033 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409033 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
@ -227,16 +227,16 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
|
|
|
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2457 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::total 2457 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2453 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.writebacks::total 2453 # number of writebacks
|
|
|
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.icache.tags.replacements 792213 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 510.662957 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 243675024 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 792725 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 307.389100 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.warmup_cycle 148913080500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.662957 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.replacements 792216 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 243675150 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 792728 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 307.388095 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
|
|
|
@ -245,26 +245,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 130
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.icache.tags.tag_accesses 245260488 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 245260488 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 243675024 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 243675024 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 243675024 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 243675024 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 243675024 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 243675024 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 792732 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 792732 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 792732 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 792732 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 792732 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 792732 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 244467756 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 244467756 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 244467756 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 244467756 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 244467756 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 244467756 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.tags.tag_accesses 245260620 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 245260620 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 243675150 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 243675150 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 243675150 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 243675150 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 243675150 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 243675150 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 792735 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 792735 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 792735 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 792735 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 792735 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 792735 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 244467885 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 244467885 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 244467885 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 244467885 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 244467885 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 244467885 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses
|
|
|
|
|
@ -285,7 +285,7 @@ system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 #
|
|
|
|
|
system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5102144858000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5102144896000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026546 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189159 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189159 # Average percentage of cache occupancy
|
|
|
|
|
@ -336,16 +336,16 @@ system.cpu.itb_walker_cache.writebacks::writebacks 545
|
|
|
|
|
system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks
|
|
|
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.tags.replacements 106219 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 64823.931621 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 3459892 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 3459867 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 170177 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 20.331138 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 20.330991 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109660 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109466 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132289 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2455.813692 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873502 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2455.813677 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873394 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.792375 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
|
|
|
|
@ -359,29 +359,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 32213022 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 32213022 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6661 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 32212786 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 32212786 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6656 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2896 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 779364 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1275206 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 2064127 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1538797 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 1538797 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 779367 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1275199 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 2064118 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 179775 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 179775 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6661 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 179771 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 179771 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 779364 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 1454981 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2243902 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6661 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 779367 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 1454970 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2243889 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 779364 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 1454981 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2243902 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 779367 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 1454970 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2243889 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13355 # number of ReadReq misses
|
|
|
|
|
@ -401,27 +401,27 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 5
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 13355 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 166813 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 180174 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6662 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6657 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2901 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 792719 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307369 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 2109651 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1538797 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 1538797 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 792722 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307362 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 2109642 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314425 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 314425 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6662 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 314421 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6657 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2901 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 792719 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1621794 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2424076 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6662 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 792722 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1621783 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2424063 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6657 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2901 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 792719 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1621794 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2424076 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 792722 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1621783 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016847 # miss rate for ReadReq accesses
|
|
|
|
|
@ -429,17 +429,17 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024601
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.021579 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987972 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987972 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428242 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428242 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428247 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428247 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016847 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102858 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.074327 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016847 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102858 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.074327 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
@ -452,39 +452,39 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|
|
|
|
system.cpu.l2cache.writebacks::writebacks 98110 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 98110 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 15971499 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 15971499 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 15971490 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1538797 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1538781 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 314430 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 314430 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585464 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32527803 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585470 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32527769 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9455 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20381 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 34143103 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50734848 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227551993 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20367 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 34143061 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550521 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730816 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 279337657 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 279335801 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 48002 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4017293 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4017264 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.011855 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.108231 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::3 3969670 98.81% 98.81% # Request fanout histogram
|
|
|
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|
system.cpu.toL2Bus.snoop_fanout::3 3969641 98.81% 98.81% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::4 47623 1.19% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::total 4017293 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::total 4017264 # Request fanout histogram
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system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
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system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
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system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
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@ -545,7 +545,7 @@ system.iocache.tags.tagsinuse 0.042441 # Cy
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system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
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system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks.
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system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.tags.warmup_cycle 4994875215009 # Cycle when the warmup percentage was hit.
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system.iocache.tags.warmup_cycle 4994875253009 # Cycle when the warmup percentage was hit.
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system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor
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system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
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system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
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Nilay Vaish