1361 lines
162 KiB
Text
1361 lines
162 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 5.188464 # Number of seconds simulated
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sim_ticks 5188464227000 # Number of ticks simulated
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final_tick 5188464227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 671592 # Simulator instruction rate (inst/s)
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host_op_rate 1294539 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 27056983658 # Simulator tick rate (ticks/s)
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host_mem_usage 641928 # Number of bytes of host memory used
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host_seconds 191.76 # Real time elapsed on the host
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sim_insts 128784844 # Number of instructions simulated
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sim_ops 248241672 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 828672 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9042304 # Number of bytes read from this memory
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system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9899712 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 828672 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 828672 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 8125568 # Number of bytes written to this memory
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system.physmem.bytes_written::total 8125568 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 12948 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141286 # Number of read requests responded to by this memory
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system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 154683 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 126962 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 126962 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 159714 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1742771 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::pc.south_bridge.ide 5464 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1908024 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 159714 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 159714 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1566083 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1566083 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1566083 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 159714 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1742771 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::pc.south_bridge.ide 5464 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3474107 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 154683 # Number of read requests accepted
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system.physmem.writeReqs 173682 # Number of write requests accepted
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system.physmem.readBursts 154683 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 173682 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 9893504 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue
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system.physmem.bytesWritten 10954816 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 9899712 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 11115648 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 2485 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 1609 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 10173 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9740 # Per bank write bursts
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system.physmem.perBankRdBursts::2 9593 # Per bank write bursts
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system.physmem.perBankRdBursts::3 9430 # Per bank write bursts
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system.physmem.perBankRdBursts::4 10001 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9691 # Per bank write bursts
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system.physmem.perBankRdBursts::6 9399 # Per bank write bursts
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system.physmem.perBankRdBursts::7 9276 # Per bank write bursts
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system.physmem.perBankRdBursts::8 9154 # Per bank write bursts
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system.physmem.perBankRdBursts::9 9223 # Per bank write bursts
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system.physmem.perBankRdBursts::10 9471 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9338 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9899 # Per bank write bursts
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system.physmem.perBankRdBursts::13 10266 # Per bank write bursts
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system.physmem.perBankRdBursts::14 9992 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9940 # Per bank write bursts
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system.physmem.perBankWrBursts::0 11451 # Per bank write bursts
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system.physmem.perBankWrBursts::1 10885 # Per bank write bursts
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system.physmem.perBankWrBursts::2 11361 # Per bank write bursts
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system.physmem.perBankWrBursts::3 10717 # Per bank write bursts
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system.physmem.perBankWrBursts::4 11001 # Per bank write bursts
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system.physmem.perBankWrBursts::5 10578 # Per bank write bursts
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system.physmem.perBankWrBursts::6 10603 # Per bank write bursts
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system.physmem.perBankWrBursts::7 9872 # Per bank write bursts
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system.physmem.perBankWrBursts::8 10400 # Per bank write bursts
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system.physmem.perBankWrBursts::9 10659 # Per bank write bursts
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system.physmem.perBankWrBursts::10 10851 # Per bank write bursts
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system.physmem.perBankWrBursts::11 10912 # Per bank write bursts
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system.physmem.perBankWrBursts::12 10837 # Per bank write bursts
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system.physmem.perBankWrBursts::13 10879 # Per bank write bursts
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system.physmem.perBankWrBursts::14 9964 # Per bank write bursts
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system.physmem.perBankWrBursts::15 10199 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 5188464163500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 154683 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 173682 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 151354 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2788 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::15 2688 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 5143 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 8699 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 9820 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 10213 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 11279 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 11696 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 12708 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 12272 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 12858 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 11610 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 11043 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 9612 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 8840 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 7385 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 7046 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6960 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6830 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 379 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 262 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 234 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 225 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 58562 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 356.003142 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 207.252442 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 358.966719 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 19491 33.28% 33.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 13719 23.43% 56.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 5713 9.76% 66.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 3485 5.95% 72.42% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-639 2346 4.01% 76.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1652 2.82% 79.24% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::768-895 1138 1.94% 81.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1007 1.72% 82.91% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1024-1151 10011 17.09% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 58562 # Bytes accessed per row activation
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|
system.physmem.rdPerTurnAround::samples 6360 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 24.303774 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 600.449814 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-2047 6359 99.98% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 6360 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 6360 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 26.913365 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 21.548238 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 26.273775 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::16-19 4929 77.50% 77.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 43 0.68% 78.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 22 0.35% 78.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 287 4.51% 83.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 171 2.69% 85.72% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 54 0.85% 86.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 36 0.57% 87.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 31 0.49% 87.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 174 2.74% 90.36% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 19 0.30% 90.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 20 0.31% 90.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 9 0.14% 91.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 42 0.66% 91.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 19 0.30% 92.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 8 0.13% 92.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 53 0.83% 93.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 89 1.40% 94.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 11 0.17% 94.61% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 4 0.06% 94.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 14 0.22% 94.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 158 2.48% 97.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 4 0.06% 97.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 9 0.14% 97.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 4 0.06% 97.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 23 0.36% 98.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 5 0.08% 98.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 8 0.13% 98.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 4 0.06% 98.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 28 0.44% 98.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 11 0.17% 98.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 1 0.02% 98.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 9 0.14% 99.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 14 0.22% 99.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 8 0.13% 99.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 4 0.06% 99.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 7 0.11% 99.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-171 2 0.03% 99.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::180-183 3 0.05% 99.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::188-191 4 0.06% 99.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-195 1 0.02% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::200-203 3 0.05% 99.86% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-211 1 0.02% 99.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::212-215 1 0.02% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::216-219 2 0.03% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-227 3 0.05% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 6360 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1439298500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 4337786000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 772930000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 9310.67 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 28060.67 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 127137 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 140055 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 81.81 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 15800904.98 # Average gap between requests
|
|
system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 219436560 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 119732250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 602963400 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 560312640 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 133861007610 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 2995654884750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 3469903395930 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 668.773100 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 4983444491000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 173254120000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 31762771500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 223292160 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 121836000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 602799600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 548862480 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 134523004185 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 2995074186000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 3469979039145 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 668.787680 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 4982479156750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 173254120000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 32730835250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
|
system.cpu.numCycles 10376928454 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 128784844 # Number of instructions committed
|
|
system.cpu.committedOps 248241672 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 232811079 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
|
system.cpu.num_func_calls 2318021 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 23218427 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 232811079 # number of integer instructions
|
|
system.cpu.num_fp_insts 48 # number of float instructions
|
|
system.cpu.num_int_register_reads 436120957 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 198544312 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu.num_cc_register_reads 133281322 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 95783918 # number of times the CC registers were written
|
|
system.cpu.num_mem_refs 22376754 # number of memory refs
|
|
system.cpu.num_load_insts 13962110 # Number of load instructions
|
|
system.cpu.num_store_insts 8414644 # Number of store instructions
|
|
system.cpu.num_idle_cycles 9778737102.998116 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 598191351.001885 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.057646 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.942354 # Percentage of idle cycles
|
|
system.cpu.Branches 26395735 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 172520 0.07% 0.07% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 225434965 90.81% 90.88% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 140546 0.06% 90.94% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 123415 0.05% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 13957123 5.62% 96.61% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 8414644 3.39% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 248243229 # Class of executed instruction
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu.dcache.tags.replacements 1624253 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.996840 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 20159481 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1624765 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 12.407629 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.996840 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 88800329 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 88800329 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 12017170 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 12017170 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8080876 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 8080876 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 59251 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 59251 # number of SoftPFReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 20098046 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 20098046 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 20157297 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 20157297 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 908286 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 908286 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 325792 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 325792 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 402501 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 402501 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1234078 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1234078 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1636579 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1636579 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12749281750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 12749281750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11335230829 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 11335230829 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 24084512579 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 24084512579 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 24084512579 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 24084512579 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 12925456 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 12925456 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8406668 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 8406668 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461752 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 461752 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 21332124 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 21332124 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 21793876 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 21793876 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070271 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.070271 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038754 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.038754 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871682 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.871682 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.057851 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.057851 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.075094 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.075094 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14036.637964 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14036.637964 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34792.845831 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 34792.845831 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19516.199607 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 19516.199607 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14716.376404 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 14716.376404 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 9103 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 96 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.822917 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1540563 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1540563 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9246 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 9246 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 9536 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 9536 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 9536 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 9536 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907996 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 907996 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316546 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 316546 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402467 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 402467 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1224542 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1224542 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1627009 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1627009 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10925755250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10925755250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10200095361 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10200095361 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5340766250 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5340766250 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21125850611 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 21125850611 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26466616861 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 26466616861 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94247525000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94247525000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568413500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568413500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815938500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815938500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070249 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070249 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037654 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037654 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871609 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871609 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057404 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.057404 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074654 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.074654 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.823107 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.823107 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32223.106155 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32223.106155 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.072453 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.072453 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17252.042487 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17252.042487 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16267.037774 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16267.037774 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dtb_walker_cache.tags.replacements 7518 # number of replacements
|
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.053105 # Cycle average of tags in use
|
|
system.cpu.dtb_walker_cache.tags.total_refs 13360 # Total number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.sampled_refs 7533 # Sample count of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.773530 # Average number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5157758038000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053105 # Average occupied blocks per requestor
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315819 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315819 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
|
|
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
|
|
system.cpu.dtb_walker_cache.tags.tag_accesses 52972 # Number of tag accesses
|
|
system.cpu.dtb_walker_cache.tags.data_accesses 52972 # Number of data accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13370 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 13370 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13370 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.demand_hits::total 13370 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13370 # number of overall hits
|
|
system.cpu.dtb_walker_cache.overall_hits::total 13370 # number of overall hits
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8744 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 8744 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8744 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.demand_misses::total 8744 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8744 # number of overall misses
|
|
system.cpu.dtb_walker_cache.overall_misses::total 8744 # number of overall misses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92278000 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92278000 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92278000 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::total 92278000 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92278000 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::total 92278000 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22114 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 22114 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22114 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 22114 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22114 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 22114 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395406 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395406 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395406 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395406 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395406 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395406 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.293687 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.293687 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.293687 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.293687 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2885 # number of writebacks
|
|
system.cpu.dtb_walker_cache.writebacks::total 2885 # number of writebacks
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8744 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8744 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8744 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8744 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8744 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8744 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74789500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74789500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74789500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74789500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74789500 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74789500 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395406 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395406 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395406 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.236505 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 794079 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.347189 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 145115978 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 794591 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 182.629778 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 161164789250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.347189 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.996772 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.996772 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 146705174 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 146705174 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 145115978 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 145115978 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 145115978 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 145115978 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 145115978 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 145115978 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 794598 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 794598 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 794598 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 794598 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 794598 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 794598 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11149966366 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 11149966366 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 11149966366 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 11149966366 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 11149966366 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 11149966366 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 145910576 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 145910576 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 145910576 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 145910576 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 145910576 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 145910576 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005446 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.005446 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.005446 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.005446 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.005446 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.005446 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14032.210459 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14032.210459 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 14032.210459 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 14032.210459 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794598 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 794598 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 794598 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 794598 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 794598 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 794598 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9555900634 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 9555900634 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9555900634 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 9555900634 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9555900634 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 9555900634 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005446 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.005446 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.005446 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.081911 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.081911 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements
|
|
system.cpu.itb_walker_cache.tags.tagsinuse 3.069566 # Cycle average of tags in use
|
|
system.cpu.itb_walker_cache.tags.total_refs 7987 # Total number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.sampled_refs 3486 # Sample count of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.avg_refs 2.291165 # Average number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5161163241000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069566 # Average occupied blocks per requestor
|
|
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191848 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.tags.occ_percent::total 0.191848 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
|
|
system.cpu.itb_walker_cache.tags.tag_accesses 28991 # Number of tag accesses
|
|
system.cpu.itb_walker_cache.tags.data_accesses 28991 # Number of data accesses
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7985 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 7985 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7987 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.demand_hits::total 7987 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7987 # number of overall hits
|
|
system.cpu.itb_walker_cache.overall_hits::total 7987 # number of overall hits
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4339 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 4339 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4339 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.demand_misses::total 4339 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4339 # number of overall misses
|
|
system.cpu.itb_walker_cache.overall_misses::total 4339 # number of overall misses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42562750 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42562750 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42562750 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::total 42562750 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42562750 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::total 42562750 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 12324 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12326 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.demand_accesses::total 12326 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12326 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::total 12326 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352077 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352077 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352020 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total 0.352020 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352020 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total 0.352020 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9809.345471 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9809.345471 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9809.345471 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9809.345471 # average overall miss latency
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 618 # number of writebacks
|
|
system.cpu.itb_walker_cache.writebacks::total 618 # number of writebacks
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4339 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4339 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4339 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::total 4339 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4339 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::total 4339 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33883250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33883250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33883250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33883250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33883250 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33883250 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352077 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352077 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352020 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352020 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7808.999770 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 87360 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 64748.911122 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3495788 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 152066 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 22.988623 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 50325.123938 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006393 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141290 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.854795 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 11198.784706 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.767900 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049207 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.170880 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.987990 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64706 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2949 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5093 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56562 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987335 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 32257665 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 32257665 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6357 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2756 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 781636 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1281044 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2071793 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1544066 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1544066 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 200764 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 200764 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6357 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 2756 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 781636 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1481808 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2272557 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6357 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 2756 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 781636 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1481808 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2272557 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12949 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 28624 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 41579 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1347 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 1347 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 113593 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 113593 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 12949 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 142217 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 155172 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 12949 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 142217 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 155172 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 405750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 944829500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2144751500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 3090076000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16383859 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 16383859 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7839721470 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7839721470 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 405750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 944829500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9984472970 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 10929797470 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 405750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 944829500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9984472970 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 10929797470 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6358 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2761 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 794585 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1309668 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2113372 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1544066 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1544066 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1668 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1668 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314357 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 314357 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6358 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2761 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 794585 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1624025 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2427729 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6358 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2761 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 794585 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1624025 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2427729 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000157 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001811 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021856 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.019674 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807554 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807554 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361350 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.361350 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000157 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001811 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087571 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.063917 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000157 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001811 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087571 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.063917 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81150 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72965.441347 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74928.434181 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74318.189471 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12163.221232 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12163.221232 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69015.885398 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69015.885398 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 70436.660416 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 70436.660416 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 80295 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 80295 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12949 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28624 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 41579 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1347 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1347 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113593 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 113593 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12949 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 142217 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 155172 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12949 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 142217 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 155172 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 342750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 782620000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1786397500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2569436500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14401829 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14401829 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6419846030 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6419846030 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 342750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 782620000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8206243530 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 8989282530 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 342750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 782620000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8206243530 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 8989282530 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86686810500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86686810500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088095000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088095000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021856 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019674 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807554 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807554 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361350 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361350 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063917 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063917 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68550 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60438.643911 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62409.079793 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61796.495827 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.780995 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.780995 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56516.211650 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56516.211650 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2700583 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2700055 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 13918 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1544066 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2197 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2197 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 314362 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 314362 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589183 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5984618 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7718 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17987 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 7599506 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50853440 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204220931 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 216256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 591552 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 255882179 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 53190 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4026335 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.011814 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.108047 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 3978769 98.82% 98.82% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 47566 1.18% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 4026335 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3838165000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 477000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1194331866 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3057201859 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 6509250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 13116250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 230298 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 230298 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 11006 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
|
system.iobus.trans_dist::MessageReq 1653 # Transaction distribution
|
|
system.iobus.trans_dist::MessageResp 1653 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 579354 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 3280662 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 448396611 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 52232002 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 47511 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 5045849712000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 428094 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 428094 # Number of data accesses
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 846 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 846 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses
|
|
system.iocache.overall_misses::total 846 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144419686 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 144419686 # number of ReadReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361743923 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::total 12361743923 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.demand_miss_latency::pc.south_bridge.ide 144419686 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 144419686 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::pc.south_bridge.ide 144419686 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 144419686 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 170708.848700 # average ReadReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264592.121640 # average WriteInvalidateReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::total 264592.121640 # average WriteInvalidateReq miss latency
|
|
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 170708.848700 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 170708.848700 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 70486 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 9156 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 7.698340 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
|
system.iocache.writebacks::total 46667 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 100401686 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9932299927 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9932299927 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 100401686 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 100401686 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 118678.115839 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212592.036109 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212592.036109 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 624018 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 624018 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 13918 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 13918 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 126962 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 1627 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 113313 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 113313 # Transaction distribution
|
|
system.membus.trans_dist::MessageReq 1653 # Transaction distribution
|
|
system.membus.trans_dist::MessageResp 1653 # Transaction distribution
|
|
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393192 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584214 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141396 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 141396 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1728916 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15010240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16677187 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22688919 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 1602 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 331576 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 331576 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 331576 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 257309000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 358083500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer3.occupancy 1729903000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks)
|
|
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 2619799141 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer4.occupancy 54348998 # Layer occupancy (ticks)
|
|
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
|
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
|
|
|
---------- End Simulation Statistics ----------
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