2011-04-25 23:18:08 +02:00
---------- Begin Simulation Statistics ----------
2016-03-16 21:03:49 +01:00
sim_seconds 0.403557 # Number of seconds simulated
sim_ticks 403557300500 # Number of ticks simulated
final_tick 403557300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-04-25 23:18:08 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-03-16 21:03:49 +01:00
host_inst_rate 114335 # Simulator instruction rate (inst/s)
host_op_rate 211418 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 55801045 # Simulator tick rate (ticks/s)
host_mem_usage 368712 # Number of bytes of host memory used
host_seconds 7232.07 # Real time elapsed on the host
2012-08-15 16:38:05 +02:00
sim_insts 826877109 # Number of instructions simulated
2013-03-11 23:45:09 +01:00
sim_ops 1528988701 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-03-16 21:03:49 +01:00
system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24544448 # Number of bytes read from this memory
system.physmem.bytes_read::total 24708032 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18888768 # Number of bytes written to this memory
system.physmem.bytes_written::total 18888768 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 383507 # Number of read requests responded to by this memory
system.physmem.num_reads::total 386063 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 295137 # Number of write requests responded to by this memory
system.physmem.num_writes::total 295137 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 405355 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 60820230 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 61225585 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 405355 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 405355 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 46805665 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 46805665 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 46805665 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 405355 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 60820230 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 108031251 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 386063 # Number of read requests accepted
system.physmem.writeReqs 295137 # Number of write requests accepted
system.physmem.readBursts 386063 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 295137 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 24688384 # Total number of bytes read from DRAM
2016-02-10 10:08:27 +01:00
system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
2016-03-16 21:03:49 +01:00
system.physmem.bytesWritten 18886848 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 24708032 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18888768 # Total written bytes from the system interface side
2016-02-10 10:08:27 +01:00
system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-03-16 21:03:49 +01:00
system.physmem.perBankRdBursts::0 24073 # Per bank write bursts
system.physmem.perBankRdBursts::1 26429 # Per bank write bursts
system.physmem.perBankRdBursts::2 24836 # Per bank write bursts
system.physmem.perBankRdBursts::3 24494 # Per bank write bursts
system.physmem.perBankRdBursts::4 23227 # Per bank write bursts
system.physmem.perBankRdBursts::5 23706 # Per bank write bursts
system.physmem.perBankRdBursts::6 24492 # Per bank write bursts
system.physmem.perBankRdBursts::7 24304 # Per bank write bursts
system.physmem.perBankRdBursts::8 23632 # Per bank write bursts
system.physmem.perBankRdBursts::9 23534 # Per bank write bursts
system.physmem.perBankRdBursts::10 24801 # Per bank write bursts
system.physmem.perBankRdBursts::11 23978 # Per bank write bursts
system.physmem.perBankRdBursts::12 23332 # Per bank write bursts
system.physmem.perBankRdBursts::13 22938 # Per bank write bursts
system.physmem.perBankRdBursts::14 24084 # Per bank write bursts
system.physmem.perBankRdBursts::15 23896 # Per bank write bursts
system.physmem.perBankWrBursts::0 18613 # Per bank write bursts
system.physmem.perBankWrBursts::1 19937 # Per bank write bursts
system.physmem.perBankWrBursts::2 19197 # Per bank write bursts
2015-12-02 15:58:24 +01:00
system.physmem.perBankWrBursts::3 19026 # Per bank write bursts
2016-03-16 21:03:49 +01:00
system.physmem.perBankWrBursts::4 18109 # Per bank write bursts
system.physmem.perBankWrBursts::5 18508 # Per bank write bursts
system.physmem.perBankWrBursts::6 19135 # Per bank write bursts
system.physmem.perBankWrBursts::7 19091 # Per bank write bursts
system.physmem.perBankWrBursts::8 18652 # Per bank write bursts
system.physmem.perBankWrBursts::9 17959 # Per bank write bursts
system.physmem.perBankWrBursts::10 18920 # Per bank write bursts
system.physmem.perBankWrBursts::11 17762 # Per bank write bursts
system.physmem.perBankWrBursts::12 17406 # Per bank write bursts
system.physmem.perBankWrBursts::13 17012 # Per bank write bursts
system.physmem.perBankWrBursts::14 17899 # Per bank write bursts
system.physmem.perBankWrBursts::15 17881 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2013-11-27 00:05:25 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-03-16 21:03:49 +01:00
system.physmem.totGap 403557258500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-03-16 21:03:49 +01:00
system.physmem.readPktSize::6 386063 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-03-16 21:03:49 +01:00
system.physmem.writePktSize::6 295137 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 380830 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4573 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 303 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
2013-03-28 00:36:21 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.wrQLenPdf::15 6160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6563 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 16932 # What write queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.wrQLenPdf::19 17644 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 17643 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17657 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 17710 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17665 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 17732 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 17685 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17778 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17778 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17761 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 17921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17612 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 17541 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
2015-12-02 15:58:24 +01:00
system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
2016-02-10 10:08:27 +01:00
system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2016-03-16 21:03:49 +01:00
system.physmem.bytesPerActivate::samples 146836 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 296.749026 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 175.460690 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 322.805815 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 54147 36.88% 36.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 39842 27.13% 64.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 13777 9.38% 73.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7669 5.22% 78.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5515 3.76% 82.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3906 2.66% 85.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2997 2.04% 87.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2808 1.91% 88.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16175 11.02% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 146836 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17510 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 22.029754 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 217.905540 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 17500 99.94% 99.94% # Reads before turning the bus around for writes
2015-11-16 12:08:57 +01:00
system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
2014-06-22 23:33:09 +02:00
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
2016-03-16 21:03:49 +01:00
system.physmem.rdPerTurnAround::total 17510 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17510 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.853626 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.775847 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.814458 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 17322 98.93% 98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 130 0.74% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 32 0.18% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 9 0.05% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 1 0.01% 99.91% # Writes before turning the bus around for reads
2016-02-10 10:08:27 +01:00
system.physmem.wrPerTurnAround::36-39 3 0.02% 99.93% # Writes before turning the bus around for reads
2015-11-16 12:08:57 +01:00
system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads
2016-02-10 10:08:27 +01:00
system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads
2016-02-10 10:08:27 +01:00
system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads
2015-09-25 13:27:03 +02:00
system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
2015-09-25 13:27:03 +02:00
system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads
2016-03-16 21:03:49 +01:00
system.physmem.wrPerTurnAround::total 17510 # Writes before turning the bus around for reads
system.physmem.totQLat 4294664500 # Total ticks spent queuing
system.physmem.totMemAccLat 11527589500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1928780000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11133.11 # Average queueing delay per DRAM burst
2015-04-30 05:35:23 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-03-16 21:03:49 +01:00
system.physmem.avgMemAccLat 29883.11 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 61.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 46.80 # Average achieved write bandwidth in MiByte/s
2016-02-10 10:08:27 +01:00
system.physmem.avgRdBWSys 61.23 # Average system read bandwidth in MiByte/s
2016-03-16 21:03:49 +01:00
system.physmem.avgWrBWSys 46.81 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-09-15 15:14:09 +02:00
system.physmem.busUtil 0.84 # Data bus utilization in percentage
system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads
2015-11-06 09:26:50 +01:00
system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes
2015-09-15 15:14:09 +02:00
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
2016-03-16 21:03:49 +01:00
system.physmem.avgWrQLen 21.17 # Average write queue length when enqueuing
system.physmem.readRowHits 318250 # Number of row buffer hits during reads
system.physmem.writeRowHits 215762 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes
system.physmem.avgGap 592421.11 # Average gap between requests
system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 567929880 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 309882375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1525258800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 982361520 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 26358156240 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 62125312320 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 187636398750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 279505299885 # Total energy per rank (pJ)
system.physmem_0.averagePower 692.609739 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 311602147750 # Time in different power states
system.physmem_0.memoryStateTime::REF 13475540000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-03-16 21:03:49 +01:00
system.physmem_0.memoryStateTime::ACT 78476140500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-03-16 21:03:49 +01:00
system.physmem_1.actEnergy 541832760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 295642875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1483138800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 929594880 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 26358156240 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 60415771455 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 189135996000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 279160133010 # Total energy per rank (pJ)
system.physmem_1.averagePower 691.754421 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 314107658000 # Time in different power states
system.physmem_1.memoryStateTime::REF 13475540000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-03-16 21:03:49 +01:00
system.physmem_1.memoryStateTime::ACT 75970627000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-03-16 21:03:49 +01:00
system.cpu.branchPred.lookups 219252380 # Number of BP lookups
system.cpu.branchPred.condPredicted 219252380 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 8528271 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 123973177 # Number of BTB lookups
system.cpu.branchPred.BTBHits 121800120 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-03-16 21:03:49 +01:00
system.cpu.branchPred.BTBHitPct 98.247156 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 27061903 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1407355 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-01-24 22:29:33 +01:00
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 551 # Number of system calls
2016-03-16 21:03:49 +01:00
system.cpu.numCycles 807114602 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-03-16 21:03:49 +01:00
system.cpu.fetch.icacheStallCycles 175891157 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1208567118 # Number of instructions fetch has processed
system.cpu.fetch.Branches 219252380 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 148862023 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 621375374 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 17762469 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 90709 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 718160 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1191 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 170755406 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2320013 # Number of outstanding Icache misses that were squashed
2015-11-06 09:26:50 +01:00
system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
2016-03-16 21:03:49 +01:00
system.cpu.fetch.rateDist::samples 806958068 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.786744 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.368251 # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-03-16 21:03:49 +01:00
system.cpu.fetch.rateDist::0 417094848 51.69% 51.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 32452037 4.02% 55.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 31902781 3.95% 59.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 32612026 4.04% 63.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 26524373 3.29% 66.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 26910367 3.33% 70.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 35157617 4.36% 74.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 31335613 3.88% 78.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 172968406 21.43% 100.00% # Number of instructions fetched each cycle (Total)
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-03-16 21:03:49 +01:00
system.cpu.fetch.rateDist::total 806958068 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.271650 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.497392 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 120421699 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 370368413 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 225215938 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 82070784 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 8881234 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2132047991 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 8881234 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 152579592 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 150649676 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 43646 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 271398208 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 223405712 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2088421237 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 135982 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 138413157 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 24833190 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 50057898 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 2190635347 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5277929489 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3356932236 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 59989 # Number of floating rename lookups
2013-03-11 23:45:09 +01:00
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
2016-03-16 21:03:49 +01:00
system.cpu.rename.UndoneMaps 576594493 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3330 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 3150 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 422929221 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 507109788 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 200805340 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 229274294 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 68310404 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2023046060 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27646 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1788955161 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 413315 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 494085005 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 832817551 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 27094 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 806958068 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.216912 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.070634 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-03-16 21:03:49 +01:00
system.cpu.iq.issued_per_cycle::0 238363650 29.54% 29.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 123779759 15.34% 44.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 118420990 14.67% 59.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 107850309 13.37% 72.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 89928227 11.14% 84.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 60113985 7.45% 91.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 42280336 5.24% 96.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 18948850 2.35% 99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 7271962 0.90% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-03-16 21:03:49 +01:00
system.cpu.iq.issued_per_cycle::total 806958068 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-03-16 21:03:49 +01:00
system.cpu.iq.fu_full::IntAlu 11501801 42.82% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.82% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 12260611 45.64% 88.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 3099977 11.54% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-03-16 21:03:49 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2718189 0.15% 0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1183067002 66.13% 66.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 368893 0.02% 66.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 3881187 0.22% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued
2016-03-16 21:03:49 +01:00
system.cpu.iq.FU_type_0::FloatMult 38 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 395 0.00% 66.52% # Type of FU issued
2015-09-15 15:14:09 +02:00
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued
2016-03-16 21:03:49 +01:00
system.cpu.iq.FU_type_0::MemRead 428511642 23.95% 90.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170407678 9.53% 100.00% # Type of FU issued
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-03-16 21:03:49 +01:00
system.cpu.iq.FU_type_0::total 1788955161 # Type of FU issued
system.cpu.iq.rate 2.216482 # Inst issue rate
system.cpu.iq.fu_busy_cnt 26862389 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.015016 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4412114486 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2517408815 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1762314892 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 29608 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 69342 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 5559 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1813086388 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 12973 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 185891278 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-03-16 21:03:49 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 123009946 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 214354 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 373061 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 51645154 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-03-16 21:03:49 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 23005 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1152 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-03-16 21:03:49 +01:00
system.cpu.iew.iewSquashCycles 8881234 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 97675937 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 6156450 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2023073706 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 372553 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 507112103 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 200805340 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 12025 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1859445 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3396246 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 373061 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4843605 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4134020 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8977625 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1769939059 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 423109380 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 19016102 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
2016-03-16 21:03:49 +01:00
system.cpu.iew.exec_refs 590326143 # number of memory reference insts executed
system.cpu.iew.exec_branches 168971977 # Number of branches executed
system.cpu.iew.exec_stores 167216763 # Number of stores executed
system.cpu.iew.exec_rate 2.192922 # Inst execution rate
system.cpu.iew.wb_sent 1766810354 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1762320451 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1339786199 # num instructions producing a value
system.cpu.iew.wb_consumers 2050074397 # num instructions consuming a value
system.cpu.iew.wb_rate 2.183482 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.653531 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 494145922 # The number of squashed insts skipped by commit
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
2016-03-16 21:03:49 +01:00
system.cpu.commit.branchMispredicts 8608481 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 739768084 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.066849 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.575796 # Number of insts commited each cycle
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-03-16 21:03:49 +01:00
system.cpu.commit.committed_per_cycle::0 275719169 37.27% 37.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 172002982 23.25% 60.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 56035372 7.57% 68.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 86287676 11.66% 79.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 25889173 3.50% 83.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 26492883 3.58% 86.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 9844270 1.33% 88.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9007252 1.22% 89.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 78489307 10.61% 100.00% # Number of insts commited each cycle
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-03-16 21:03:49 +01:00
system.cpu.commit.committed_per_cycle::total 739768084 # Number of insts commited each cycle
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
2013-03-11 23:45:09 +01:00
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 533262343 # Number of memory references committed
system.cpu.commit.loads 384102157 # Number of loads committed
2011-04-25 23:18:08 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 149758583 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
2013-10-16 16:44:12 +02:00
system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
2016-03-16 21:03:49 +01:00
system.cpu.commit.bw_lim_events 78489307 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 2684413400 # The number of ROB reads
system.cpu.rob.rob_writes 4113633509 # The number of ROB writes
system.cpu.timesIdled 1975 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 156534 # Total number of cycles that the CPU has spent unscheduled due to idling
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
2013-03-11 23:45:09 +01:00
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
2016-03-16 21:03:49 +01:00
system.cpu.cpi 0.976100 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.976100 # CPI: Total CPI of All Threads
system.cpu.ipc 1.024485 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.024485 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2722552264 # number of integer regfile reads
system.cpu.int_regfile_writes 1435774618 # number of integer regfile writes
system.cpu.fp_regfile_reads 5765 # number of floating regfile reads
system.cpu.fp_regfile_writes 491 # number of floating regfile writes
system.cpu.cc_regfile_reads 596650045 # number of cc regfile reads
system.cpu.cc_regfile_writes 405459285 # number of cc regfile writes
system.cpu.misc_regfile_reads 971600702 # number of misc regfile reads
2013-03-11 23:45:09 +01:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
2016-03-16 21:03:49 +01:00
system.cpu.dcache.tags.replacements 2530810 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.810337 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 382026213 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2534906 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 150.706264 # Average number of references to valid blocks.
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit.
2016-03-16 21:03:49 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.810337 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
2016-03-16 21:03:49 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3177 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-03-16 21:03:49 +01:00
system.cpu.dcache.tags.tag_accesses 773143076 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 773143076 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 233377627 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 233377627 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148173651 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148173651 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 381551278 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 381551278 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 381551278 # number of overall hits
system.cpu.dcache.overall_hits::total 381551278 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2766256 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2766256 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 986551 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 986551 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3752807 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3752807 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3752807 # number of overall misses
system.cpu.dcache.overall_misses::total 3752807 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 58648858500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 58648858500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 30791929995 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 30791929995 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 89440788495 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 89440788495 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 89440788495 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 89440788495 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 236143883 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 236143883 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
2016-03-16 21:03:49 +01:00
system.cpu.dcache.demand_accesses::cpu.data 385304085 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 385304085 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 385304085 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 385304085 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011714 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.011714 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006614 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006614 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009740 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009740 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009740 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009740 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21201.529613 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21201.529613 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31211.696096 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31211.696096 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23833.037109 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23833.037109 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23833.037109 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23833.037109 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 10234 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1094 # number of cycles access was blocked
2015-12-02 15:58:24 +01:00
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
2016-03-16 21:03:49 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.354662 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2016-03-16 21:03:49 +01:00
system.cpu.dcache.writebacks::writebacks 2330455 # number of writebacks
system.cpu.dcache.writebacks::total 2330455 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1001445 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1001445 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19420 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 19420 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1020865 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1020865 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1020865 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1020865 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764811 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1764811 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967131 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 967131 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2731942 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2731942 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2731942 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2731942 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33568096500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33568096500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29570460997 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 29570460997 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63138557497 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 63138557497 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63138557497 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 63138557497 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007473 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007473 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006484 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006484 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.007090 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.007090 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19020.788345 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19020.788345 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30575.445309 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30575.445309 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23111.236438 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23111.236438 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23111.236438 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23111.236438 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-16 21:03:49 +01:00
system.cpu.icache.tags.replacements 6689 # number of replacements
system.cpu.icache.tags.tagsinuse 1037.520443 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 170544686 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 8296 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 20557.459740 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-03-16 21:03:49 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1037.520443 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.506602 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.506602 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
2016-03-16 21:03:49 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
2016-02-10 10:08:27 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
2016-03-16 21:03:49 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 323 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1154 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 341716240 # Number of tag accesses
system.cpu.icache.tags.data_accesses 341716240 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 170547776 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 170547776 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 170547776 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 170547776 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 170547776 # number of overall hits
system.cpu.icache.overall_hits::total 170547776 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 207629 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 207629 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 207629 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 207629 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 207629 # number of overall misses
system.cpu.icache.overall_misses::total 207629 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1204990000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1204990000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1204990000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1204990000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1204990000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1204990000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 170755405 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 170755405 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 170755405 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 170755405 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 170755405 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 170755405 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001216 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001216 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001216 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001216 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001216 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001216 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5803.572719 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 5803.572719 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 5803.572719 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 5803.572719 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 5803.572719 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 5803.572719 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 923 # number of cycles access was blocked
2015-07-18 22:07:35 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-03-16 21:03:49 +01:00
system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
2015-07-18 22:07:35 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-03-16 21:03:49 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked
2015-07-18 22:07:35 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2016-03-16 21:03:49 +01:00
system.cpu.icache.writebacks::writebacks 6689 # number of writebacks
system.cpu.icache.writebacks::total 6689 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2197 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2197 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2197 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2197 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2197 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2197 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205432 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 205432 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 205432 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 205432 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 205432 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 205432 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915620000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 915620000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915620000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 915620000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915620000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 915620000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001203 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001203 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001203 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4457.046614 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4457.046614 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4457.046614 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 4457.046614 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4457.046614 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 4457.046614 # average overall mshr miss latency
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-16 21:03:49 +01:00
system.cpu.l2cache.tags.replacements 355320 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29620.939989 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3892489 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 387653 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.041168 # Average number of references to valid blocks.
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.tags.warmup_cycle 189331361500 # Cycle when the warmup percentage was hit.
2016-03-16 21:03:49 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 21024.490956 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.822585 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8409.626448 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.641617 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005701 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.256641 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.903959 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32333 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13412 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18612 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986725 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 43293695 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 43293695 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 2330455 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 2330455 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6282 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 6282 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1842 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1842 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 563562 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 563562 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5713 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 5713 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587786 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 1587786 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 5713 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2151348 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2157061 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 5713 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2151348 # number of overall hits
system.cpu.l2cache.overall_hits::total 2157061 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 195194 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 195194 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 206925 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206925 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2558 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2558 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176633 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 176633 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2558 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 383558 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 386116 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2558 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 383558 # number of overall misses
system.cpu.l2cache.overall_misses::total 386116 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12720000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 12720000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16418152000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16418152000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 210152000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 210152000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14200919500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 14200919500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 210152000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 30619071500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 30829223500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 210152000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 30619071500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 30829223500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330455 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 2330455 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 6282 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 6282 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 197036 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 197036 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 770487 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 770487 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8271 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 8271 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764419 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 1764419 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 8271 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2534906 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2543177 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 8271 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2534906 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2543177 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990651 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990651 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268564 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.268564 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.309273 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.309273 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100108 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100108 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.309273 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.151311 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.151824 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.309273 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.151311 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151824 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 65.165937 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 65.165937 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79343.491603 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79343.491603 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82154.808444 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82154.808444 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80397.884314 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80397.884314 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82154.808444 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79829.051930 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79844.459955 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82154.808444 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79829.051930 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79844.459955 # average overall miss latency
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2016-03-16 21:03:49 +01:00
system.cpu.l2cache.writebacks::writebacks 295137 # number of writebacks
system.cpu.l2cache.writebacks::total 295137 # number of writebacks
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses
2016-03-16 21:03:49 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195194 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 195194 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206925 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206925 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176633 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176633 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 383558 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 386115 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 383558 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 386115 # number of overall MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3766618491 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3766618491 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14348902000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14348902000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184524501 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184524501 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12434572036 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12434572036 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184524501 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26783474036 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26967998537 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184524501 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26783474036 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26967998537 # number of overall MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-03-16 21:03:49 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990651 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990651 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268564 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268564 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.309152 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.309152 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100108 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100108 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.309152 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151311 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151824 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.309152 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151311 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151824 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19296.794425 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19296.794425 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69343.491603 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69343.491603 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72164.450919 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72164.450919 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70397.785442 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70397.785442 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72164.450919 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69829.006398 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69844.472598 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72164.450919 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69829.006398 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69844.472598 # average overall mshr miss latency
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-03-16 21:03:49 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 5474873 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2731236 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 212343 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 3595 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3595 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-03-16 21:03:49 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 1969849 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 2625592 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 6689 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 260538 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 197036 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 197036 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 770487 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 770487 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 205432 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764419 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220390 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7994694 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8215084 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311383104 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 312340416 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 552481 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3292694 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.124385 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.330020 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-16 21:03:49 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2883132 87.56% 87.56% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 409562 12.44% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-03-16 21:03:49 +01:00
system.cpu.toL2Bus.snoop_fanout::total 3292694 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5103271503 # Layer occupancy (ticks)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 308149990 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3900879073 # Layer occupancy (ticks)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.membus.trans_dist::ReadResp 179188 # Transaction distribution
system.membus.trans_dist::WritebackDirty 295137 # Transaction distribution
system.membus.trans_dist::CleanEvict 56656 # Transaction distribution
system.membus.trans_dist::UpgradeReq 195245 # Transaction distribution
system.membus.trans_dist::ReadExReq 206874 # Transaction distribution
system.membus.trans_dist::ReadExResp 206874 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 179189 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1319163 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1319163 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1319163 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43596736 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43596736 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43596736 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-03-16 21:03:49 +01:00
system.membus.snoop_fanout::samples 933101 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-03-16 21:03:49 +01:00
system.membus.snoop_fanout::0 933101 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-03-16 21:03:49 +01:00
system.membus.snoop_fanout::total 933101 # Request fanout histogram
system.membus.reqLayer0.occupancy 2242999911 # Layer occupancy (ticks)
2015-09-15 15:14:09 +02:00
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
2016-03-16 21:03:49 +01:00
system.membus.respLayer1.occupancy 2042259250 # Layer occupancy (ticks)
2016-02-10 10:08:27 +01:00
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
2011-04-25 23:18:08 +02:00
---------- End Simulation Statistics ----------
