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gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

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stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
---------- Begin Simulation Statistics ----------
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
sim_seconds 0.458275 # Number of seconds simulated
sim_ticks 458275427000 # Number of ticks simulated
final_tick 458275427000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
host_inst_rate 66021 # Simulator instruction rate (inst/s)
host_op_rate 122081 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36590577 # Simulator tick rate (ticks/s)
host_mem_usage 346580 # Number of bytes of host memory used
host_seconds 12524.41 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 826877109 # Number of instructions simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
sim_ops 1528988701 # Number of ops (including micro ops) simulated
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24473408 # Number of bytes read from this memory
system.physmem.bytes_read::total 24676160 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18786624 # Number of bytes written to this memory
system.physmem.bytes_written::total 18786624 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 382397 # Number of read requests responded to by this memory
system.physmem.num_reads::total 385565 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293541 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293541 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 442424 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 53403274 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 53845697 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 442424 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 442424 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 40994177 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 40994177 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 40994177 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 442424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 53403274 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 94839875 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 385565 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 293541 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 385565 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 293541 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 24676160 # Total number of bytes read from memory
system.physmem.bytesWritten 18786624 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 24676160 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 18786624 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 130355 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 26434 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 24675 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 24503 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 23237 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 23662 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 24409 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 24202 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 23617 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 23804 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 24780 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 24047 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 23248 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 22961 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 23770 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 23994 # Track reads on a per bank basis
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.perBankWrReqs::0 18525 # Track writes on a per bank basis
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 18939 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 18911 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 18030 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 18408 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 18975 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 18939 # Track writes on a per bank basis
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.perBankWrReqs::8 18544 # Track writes on a per bank basis
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.perBankWrReqs::9 18098 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 17702 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 16955 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 17708 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 17829 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.totGap 458275318500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.readPktSize::6 385565 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.writePktSize::6 293541 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 380824 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4248 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 296 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.wrQLenPdf::0 12718 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 12731 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 12737 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 12739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 12742 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 12745 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 12747 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 12749 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 12763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 12763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 12763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 12763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 12763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 12763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 12762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 12762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 12762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 12762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 12762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 12762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 12762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 12762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.wrQLenPdf::24 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytesPerActivate::samples 125751 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 345.531089 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 162.070662 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 668.026506 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 53960 42.91% 42.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 23382 18.59% 61.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 10554 8.39% 69.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 6402 5.09% 74.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 3989 3.17% 78.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 2874 2.29% 80.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 2122 1.69% 82.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 1769 1.41% 83.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 1442 1.15% 84.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 1166 0.93% 85.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 1242 0.99% 86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 1075 0.85% 87.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 727 0.58% 88.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 689 0.55% 88.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 609 0.48% 89.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 572 0.45% 89.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 523 0.42% 89.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 500 0.40% 90.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 598 0.48% 90.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 763 0.61% 91.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 633 0.50% 91.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 692 0.55% 92.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 6202 4.93% 97.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 529 0.42% 97.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 343 0.27% 98.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 283 0.23% 98.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 212 0.17% 98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 156 0.12% 98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 148 0.12% 98.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 111 0.09% 98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 101 0.08% 98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 82 0.07% 98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 91 0.07% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 56 0.04% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 52 0.04% 99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 46 0.04% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 44 0.03% 99.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 29 0.02% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 32 0.03% 99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 22 0.02% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 18 0.01% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 15 0.01% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 19 0.02% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 11 0.01% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 25 0.02% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 22 0.02% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 17 0.01% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 13 0.01% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 10 0.01% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 18 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 10 0.01% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 20 0.02% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 6 0.00% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 12 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 10 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 13 0.01% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 9 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 10 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841 10 0.01% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 9 0.01% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 5 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 10 0.01% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417 4 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 8 0.01% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673 3 0.00% 99.56% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::4736-4737 5 0.00% 99.56% # Bytes accessed per row activation
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytesPerActivate::4800-4801 7 0.01% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 3 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 2 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 6 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 5 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 8 0.01% 99.59% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytesPerActivate::5312-5313 3 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 8 0.01% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633 4 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.62% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::5824-5825 5 0.00% 99.62% # Bytes accessed per row activation
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 4 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145 6 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.64% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.64% # Bytes accessed per row activation
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 3 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529 3 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657 7 0.01% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.67% # Bytes accessed per row activation
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.68% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.68% # Bytes accessed per row activation
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.70% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.70% # Bytes accessed per row activation
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytesPerActivate::8128-8129 3 0.00% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 378 0.30% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 125751 # Bytes accessed per row activation
system.physmem.totQLat 3033779750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11207673500 # Sum of mem lat for all requests
system.physmem.totBusLat 1927035000 # Total cycles spent in databus access
system.physmem.totBankLat 6246858750 # Total cycles spent in bank access
system.physmem.avgQLat 7871.63 # Average queueing delay per request
system.physmem.avgBankLat 16208.47 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.avgMemAccLat 29080.10 # Average memory access latency
system.physmem.avgRdBW 53.85 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 40.99 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 53.85 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 40.99 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.busUtil 0.74 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.avgWrQLen 10.19 # Average write queue length over time
system.physmem.readRowHits 346237 # Number of row buffer hits during reads
system.physmem.writeRowHits 206945 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 70.50 # Row buffer hit rate for writes
system.physmem.avgGap 674821.48 # Average gap between requests
system.membus.throughput 94839875 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 178718 # Transaction distribution
system.membus.trans_dist::ReadResp 178718 # Transaction distribution
system.membus.trans_dist::Writeback 293541 # Transaction distribution
system.membus.trans_dist::UpgradeReq 130355 # Transaction distribution
system.membus.trans_dist::UpgradeResp 130355 # Transaction distribution
system.membus.trans_dist::ReadExReq 206847 # Transaction distribution
system.membus.trans_dist::ReadExResp 206847 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1325381 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1325381 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1325381 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43462784 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43462784 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 43462784 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 43462784 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.membus.reqLayer0.occupancy 3388183000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.membus.respLayer1.occupancy 3900602651 # Layer occupancy (ticks)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.branchPred.lookups 205585963 # Number of BP lookups
system.cpu.branchPred.condPredicted 205585963 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 9896898 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 117084329 # Number of BTB lookups
system.cpu.branchPred.BTBHits 114697569 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.branchPred.BTBHitPct 97.961503 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 25058112 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1791626 # Number of incorrect RAS predictions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 551 # Number of system calls
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.numCycles 916710548 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.fetch.icacheStallCycles 167348410 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1131642862 # Number of instructions fetch has processed
system.cpu.fetch.Branches 205585963 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 139755681 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 352231951 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 71067415 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 303674725 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 47310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 248698 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 162008096 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2545258 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 884470252 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.380434 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.325121 # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.fetch.rateDist::0 536305374 60.64% 60.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 23381398 2.64% 63.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 25249677 2.85% 66.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 27894624 3.15% 69.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 17755657 2.01% 71.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 22913193 2.59% 73.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 29422157 3.33% 77.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 26648623 3.01% 80.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 174899549 19.77% 100.00% # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.fetch.rateDist::total 884470252 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.224265 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.234460 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 222591066 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 258702766 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 295279341 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 46977961 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 60919118 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2071200226 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 60919118 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 256021570 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 114401726 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 17692 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 306707585 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 146402561 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2035040457 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 18320 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 24691093 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 106444419 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 265 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2137898681 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5150156292 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5150048563 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 107729 # Number of floating rename lookups
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.rename.UndoneMaps 523857827 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1226 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1159 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 345797829 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 495831912 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 194432339 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 195703509 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 55003285 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1975319588 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 13057 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1772061886 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 486216 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 441442603 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 734769754 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12505 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 884470252 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.003529 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.883234 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iq.issued_per_cycle::0 268041211 30.31% 30.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 151493171 17.13% 47.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 137403926 15.54% 62.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 131820403 14.90% 77.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 91692561 10.37% 88.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 55993839 6.33% 94.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 34399481 3.89% 98.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 11841951 1.34% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1783709 0.20% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iq.issued_per_cycle::total 884470252 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iq.fu_full::IntAlu 4921151 32.49% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7620621 50.31% 82.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2606942 17.21% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iq.FU_type_0::No_OpClass 2621205 0.15% 0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1165737036 65.78% 65.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 353398 0.02% 65.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 3880807 0.22% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iq.FU_type_0::MemRead 429244538 24.22% 90.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170224897 9.61% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iq.FU_type_0::total 1772061886 # Type of FU issued
system.cpu.iq.rate 1.933066 # Inst issue rate
system.cpu.iq.fu_busy_cnt 15148714 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008549 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4444213917 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2416999842 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1744830269 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15037 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 32010 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 3518 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1784582309 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7086 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 172513794 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 111729755 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 382662 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 328443 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 45273076 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 15362 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 587 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iew.iewSquashCycles 60919118 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 66781934 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 7163097 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1975332645 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 792462 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 495831912 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 194433262 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3156 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 4458880 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 83353 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 328443 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 5899350 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4421061 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 10320411 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1752917873 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 424115674 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 19144013 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iew.exec_refs 590898440 # number of memory reference insts executed
system.cpu.iew.exec_branches 167466606 # Number of branches executed
system.cpu.iew.exec_stores 166782766 # Number of stores executed
system.cpu.iew.exec_rate 1.912183 # Inst execution rate
system.cpu.iew.wb_sent 1749674904 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1744833787 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1325104556 # num instructions producing a value
system.cpu.iew.wb_consumers 1945968985 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.iew.wb_rate 1.903364 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.680948 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.commit.commitSquashedInsts 446372129 # The number of squashed insts skipped by commit
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.commit.branchMispredicts 9924639 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 823551134 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.856580 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.437034 # Number of insts commited each cycle
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.commit.committed_per_cycle::0 331597809 40.26% 40.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 193248476 23.47% 63.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 63098135 7.66% 71.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 92588887 11.24% 82.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 24967401 3.03% 85.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27517381 3.34% 89.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 9278594 1.13% 90.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 11386387 1.38% 91.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 69868064 8.48% 100.00% # Number of insts commited each cycle
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.commit.committed_per_cycle::total 823551134 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 533262343 # Number of memory references committed
system.cpu.commit.loads 384102157 # Number of loads committed
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 149758583 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions.
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.commit.bw_lim_events 69868064 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.rob.rob_reads 2729043900 # The number of ROB reads
system.cpu.rob.rob_writes 4011801822 # The number of ROB writes
system.cpu.timesIdled 3353209 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 32240296 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.cpi 1.108642 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.108642 # CPI: Total CPI of All Threads
system.cpu.ipc 0.902005 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.902005 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3313398089 # number of integer regfile reads
system.cpu.int_regfile_writes 1825851160 # number of integer regfile writes
system.cpu.fp_regfile_reads 3505 # number of floating regfile reads
system.cpu.fp_regfile_writes 24 # number of floating regfile writes
system.cpu.misc_regfile_reads 964629229 # number of misc regfile reads
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.toL2Bus.throughput 698744583 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1900899 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1900898 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2330727 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 131758 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 131758 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 771773 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 771773 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 145540 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7662191 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7807731 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437888 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311340864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 311778752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 311778752 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 8438720 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4901666269 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 208719992 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 3959172045 # Layer occupancy (ticks)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.icache.tags.replacements 5320 # number of replacements
system.cpu.icache.tags.tagsinuse 1038.062732 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 161865564 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6903 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 23448.582355 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1038.062732 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.506867 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.506867 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 161867461 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 161867461 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 161867461 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 161867461 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 161867461 # number of overall hits
system.cpu.icache.overall_hits::total 161867461 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 140635 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 140635 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 140635 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 140635 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 140635 # number of overall misses
system.cpu.icache.overall_misses::total 140635 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 923937485 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 923937485 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 923937485 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 923937485 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 923937485 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 923937485 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 162008096 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 162008096 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 162008096 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 162008096 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 162008096 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 162008096 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000868 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000868 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000868 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000868 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000868 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000868 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6569.754933 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 6569.754933 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6569.754933 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 6569.754933 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6569.754933 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 6569.754933 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 708 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
x86, regressions: updates stats This is due to op class, function call, walker patches.
2013-05-21 18:41:27 +02:00
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 118 # average number of cycles each access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1937 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1937 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1937 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1937 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1937 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1937 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 138698 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 138698 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 138698 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 138698 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 138698 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 138698 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 556491008 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 556491008 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 556491008 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 556491008 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 556491008 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 556491008 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000856 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000856 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000856 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000856 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000856 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000856 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4012.249694 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4012.249694 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4012.249694 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 4012.249694 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4012.249694 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 4012.249694 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.tags.replacements 352883 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29672.816995 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3696782 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 385243 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 9.595974 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 199077347000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21120.561633 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 222.415022 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8329.840341 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.644548 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006788 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.254207 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.905543 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3674 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1586650 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1590324 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2330727 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2330727 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1427 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1427 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 564902 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 564902 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3674 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2151552 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2155226 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3674 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2151552 # number of overall hits
system.cpu.l2cache.overall_hits::total 2155226 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3169 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 175551 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 178720 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 130331 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 130331 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 206871 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206871 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3169 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 382422 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 385591 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3169 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 382422 # number of overall misses
system.cpu.l2cache.overall_misses::total 385591 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245985250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13221288951 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 13467274201 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6607716 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 6607716 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14252900476 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 14252900476 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 245985250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 27474189427 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 27720174677 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 245985250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 27474189427 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 27720174677 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6843 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1762201 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1769044 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2330727 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2330727 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 131758 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 131758 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 771773 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 771773 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 6843 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2533974 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2540817 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6843 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2533974 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2540817 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463101 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099620 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.101026 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989170 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989170 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268046 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.268046 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463101 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150918 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.151759 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463101 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150918 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151759 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77622.357210 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75313.093921 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75354.040964 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 50.699496 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 50.699496 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68897.527812 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68897.527812 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77622.357210 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71842.596469 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71890.097738 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77622.357210 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71842.596469 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71890.097738 # average overall miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.writebacks::writebacks 293541 # number of writebacks
system.cpu.l2cache.writebacks::total 293541 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3169 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175550 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 178719 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 130331 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 130331 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206871 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206871 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 382421 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 385590 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 382421 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 385590 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205942250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10968319701 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11174261951 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1306769847 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1306769847 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11624255024 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11624255024 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205942250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22592574725 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 22798516975 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205942250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22592574725 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 22798516975 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099620 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101026 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989170 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989170 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268046 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268046 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150917 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151758 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150917 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151758 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64986.509940 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.747656 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62524.196929 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.546616 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.546616 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56190.838851 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56190.838851 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64986.509940 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59077.756517 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59126.318045 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64986.509940 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59077.756517 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59126.318045 # average overall mshr miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.tags.replacements 2529878 # number of replacements
system.cpu.dcache.tags.tagsinuse 4088.353781 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 396093197 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2533974 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 156.313047 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit.
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353781 # Average occupied blocks per requestor
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.ReadReq_hits::cpu.data 247361230 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 247361230 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148239956 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148239956 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 395601186 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 395601186 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 395601186 # number of overall hits
system.cpu.dcache.overall_hits::total 395601186 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2863617 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2863617 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 920246 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 920246 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3783863 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3783863 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3783863 # number of overall misses
system.cpu.dcache.overall_misses::total 3783863 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57446251269 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 57446251269 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25840120296 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 25840120296 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 83286371565 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 83286371565 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 83286371565 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 83286371565 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250224847 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250224847 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.demand_accesses::cpu.data 399385049 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 399385049 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 399385049 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 399385049 # number of overall (read+write) accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011444 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.011444 # miss rate for ReadReq accesses
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006170 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006170 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009474 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009474 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009474 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009474 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20060.731330 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20060.731330 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28079.579043 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28079.579043 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22010.937385 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22010.937385 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22010.937385 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22010.937385 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 7195 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.blocked::no_mshrs 685 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.503650 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.writebacks::writebacks 2330727 # number of writebacks
system.cpu.dcache.writebacks::total 2330727 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1101143 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1101143 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16988 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 16988 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1118131 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1118131 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1118131 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1118131 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762474 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1762474 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 903258 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 903258 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2665732 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2665732 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2665732 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2665732 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30885946501 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30885946501 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23721964454 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 23721964454 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54607910955 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 54607910955 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54607910955 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 54607910955 # number of overall MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006056 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006056 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006675 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006675 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006675 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006675 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17524.199790 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17524.199790 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26262.667426 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26262.667426 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20485.146652 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20485.146652 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20485.146652 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20485.146652 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink