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gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

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stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
---------- Begin Simulation Statistics ----------
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
sim_seconds 0.434779 # Number of seconds simulated
sim_ticks 434778577000 # Number of ticks simulated
final_tick 434778577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
host_inst_rate 92341 # Simulator instruction rate (inst/s)
host_op_rate 170748 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 48553388 # Simulator tick rate (ticks/s)
host_mem_usage 422424 # Number of bytes of host memory used
host_seconds 8954.65 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 826877109 # Number of instructions simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 207616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24480192 # Number of bytes read from this memory
system.physmem.bytes_read::total 24687808 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 207616 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 207616 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18793792 # Number of bytes written to this memory
system.physmem.bytes_written::total 18793792 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3244 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 382503 # Number of read requests responded to by this memory
system.physmem.num_reads::total 385747 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293653 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293653 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 477521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 56304964 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 56782485 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 477521 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 477521 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 43226122 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 43226122 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 43226122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 477521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 56304964 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 100008607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 385749 # Total number of read requests seen
system.physmem.writeReqs 293653 # Total number of write requests seen
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.cpureqs 895346 # Reqs generatd by CPU via cache - shady
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.bytesRead 24687808 # Total number of bytes read from memory
system.physmem.bytesWritten 18793792 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 24687808 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 18793792 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 215914 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 23310 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 24517 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 23767 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 22579 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 23602 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 24804 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 24363 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 24233 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 24554 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 24709 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 24156 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 24303 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 24582 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 23494 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 24683 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 23927 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 17803 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 18810 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 18279 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 17552 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 18029 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 18664 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 18338 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 18780 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 18770 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 18402 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 18539 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 18562 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 17888 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 18802 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 18117 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.totGap 434778560000 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.readPktSize::6 385749 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.writePktSize::6 293653 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 380888 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4255 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 362 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 63 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.wrQLenPdf::0 12710 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 12723 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 12724 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 12726 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 12730 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 12731 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 12734 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 12734 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 12736 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 37 # What write queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.totQLat 3433770500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 12026723000 # Sum of mem lat for all requests
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.totBusLat 1927915000 # Total cycles spent in databus access
system.physmem.totBankLat 6665037500 # Total cycles spent in bank access
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.avgQLat 8905.40 # Average queueing delay per request
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.avgBankLat 17285.61 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.physmem.avgMemAccLat 31191.01 # Average memory access latency
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.avgRdBW 56.78 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 43.23 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 56.78 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 43.23 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.78 # Data bus utilization in percentage
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgRdQLen 0.03 # Average read queue length over time
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.physmem.avgWrQLen 9.96 # Average write queue length over time
system.physmem.readRowHits 331863 # Number of row buffer hits during reads
system.physmem.writeRowHits 191855 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 65.33 # Row buffer hit rate for writes
system.physmem.avgGap 639943.01 # Average gap between requests
system.cpu.branchPred.lookups 214994146 # Number of BP lookups
system.cpu.branchPred.condPredicted 214994146 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 13135298 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 150584792 # Number of BTB lookups
system.cpu.branchPred.BTBHits 147887338 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.branchPred.BTBHitPct 98.208681 # BTB Hit Percentage
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.workload.num_syscalls 551 # Number of system calls
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.numCycles 869557155 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.fetch.icacheStallCycles 180620519 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1193264599 # Number of instructions fetch has processed
system.cpu.fetch.Branches 214994146 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 147887338 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 371275147 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 83409102 # Number of cycles fetch has spent squashing
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.fetch.BlockedCycles 231974121 # Number of cycles fetch has spent blocked
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.fetch.MiscStallCycles 33791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 326928 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 173497134 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 3845609 # Number of outstanding Icache misses that were squashed
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.fetch.rateDist::samples 854248202 # Number of instructions fetched each cycle (Total)
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.fetch.rateDist::mean 2.593680 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.388732 # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.fetch.rateDist::0 487377951 57.05% 57.05% # Number of instructions fetched each cycle (Total)
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.fetch.rateDist::1 24712671 2.89% 59.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 27340185 3.20% 63.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 28885218 3.38% 66.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 18461820 2.16% 68.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 24636038 2.88% 71.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 30640475 3.59% 75.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 28823425 3.37% 78.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 183370419 21.47% 100.00% # Number of instructions fetched each cycle (Total)
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.fetch.rateDist::total 854248202 # Number of instructions fetched each cycle (Total)
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.fetch.branchRate 0.247246 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.372267 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 237078092 # Number of cycles decode is idle
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.decode.BlockedCycles 188537107 # Number of cycles decode is blocked
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.decode.RunCycles 313423018 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 45192344 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 70017641 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2166915251 # Number of instructions handled by decode
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.rename.SquashCycles 70017641 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 270505809 # Number of cycles rename is idle
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.rename.BlockCycles 54166580 # Number of cycles rename is blocking
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.rename.serializeStallCycles 16246 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 322705449 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 136836477 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2120054204 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 31988 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 21457173 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 101130762 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 79 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2216502453 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5356043513 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5355912931 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 130582 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 602461599 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1415 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1390 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 330161364 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 512694390 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 204951429 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 196255090 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 55443674 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2034023079 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 23697 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1808317213 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 841556 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 499552115 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 818199817 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 23145 # Number of squashed non-spec instructions that were removed
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.iq.issued_per_cycle::samples 854248202 # Number of insts issued each cycle
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iq.issued_per_cycle::mean 2.116852 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.887224 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.iq.issued_per_cycle::0 233580309 27.34% 27.34% # Number of insts issued each cycle
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iq.issued_per_cycle::1 145624549 17.05% 44.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 138385021 16.20% 60.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 133093921 15.58% 76.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 95894144 11.23% 87.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 58820201 6.89% 94.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 34887177 4.08% 98.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 12062824 1.41% 99.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1900056 0.22% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.iq.issued_per_cycle::total 854248202 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iq.fu_full::IntAlu 4959094 32.46% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7752013 50.74% 83.20% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2567167 16.80% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2720919 0.15% 0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1190891827 65.86% 66.01% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 66.01% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iq.FU_type_0::MemRead 438957859 24.27% 90.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 175746607 9.72% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iq.FU_type_0::total 1808317213 # Type of FU issued
system.cpu.iq.rate 2.079584 # Inst issue rate
system.cpu.iq.fu_busy_cnt 15278274 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst)
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.iq.int_inst_queue_reads 4486980235 # Number of integer instruction queue reads
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iq.int_inst_queue_writes 2533813283 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1768843031 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 42394 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 5084 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1820864137 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 10431 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 170575963 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 128592233 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 466094 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 268512 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 55791476 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 12353 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 585 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iew.iewSquashCycles 70017641 # Number of cycles IEW is squashing
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.iew.iewBlockCycles 16317046 # Number of cycles IEW is blocking
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iew.iewUnblockCycles 2892217 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2034046776 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2393263 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 512694390 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 204951662 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6140 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1820618 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 76746 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 268512 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 9116558 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4489858 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 13606416 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1780627625 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 431426006 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 27689588 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iew.exec_refs 602161774 # number of memory reference insts executed
system.cpu.iew.exec_branches 169273752 # Number of branches executed
system.cpu.iew.exec_stores 170735768 # Number of stores executed
system.cpu.iew.exec_rate 2.047741 # Inst execution rate
system.cpu.iew.wb_sent 1775545178 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1768848115 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1341672434 # num instructions producing a value
system.cpu.iew.wb_consumers 1964743040 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.iew.wb_rate 2.034194 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.682874 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.commitSquashedInsts 505092905 # The number of squashed insts skipped by commit
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.branchMispredicts 13168881 # The number of times a branch was mispredicted
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.commit.committed_per_cycle::samples 784230561 # Number of insts commited each cycle
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.committed_per_cycle::mean 1.949667 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.458347 # Number of insts commited each cycle
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.commit.committed_per_cycle::0 290802584 37.08% 37.08% # Number of insts commited each cycle
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.committed_per_cycle::1 195769482 24.96% 62.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 62065599 7.91% 69.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 92211558 11.76% 81.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 25071827 3.20% 84.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 28246222 3.60% 88.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 9385684 1.20% 89.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10800015 1.38% 91.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 69877590 8.91% 100.00% # Number of insts commited each cycle
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.commit.committed_per_cycle::total 784230561 # Number of insts commited each cycle
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.refs 533262343 # Number of memory references committed
system.cpu.commit.loads 384102157 # Number of loads committed
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
system.cpu.commit.membars 0 # Number of memory barriers committed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.commit.branches 149758583 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 0 # Number of function calls committed.
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.commit.bw_lim_events 69877590 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.rob.rob_reads 2748434577 # The number of ROB reads
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.rob.rob_writes 4138359582 # The number of ROB writes
system.cpu.timesIdled 322597 # Number of times that the entire CPU went into an idle state and unscheduled itself
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.idleCycles 15308953 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.cpi 1.051616 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.051616 # CPI: Total CPI of All Threads
system.cpu.ipc 0.950917 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.950917 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3357648579 # number of integer regfile reads
system.cpu.int_regfile_writes 1848573449 # number of integer regfile writes
system.cpu.fp_regfile_reads 5079 # number of floating regfile reads
system.cpu.fp_regfile_writes 8 # number of floating regfile writes
system.cpu.misc_regfile_reads 980313786 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 5514 # number of replacements
system.cpu.icache.tagsinuse 1036.209327 # Cycle average of tags in use
system.cpu.icache.total_refs 173254328 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 7112 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 24360.844769 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.icache.occ_blocks::cpu.inst 1036.209327 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.505962 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.505962 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 173270216 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 173270216 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 173270216 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 173270216 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 173270216 # number of overall hits
system.cpu.icache.overall_hits::total 173270216 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 226918 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 226918 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 226918 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 226918 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 226918 # number of overall misses
system.cpu.icache.overall_misses::total 226918 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1447936998 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1447936998 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1447936998 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1447936998 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1447936998 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1447936998 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 173497134 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 173497134 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 173497134 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 173497134 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 173497134 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 173497134 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001308 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001308 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001308 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001308 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001308 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001308 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.882072 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 6380.882072 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6380.882072 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 6380.882072 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.882072 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 6380.882072 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1948 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 121.750000 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2338 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2338 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2338 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2338 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2338 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2338 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 224580 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 224580 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 224580 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 224580 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 224580 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 224580 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 927401499 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 927401499 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 927401499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 927401499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 927401499 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 927401499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001294 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001294 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001294 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001294 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001294 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001294 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4129.492827 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4129.492827 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4129.492827 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 4129.492827 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4129.492827 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 4129.492827 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.replacements 353068 # number of replacements
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.tagsinuse 29624.531166 # Cycle average of tags in use
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.total_refs 3697718 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 385429 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 9.593772 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 201975419000 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.occ_blocks::writebacks 21048.484720 # Average occupied blocks per requestor
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.occ_blocks::cpu.inst 232.592119 # Average occupied blocks per requestor
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.occ_blocks::cpu.data 8343.454326 # Average occupied blocks per requestor
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.occ_percent::writebacks 0.642349 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.007098 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.254622 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.904069 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3816 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1586658 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1590474 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2331136 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2331136 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1531 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1531 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 564560 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 564560 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3816 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2151218 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2155034 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3816 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2151218 # number of overall hits
system.cpu.l2cache.overall_hits::total 2155034 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3245 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 175772 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 179017 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 215883 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 215883 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 206764 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206764 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3245 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 382536 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 385781 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3245 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 382536 # number of overall misses
system.cpu.l2cache.overall_misses::total 385781 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201201000 # number of ReadReq miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10144983954 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 10346184954 # number of ReadReq miss cycles
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7392500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 7392500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10367117000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 10367117000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 201201000 # number of demand (read+write) miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.data 20512100954 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20713301954 # number of demand (read+write) miss cycles
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 201201000 # number of overall miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.data 20512100954 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20713301954 # number of overall miss cycles
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 7061 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1762430 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1769491 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2331136 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2331136 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 217414 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 217414 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 771324 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 771324 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 7061 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2533754 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2540815 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 7061 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2533754 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2540815 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459567 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099733 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.101169 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992958 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992958 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268064 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.268064 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459567 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150976 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.151834 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459567 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150976 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151834 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62003.389831 # average ReadReq miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.723676 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.427088 # average ReadReq miss latency
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.243085 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.243085 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50139.855101 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50139.855101 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 53691.866510 # average overall miss latency
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 53691.866510 # average overall miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.writebacks::writebacks 293653 # number of writebacks
system.cpu.l2cache.writebacks::total 293653 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3245 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175772 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 179017 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 215883 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 215883 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206764 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206764 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3245 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 382536 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 385781 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3245 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 382536 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160858519 # number of ReadReq MSHR miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7969654402 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8130512921 # number of ReadReq MSHR miss cycles
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2164647428 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2164647428 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7779866278 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7779866278 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160858519 # number of demand (read+write) MSHR miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15749520680 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15910379199 # number of demand (read+write) MSHR miss cycles
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160858519 # number of overall MSHR miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15749520680 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15910379199 # number of overall MSHR miss cycles
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099733 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101169 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992958 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992958 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268064 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268064 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150976 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151834 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150976 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151834 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49571.192296 # average ReadReq mshr miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45340.864313 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45417.546496 # average ReadReq mshr miss latency
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.947133 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.947133 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37626.793243 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37626.793243 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency
x86 regressions: stats update due to new x87 instructions
2012-12-30 19:45:52 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.dcache.replacements 2529656 # number of replacements
system.cpu.dcache.tagsinuse 4087.796251 # Cycle average of tags in use
system.cpu.dcache.total_refs 405349896 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2533752 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 159.980099 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1794571000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.796251 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997997 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997997 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 256610011 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 256610011 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148154878 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148154878 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 404764889 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 404764889 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 404764889 # number of overall hits
system.cpu.dcache.overall_hits::total 404764889 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2895327 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2895327 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1005324 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1005324 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3900651 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3900651 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3900651 # number of overall misses
system.cpu.dcache.overall_misses::total 3900651 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 51401791500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 51401791500 # number of ReadReq miss cycles
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898481499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 23898481499 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 75300272999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 75300272999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 75300272999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 75300272999 # number of overall miss cycles
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 259505338 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 259505338 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.dcache.demand_accesses::cpu.data 408665540 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 408665540 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 408665540 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 408665540 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011157 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.011157 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006740 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006740 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17753.363092 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17753.363092 # average ReadReq miss latency
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.919798 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.919798 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19304.539934 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19304.539934 # average overall miss latency
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 6530 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.dcache.blocked::no_mshrs 642 # number of cycles access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.171340 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.dcache.writebacks::writebacks 2331136 # number of writebacks
system.cpu.dcache.writebacks::total 2331136 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1132617 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1132617 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16869 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 16869 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1149486 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1149486 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1149486 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1149486 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762710 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1762710 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 988455 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 988455 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2751165 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2751165 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2751165 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2751165 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27811279500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27811279500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21719252000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 21719252000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49530531500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 49530531500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49530531500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 49530531500 # number of overall MSHR miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006627 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006627 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006732 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006732 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006732 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006732 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15777.569481 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15777.569481 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21972.929471 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21972.929471 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18003.475437 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18003.475437 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18003.475437 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18003.475437 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update 20.parser o3 now that it works. realview-o3 works too.
2011-04-25 23:18:08 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink