2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
2016-10-14 00:21:40 +02:00
sim_seconds 2.826595 # Number of seconds simulated
sim_ticks 2826594924500 # Number of ticks simulated
final_tick 2826594924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-10-14 00:21:40 +02:00
host_inst_rate 79087 # Simulator instruction rate (inst/s)
host_op_rate 95944 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1861516367 # Simulator tick rate (ticks/s)
host_mem_usage 623016 # Number of bytes of host memory used
host_seconds 1518.44 # Real time elapsed on the host
sim_insts 120088860 # Number of instructions simulated
sim_ops 145685275 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory
2016-05-31 12:07:18 +02:00
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_read::cpu0.inst 1324752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1304168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8428096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_read::cpu1.inst 175008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 586900 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 427200 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_read::total 12249452 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1324752 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 175008 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1499760 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8803008 # Number of bytes written to this memory
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_written::total 8820572 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_reads::cpu0.inst 22950 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 20898 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 131689 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_reads::cpu1.inst 2802 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9191 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 6675 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_reads::total 194257 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 137547 # Number of write requests responded to by this memory
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_writes::total 141938 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 657 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_read::cpu0.inst 468674 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 461392 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2981713 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_read::cpu1.inst 61915 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 207635 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 151136 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_read::total 4333643 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 468674 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 61915 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 530589 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3114351 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_write::total 3120565 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3114351 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_total::cpu0.inst 468674 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 467592 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2981713 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_total::cpu1.inst 61915 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 207649 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 151136 # Total bandwidth to/from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_total::total 7454207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 194258 # Number of read requests accepted
system.physmem.writeReqs 141938 # Number of write requests accepted
system.physmem.readBursts 194258 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 141938 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12422976 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue
system.physmem.bytesWritten 8833536 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12249516 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8820572 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::0 12130 # Per bank write bursts
system.physmem.perBankRdBursts::1 12140 # Per bank write bursts
system.physmem.perBankRdBursts::2 12480 # Per bank write bursts
system.physmem.perBankRdBursts::3 12151 # Per bank write bursts
system.physmem.perBankRdBursts::4 14882 # Per bank write bursts
system.physmem.perBankRdBursts::5 12677 # Per bank write bursts
system.physmem.perBankRdBursts::6 12709 # Per bank write bursts
system.physmem.perBankRdBursts::7 12606 # Per bank write bursts
system.physmem.perBankRdBursts::8 11844 # Per bank write bursts
system.physmem.perBankRdBursts::9 11522 # Per bank write bursts
system.physmem.perBankRdBursts::10 11334 # Per bank write bursts
system.physmem.perBankRdBursts::11 10175 # Per bank write bursts
system.physmem.perBankRdBursts::12 11497 # Per bank write bursts
system.physmem.perBankRdBursts::13 12486 # Per bank write bursts
system.physmem.perBankRdBursts::14 11961 # Per bank write bursts
system.physmem.perBankRdBursts::15 11515 # Per bank write bursts
system.physmem.perBankWrBursts::0 8842 # Per bank write bursts
system.physmem.perBankWrBursts::1 8923 # Per bank write bursts
system.physmem.perBankWrBursts::2 9151 # Per bank write bursts
system.physmem.perBankWrBursts::3 8834 # Per bank write bursts
system.physmem.perBankWrBursts::4 8743 # Per bank write bursts
system.physmem.perBankWrBursts::5 9257 # Per bank write bursts
system.physmem.perBankWrBursts::6 9174 # Per bank write bursts
system.physmem.perBankWrBursts::7 9022 # Per bank write bursts
system.physmem.perBankWrBursts::8 8380 # Per bank write bursts
system.physmem.perBankWrBursts::9 8199 # Per bank write bursts
system.physmem.perBankWrBursts::10 8228 # Per bank write bursts
system.physmem.perBankWrBursts::11 7543 # Per bank write bursts
system.physmem.perBankWrBursts::12 8493 # Per bank write bursts
system.physmem.perBankWrBursts::13 8795 # Per bank write bursts
system.physmem.perBankWrBursts::14 8486 # Per bank write bursts
system.physmem.perBankWrBursts::15 7954 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-10-14 00:21:40 +02:00
system.physmem.numWrRetry 65 # Number of times write queue was full causing retry
system.physmem.totGap 2826594637500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::2 551 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 28 # Read request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.readPktSize::4 3091 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.readPktSize::6 190588 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.writePktSize::6 137547 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 58416 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 70500 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 15616 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12705 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8571 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7500 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 6655 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5421 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4753 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1522 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1119 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 747 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 307 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 270 # What read queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::15 2470 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3918 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5685 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7253 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9581 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10090 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8838 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 10600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8664 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1058 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 743 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 239 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 169 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 210 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 84597 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 251.267917 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 142.709069 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 307.432600 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 42654 50.42% 50.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17739 20.97% 71.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6092 7.20% 78.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3470 4.10% 82.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2903 3.43% 86.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1534 1.81% 87.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 962 1.14% 89.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 998 1.18% 90.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8245 9.75% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 84597 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6823 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.448923 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 563.375084 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6821 99.97% 99.97% # Reads before turning the bus around for writes
2016-05-31 12:07:18 +02:00
system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
2016-05-31 17:55:47 +02:00
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
2016-10-14 00:21:40 +02:00
system.physmem.rdPerTurnAround::total 6823 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6823 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.229225 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.516304 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 14.191757 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5762 84.45% 84.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 386 5.66% 90.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 77 1.13% 91.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 44 0.64% 91.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 244 3.58% 95.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 18 0.26% 95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 14 0.21% 95.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 12 0.18% 96.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 17 0.25% 96.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 2 0.03% 96.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 5 0.07% 96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 8 0.12% 96.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 140 2.05% 98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 6 0.09% 98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 5 0.07% 98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 10 0.15% 98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 12 0.18% 99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.01% 99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 3 0.04% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.03% 99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 4 0.06% 99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 3 0.04% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.01% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 8 0.12% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 2 0.03% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 2 0.03% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 13 0.19% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.01% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.01% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 2 0.03% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 4 0.06% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 4 0.06% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6823 # Writes before turning the bus around for reads
system.physmem.totQLat 10063104165 # Total ticks spent queuing
system.physmem.totMemAccLat 13702647915 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 970545000 # Total ticks spent in databus transfers
system.physmem.avgQLat 51842.28 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 70592.18 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.40 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s
2016-08-12 15:12:59 +02:00
system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.06 # Data bus utilization in percentage
2016-08-12 15:12:59 +02:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-11-06 09:26:50 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2016-10-14 00:21:40 +02:00
system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.32 # Average write queue length when enqueuing
system.physmem.readRowHits 161915 # Number of row buffer hits during reads
system.physmem.writeRowHits 85621 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.41 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 62.03 # Row buffer hit rate for writes
system.physmem.avgGap 8407579.62 # Average gap between requests
system.physmem.pageHitRate 74.52 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 318172680 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 169112790 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 726673500 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 375558120 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 4535428560.000001 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 4774700760 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 244257600 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 9148762200 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 6477825120 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 667571113185 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 694343780025 # Total energy per rank (pJ)
system.physmem_0.averagePower 245.646723 # Core power per rank (mW)
system.physmem_0.totalIdleTime 2815396783365 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 428149701 # Time in different power states
system.physmem_0.memoryStateTime::REF 1926538000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 2778550744250 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 16869300047 # Time in different power states
system.physmem_0.memoryStateTime::ACT 8757031934 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 20063160568 # Time in different power states
system.physmem_1.actEnergy 285849900 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 151932825 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 659264760 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 344927160 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4569848400.000001 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 4671042840 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 250741920 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 8727797820 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 6816319680 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 667684488600 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 694164121065 # Total energy per rank (pJ)
system.physmem_1.averagePower 245.583162 # Core power per rank (mW)
system.physmem_1.totalIdleTime 2815694283339 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 440101951 # Time in different power states
system.physmem_1.memoryStateTime::REF 1941710000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 2778803468000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 17750764755 # Time in different power states
system.physmem_1.memoryStateTime::ACT 8518829210 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 19140050584 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2016-10-14 00:21:40 +02:00
system.cpu0.branchPred.lookups 53161527 # Number of BP lookups
system.cpu0.branchPred.condPredicted 24432585 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 935077 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 32150468 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 13984916 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-10-14 00:21:40 +02:00
system.cpu0.branchPred.BTBHitPct 43.498328 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 15489494 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 33173 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 10133739 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 9977658 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 156081 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 49006 # Number of mispredicted indirect branches.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 66483 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 66483 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25519 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19054 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 21910 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 44573 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 499.046508 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 3114.296115 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191 43354 97.27% 97.27% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383 917 2.06% 99.32% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.60% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767 116 0.26% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959 24 0.05% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency
2016-04-21 10:48:24 +02:00
system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-10-14 00:21:40 +02:00
system.cpu0.dtb.walker.walkWaitTime::total 44573 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 16394 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 11498.017567 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 9809.718618 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 10152.442305 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 14883 90.78% 90.78% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1339 8.17% 98.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 129 0.79% 99.74% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535 18 0.11% 99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.01% 99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::114688-131071 6 0.04% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::245760-262143 16 0.10% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 16394 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 86404933652 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.566419 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.506005 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 86345641152 99.93% 99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 41095500 0.05% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 8202000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 4970000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 2695000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 946000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 940000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 429500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 86404933652 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5203 78.33% 78.33% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1439 21.67% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6642 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66483 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66483 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6642 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6642 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 73125 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-10-14 00:21:40 +02:00
system.cpu0.dtb.read_hits 23680324 # DTB read hits
system.cpu0.dtb.read_misses 56461 # DTB read misses
system.cpu0.dtb.write_hits 17598903 # DTB write hits
system.cpu0.dtb.write_misses 10022 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-10-14 00:21:40 +02:00
system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2246 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-10-14 00:21:40 +02:00
system.cpu0.dtb.perms_faults 902 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 23736785 # DTB read accesses
system.cpu0.dtb.write_accesses 17608925 # DTB write accesses
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-10-14 00:21:40 +02:00
system.cpu0.dtb.hits 41279227 # DTB hits
system.cpu0.dtb.misses 66483 # DTB misses
system.cpu0.dtb.accesses 41345710 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 11041 # Table walker walks requested
system.cpu0.itb.walker.walksShort 11041 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4028 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5930 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 1083 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 9958 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 410.574413 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 2129.037976 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095 9588 96.28% 96.28% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191 186 1.87% 98.15% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287 118 1.18% 99.34% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.38% 99.72% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479 5 0.05% 99.77% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 9958 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 3663 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12262.353262 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11250.035596 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 5522.553888 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 663 18.10% 18.10% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 2695 73.57% 91.67% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 173 4.72% 96.40% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 79 2.16% 98.55% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.08% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 3663 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 21980185712 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.834654 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.371618 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 3635314000 16.54% 16.54% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 18343952712 83.46% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 868500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 50500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 21980185712 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2243 86.94% 86.94% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 337 13.06% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2580 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11041 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11041 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2580 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2580 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 13621 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 72829698 # ITB inst hits
system.cpu0.itb.inst_misses 11041 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-10-14 00:21:40 +02:00
system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-10-14 00:21:40 +02:00
system.cpu0.itb.perms_faults 1929 # Number of TLB faults due to permissions restrictions
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-10-14 00:21:40 +02:00
system.cpu0.itb.inst_accesses 72840739 # ITB inst accesses
system.cpu0.itb.hits 72829698 # DTB hits
system.cpu0.itb.misses 11041 # DTB misses
system.cpu0.itb.accesses 72840739 # DTB accesses
system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 1456796210.372727 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 23672658216.113400 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 1093 58.45% 58.45% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.28% 99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-10-14 00:21:40 +02:00
system.cpu0.pwrStateClkGateDist::max_value 499970757520 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 102386011103 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724208913397 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 204773026 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-10-14 00:21:40 +02:00
system.cpu0.fetch.icacheStallCycles 20714269 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 196101622 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 53161527 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 39452068 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 175603283 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 5698298 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 148281 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 57647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 420719 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 418648 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 100050 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 72829386 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 258768 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 5384 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 200312046 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.196487 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.307164 # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu0.fetch.rateDist::0 95293979 47.57% 47.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 30393228 15.17% 62.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 14596992 7.29% 70.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 60027847 29.97% 100.00% # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu0.fetch.rateDist::total 200312046 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.259612 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.957654 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 25714917 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 108196913 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 58914772 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 4966892 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2518552 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 3065050 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 334861 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 154468947 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 3822056 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 2518552 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 34338225 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 12857218 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 83619486 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 55122113 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 11856452 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 137773765 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 1037168 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1494015 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 163408 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 59807 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 7647937 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 141868428 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 635547314 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 152852010 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 9442 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 130675877 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 11192540 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 2699923 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 2556575 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 22590232 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 24607184 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 19088589 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1696558 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2229617 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 134839557 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1714900 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 132985122 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 452743 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10598058 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 21682682 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 119247 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 200312046 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.663890 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 0.961819 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-10-14 00:21:40 +02:00
system.cpu0.iq.issued_per_cycle::0 123495652 61.65% 61.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 33655276 16.80% 78.45% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 31282184 15.62% 94.07% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 10750314 5.37% 99.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1128564 0.56% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 56 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-10-14 00:21:40 +02:00
system.cpu0.iq.issued_per_cycle::total 200312046 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-10-14 00:21:40 +02:00
system.cpu0.iq.fu_full::IntAlu 10816144 43.95% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 73 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5628152 22.87% 66.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 8167261 33.18% 100.00% # attempts to use FU when none available
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu0.iq.FU_type_0::IntAlu 89847428 67.56% 67.56% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 110447 0.08% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 7864 0.01% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 24369410 18.32% 85.98% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 18647698 14.02% 100.00% # Type of FU issued
2011-08-19 22:08:09 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu0.iq.FU_type_0::total 132985122 # Type of FU issued
system.cpu0.iq.rate 0.649427 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 24611630 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.185071 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 491314323 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 147160457 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 129454820 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 32339 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11262 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 157573424 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 21055 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 367821 # Number of loads that had data forwarded from stores
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-10-14 00:21:40 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 1916447 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2461 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 19267 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 901714 # Number of stores squashed
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-10-14 00:21:40 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 120909 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 362204 # Number of times an access to memory failed due to the cache being blocked
2011-08-19 22:08:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-10-14 00:21:40 +02:00
system.cpu0.iew.iewSquashCycles 2518552 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1651189 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 246744 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 136707359 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-10-14 00:21:40 +02:00
system.cpu0.iew.iewDispLoadInsts 24607184 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 19088589 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 876464 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 27795 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 194810 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 19267 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 261439 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 400306 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 661745 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 131953488 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 23926851 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 965273 # Number of squashed instructions skipped in execute
2011-08-19 22:08:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
2016-10-14 00:21:40 +02:00
system.cpu0.iew.exec_nop 152902 # number of nop insts executed
system.cpu0.iew.exec_refs 42414312 # number of memory reference insts executed
system.cpu0.iew.exec_branches 25613561 # Number of branches executed
system.cpu0.iew.exec_stores 18487461 # Number of stores executed
system.cpu0.iew.exec_rate 0.644389 # Inst execution rate
system.cpu0.iew.wb_sent 131398393 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 129464537 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 66052971 # num instructions producing a value
system.cpu0.iew.wb_consumers 106772912 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.632234 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.618630 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 9569777 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1595653 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 604480 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 197147849 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.639512 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.336739 # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu0.commit.committed_per_cycle::0 136598241 69.29% 69.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 33559109 17.02% 86.31% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 12649949 6.42% 92.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3238672 1.64% 94.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 4912875 2.49% 96.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 2898818 1.47% 98.33% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1203082 0.61% 98.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 557487 0.28% 99.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1529616 0.78% 100.00% # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu0.commit.committed_per_cycle::total 197147849 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 104125280 # Number of instructions committed
system.cpu0.commit.committedOps 126078442 # Number of ops (including micro ops) committed
2011-08-19 22:08:09 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
2016-10-14 00:21:40 +02:00
system.cpu0.commit.refs 40877611 # Number of memory references committed
system.cpu0.commit.loads 22690736 # Number of loads committed
system.cpu0.commit.membars 648887 # Number of memory barriers committed
system.cpu0.commit.branches 25008531 # Number of branches committed
2016-05-31 12:07:18 +02:00
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
2016-10-14 00:21:40 +02:00
system.cpu0.commit.int_insts 110051272 # Number of committed integer instructions.
system.cpu0.commit.function_calls 4840996 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::IntAlu 85084925 67.49% 67.49% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 108043 0.09% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 7863 0.01% 67.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 22690736 18.00% 85.57% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 18186875 14.43% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::total 126078442 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1529616 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 307952651 # The number of ROB reads
system.cpu0.rob.rob_writes 274451297 # The number of ROB writes
system.cpu0.timesIdled 137106 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 4460980 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5448417066 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 104003228 # Number of Instructions Simulated
system.cpu0.committedOps 125956390 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.968910 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.968910 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.507895 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.507895 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 142940096 # number of integer regfile reads
system.cpu0.int_regfile_writes 81795281 # number of integer regfile writes
system.cpu0.fp_regfile_reads 8203 # number of floating regfile reads
2016-05-31 12:07:18 +02:00
system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes
2016-10-14 00:21:40 +02:00
system.cpu0.cc_regfile_reads 465685863 # number of cc regfile reads
system.cpu0.cc_regfile_writes 49834738 # number of cc regfile writes
system.cpu0.misc_regfile_reads 394201906 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1226279 # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 711042 # number of replacements
system.cpu0.dcache.tags.tagsinuse 497.782039 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 37710898 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 711554 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 52.997943 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.782039 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972231 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.972231 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu0.dcache.tags.tag_accesses 81278285 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 81278285 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 21483760 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 21483760 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 15003255 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15003255 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307803 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 307803 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363087 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 363087 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361616 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 361616 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 36487015 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 36487015 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 36794818 # number of overall hits
system.cpu0.dcache.overall_hits::total 36794818 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 647587 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 647587 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1894796 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1894796 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148778 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 148778 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25560 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 25560 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20165 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20165 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2542383 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2542383 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2691161 # number of overall misses
system.cpu0.dcache.overall_misses::total 2691161 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9361035000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 9361035000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33017805879 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 33017805879 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 412521000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 412521000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 476921000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 476921000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 443000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 443000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 42378840879 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 42378840879 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 42378840879 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 42378840879 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 22131347 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 22131347 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 16898051 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 16898051 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456581 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 456581 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388647 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 388647 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381781 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381781 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 39029398 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 39029398 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 39485979 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 39485979 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029261 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.029261 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112131 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.112131 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325852 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325852 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065767 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065767 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052818 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052818 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065140 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.065140 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068155 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.068155 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14455.254661 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14455.254661 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17425.520150 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17425.520150 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16139.319249 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16139.319249 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23650.929829 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23650.929829 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-10-14 00:21:40 +02:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16668.944403 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16668.944403 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15747.419377 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15747.419377 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 4996394 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 202489 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 24.674891 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 711042 # number of writebacks
system.cpu0.dcache.writebacks::total 711042 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260652 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 260652 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569869 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1569869 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18798 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18798 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830521 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1830521 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830521 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1830521 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 386935 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 386935 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324927 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 324927 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102518 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 102518 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6762 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6762 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20165 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20165 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 711862 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 711862 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 814380 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 814380 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28457 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60239 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5003581000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5003581000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626488404 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626488404 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1706140000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1706140000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107183000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107183000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 456767000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 456767000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 432000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 432000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11630069404 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 11630069404 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13336209404 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 13336209404 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6624172500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6624172500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6624172500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6624172500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017484 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017484 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019229 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019229 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224534 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224534 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017399 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017399 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052818 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052818 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.018239 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020625 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.020625 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12931.321798 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12931.321798 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20393.775845 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20393.775845 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16642.345734 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16642.345734 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15850.783792 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15850.783792 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22651.475329 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22651.475329 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16337.533685 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16337.533685 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16375.904865 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16375.904865 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208425.287899 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208425.287899 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109964.848354 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109964.848354 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1252192 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.757674 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 71518552 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1252703 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 57.091387 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6585004000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757674 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu0.icache.tags.tag_accesses 146904258 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 146904258 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 71518555 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 71518555 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 71518555 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 71518555 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 71518555 # number of overall hits
system.cpu0.icache.overall_hits::total 71518555 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1307201 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1307201 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1307201 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1307201 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1307201 # number of overall misses
system.cpu0.icache.overall_misses::total 1307201 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14223203310 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14223203310 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14223203310 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14223203310 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14223203310 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14223203310 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 72825756 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 72825756 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 72825756 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 72825756 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 72825756 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 72825756 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017950 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.017950 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017950 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.017950 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017950 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.017950 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10880.655163 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10880.655163 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10880.655163 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10880.655163 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10880.655163 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10880.655163 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1774060 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 1996 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 116060 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.285714 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 153.538462 # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 1252192 # number of writebacks
system.cpu0.icache.writebacks::total 1252192 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54454 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 54454 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 54454 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 54454 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 54454 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 54454 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1252747 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1252747 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1252747 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1252747 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1252747 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1252747 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12840860811 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 12840860811 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12840860811 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 12840860811 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12840860811 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 12840860811 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017202 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.017202 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.017202 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10250.162891 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10250.162891 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10250.162891 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846192 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1848788 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 2354 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.prefetcher.pfSpanPage 238916 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 272116 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15645.226913 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 1883031 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 287760 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.543755 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.tags.occ_blocks::writebacks 14543.018555 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.670469 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.025524 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1089.512365 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.887635 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000712 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066499 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.954909 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15373 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 120 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 318 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1446 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7384 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4965 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1260 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.938293 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 67637085 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 67637085 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55351 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13068 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 68419 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 481133 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 481133 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 1450737 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 1450737 # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 220760 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 220760 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1181751 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1181751 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 388592 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 388592 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55351 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13068 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1181751 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 609352 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1859522 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55351 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13068 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1181751 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 609352 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1859522 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 507 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 200 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 707 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55745 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 55745 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20165 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 20165 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48603 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 48603 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70953 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 70953 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107504 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 107504 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 507 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 200 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 70953 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 156107 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 227767 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 507 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 200 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 70953 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 156107 # number of overall misses
system.cpu0.l2cache.overall_misses::total 227767 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 15335000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4771500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 20106500 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 35671000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 35671000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9320000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9320000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 415000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 415000 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3386740000 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 3386740000 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3777812500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3777812500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3493890998 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3493890998 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 15335000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4771500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3777812500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 6880630998 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 10678549998 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 15335000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4771500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3777812500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 6880630998 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 10678549998 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55858 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13268 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 69126 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481133 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 481133 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 1450737 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 1450737 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55745 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 55745 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20165 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20165 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269363 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 269363 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1252704 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 1252704 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 496096 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 496096 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55858 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13268 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1252704 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 765459 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2087289 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55858 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13268 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1252704 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 765459 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2087289 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009077 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015074 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.010228 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2016-03-16 21:03:49 +01:00
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180437 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180437 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056640 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056640 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216700 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216700 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009077 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015074 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056640 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.203939 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.109121 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009077 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015074 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056640 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.203939 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.109121 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30246.548323 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.500000 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28439.179632 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 639.895955 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 639.895955 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 462.186958 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 462.186958 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69681.706891 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69681.706891 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53243.872704 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53243.872704 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32500.102303 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32500.102303 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30246.548323 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.500000 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53243.872704 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44076.377088 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 46883.657413 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30246.548323 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.500000 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53243.872704 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44076.377088 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 46883.657413 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.unused_prefetches 10599 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 230738 # number of writebacks
system.cpu0.l2cache.writebacks::total 230738 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5942 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 5942 # number of ReadExReq MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 36 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 36 # number of ReadCleanReq MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 741 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 741 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 36 # number of demand (read+write) MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6683 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 6721 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 36 # number of overall MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6683 # number of overall MSHR hits
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system.cpu0.l2cache.ReadReq_mshr_misses::total 705 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262695 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 262695 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55745 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55745 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20165 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20165 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42661 # number of ReadExReq MSHR misses
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system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 70917 # number of ReadCleanReq MSHR misses
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system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable
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system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses
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system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of ReadReq MSHR miss cycles
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system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17363724717 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17363724717 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 962038500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 962038500 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304268499 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304268499 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 349000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 349000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2236694000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2236694000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3350952500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3350952500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2808325998 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2808325998 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3546000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3350952500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5045019998 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 8411811498 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3546000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3350952500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5045019998 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17363724717 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 25775536215 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6369584000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6634670000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6369584000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6634670000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010199 # mshr miss rate for ReadReq accesses
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2016-03-16 21:03:49 +01:00
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158377 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158377 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056611 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.215206 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.215206 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105901 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231756 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22466.666667 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66098.421047 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.843753 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.843753 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15088.941185 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15088.941185 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52429.478915 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52429.478915 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47251.752048 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26304.300160 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26304.300160 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38054.574604 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53283.753527 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200414.826002 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190706.237425 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105738.541476 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104900.943918 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 4079155 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2060991 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31388 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 213571 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 211819 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1752 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 114320 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1911393 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28457 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28457 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 712151 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 1482098 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 89271 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 330960 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 87226 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42590 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 113358 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 287646 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 284122 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1252747 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 585259 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 3214 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3763658 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2614734 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29156 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119485 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 6527033 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160361408 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98721444 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53072 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223432 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 259359356 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 926756 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 18862496 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 3052726 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.087981 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.285286 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu0.toL2Bus.snoop_fanout::0 2785896 91.26% 91.26% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 265078 8.68% 99.94% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 1752 0.06% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu0.toL2Bus.snoop_fanout::total 3052726 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 4077518993 # Layer occupancy (ticks)
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu0.toL2Bus.snoopLayer0.occupancy 113316466 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu0.toL2Bus.respLayer0.occupancy 1882577097 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu0.toL2Bus.respLayer1.occupancy 1233739845 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu0.toL2Bus.respLayer2.occupancy 15895485 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu0.toL2Bus.respLayer3.occupancy 63655441 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu1.branchPred.lookups 4630228 # Number of BP lookups
system.cpu1.branchPred.condPredicted 2728889 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 266806 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 2406642 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 1541904 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-10-14 00:21:40 +02:00
system.cpu1.branchPred.BTBHitPct 64.068690 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 874664 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 7405 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 249240 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 213278 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 35962 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 10619 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 21137 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 21137 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8393 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5852 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 6892 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 14245 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 645.419445 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 3393.467484 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 13571 95.27% 95.27% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191 196 1.38% 96.64% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287 230 1.61% 98.26% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383 102 0.72% 98.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.20% 99.17% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575 27 0.19% 99.36% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671 10 0.07% 99.43% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.45% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.04% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 10 0.07% 99.99% # Table walker wait (enqueue to first request) latency
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
2016-10-14 00:21:40 +02:00
system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 14245 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 5483 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11374.338866 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 9975.216104 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 6340.433585 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 1893 34.52% 34.52% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2927 53.38% 87.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 431 7.86% 95.77% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 169 3.08% 98.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 33 0.60% 99.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.44% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 5483 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 77531116060 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.220578 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.418371 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 60476667848 78.00% 78.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 17032378712 21.97% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2 12865500 0.02% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3 4248000 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4 1183000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5 1086000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6 1322500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7 461500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8 217000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9 174500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10 136000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11 33500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12 198000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13 27000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14 21000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 77531116060 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1915 74.80% 74.80% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 645 25.20% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2560 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21137 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21137 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2560 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2560 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 23697 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-10-14 00:21:40 +02:00
system.cpu1.dtb.read_hits 4149269 # DTB read hits
system.cpu1.dtb.read_misses 18244 # DTB read misses
system.cpu1.dtb.write_hits 3464998 # DTB write hits
system.cpu1.dtb.write_misses 2893 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-10-14 00:21:40 +02:00
system.cpu1.dtb.flush_entries 1955 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-10-14 00:21:40 +02:00
system.cpu1.dtb.perms_faults 410 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 4167513 # DTB read accesses
system.cpu1.dtb.write_accesses 3467891 # DTB write accesses
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-10-14 00:21:40 +02:00
system.cpu1.dtb.hits 7614267 # DTB hits
system.cpu1.dtb.misses 21137 # DTB misses
system.cpu1.dtb.accesses 7635404 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 5745 # Table walker walks requested
system.cpu1.itb.walker.walksShort 5745 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2522 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2644 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 579 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 5166 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 354.045683 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 2100.129090 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-2047 4967 96.15% 96.15% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.83% 96.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-6143 47 0.91% 97.89% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.41% 98.30% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-10239 19 0.37% 98.66% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::10240-12287 23 0.45% 99.11% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-14335 19 0.37% 99.48% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::14336-16383 7 0.14% 99.61% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.12% 99.73% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::18432-20479 1 0.02% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-22527 4 0.08% 99.83% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::22528-24575 1 0.02% 99.85% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.04% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::26624-28671 3 0.06% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-30719 3 0.06% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 5166 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1734 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12119.088812 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10982.617612 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5990.262254 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191 321 18.51% 18.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383 1223 70.53% 89.04% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575 108 6.23% 95.27% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767 58 3.34% 98.62% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959 14 0.81% 99.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.23% 99.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343 5 0.29% 99.94% # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
2016-10-14 00:21:40 +02:00
system.cpu1.itb.walker.walkCompletionTime::total 1734 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 17381208916 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.871345 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.334946 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 2236929264 12.87% 12.87% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 15143532152 87.13% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 747500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 17381208916 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 985 85.28% 85.28% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 170 14.72% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1155 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5745 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5745 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 6900 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 8164971 # ITB inst hits
system.cpu1.itb.inst_misses 5745 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-10-14 00:21:40 +02:00
system.cpu1.itb.flush_entries 1122 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-10-14 00:21:40 +02:00
system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-10-14 00:21:40 +02:00
system.cpu1.itb.inst_accesses 8170716 # ITB inst accesses
system.cpu1.itb.hits 8164971 # DTB hits
system.cpu1.itb.misses 5745 # DTB misses
system.cpu1.itb.accesses 8170716 # DTB accesses
system.cpu1.numPwrStateTransitions 5463 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 2732 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 1028238405.084919 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 25963867647.326580 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 1944 71.16% 71.16% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 782 28.62% 99.78% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state
2016-10-14 00:21:40 +02:00
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 959984033604 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 2732 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 17447601808 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809147322692 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 34895980 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-10-14 00:21:40 +02:00
system.cpu1.fetch.icacheStallCycles 8706814 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 24545743 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 4630228 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 2629846 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 24236084 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 776070 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 77763 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 35252 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 165739 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 299959 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 23654 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 8163829 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 107624 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2029 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 33933300 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.881300 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.218696 # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu1.fetch.rateDist::0 20192419 59.51% 59.51% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 4836103 14.25% 73.76% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 1645003 4.85% 78.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 7259775 21.39% 100.00% # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu1.fetch.rateDist::total 33933300 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.132687 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.703397 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 7185713 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 16755217 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 8648276 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1081250 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 262844 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 705359 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 127834 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 23145137 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 1030723 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 262844 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 8592488 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2388926 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 11714810 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 8302740 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 2671492 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 21985761 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 184128 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 260119 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 36299 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 16259 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1667149 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 21955593 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 102445019 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 25352022 # Number of integer rename lookups
2016-08-12 15:12:59 +02:00
system.cpu1.rename.fp_rename_lookups 1683 # Number of floating rename lookups
2016-10-14 00:21:40 +02:00
system.cpu1.rename.CommittedMaps 19598713 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 2356880 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 406325 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 333389 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 2861472 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 4400097 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 3772059 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 619281 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 624174 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 21175375 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 559463 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 20999121 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 90560 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 2005952 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 4627057 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 43664 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 33933300 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.618835 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.947092 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-10-14 00:21:40 +02:00
system.cpu1.iq.issued_per_cycle::0 21549433 63.51% 63.51% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 6114741 18.02% 81.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 4178352 12.31% 93.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 1835426 5.41% 99.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 255342 0.75% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 6 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-10-14 00:21:40 +02:00
system.cpu1.iq.issued_per_cycle::total 33933300 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-10-14 00:21:40 +02:00
system.cpu1.iq.fu_full::IntAlu 1405486 29.50% 29.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 669 0.01% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.52% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1602534 33.64% 63.16% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 1754875 36.84% 100.00% # attempts to use FU when none available
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu1.iq.FU_type_0::IntAlu 12960054 61.72% 61.72% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 27621 0.13% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 3265 0.02% 61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 4356029 20.74% 82.61% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 3652086 17.39% 100.00% # Type of FU issued
2011-08-19 22:08:09 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu1.iq.FU_type_0::total 20999121 # Type of FU issued
system.cpu1.iq.rate 0.601763 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4763564 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.226846 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 80779382 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 23748142 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 20541259 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 6284 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2076 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1790 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 25758471 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 4148 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 87109 # Number of loads that had data forwarded from stores
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-10-14 00:21:40 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 405898 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 640 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 9457 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 249525 # Number of stores squashed
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-10-14 00:21:40 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 40585 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 76754 # Number of times an access to memory failed due to the cache being blocked
2011-08-19 22:08:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-10-14 00:21:40 +02:00
system.cpu1.iew.iewSquashCycles 262844 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 543765 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 103558 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 21775845 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-10-14 00:21:40 +02:00
system.cpu1.iew.iewDispLoadInsts 4400097 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 3772059 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 296163 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 7694 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 88949 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 9457 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 34239 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 118390 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 152629 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 20771745 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 4261184 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 206260 # Number of squashed instructions skipped in execute
2011-08-19 22:08:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
2016-10-14 00:21:40 +02:00
system.cpu1.iew.exec_nop 41007 # number of nop insts executed
system.cpu1.iew.exec_refs 7864490 # number of memory reference insts executed
system.cpu1.iew.exec_branches 3010595 # Number of branches executed
system.cpu1.iew.exec_stores 3603306 # Number of stores executed
system.cpu1.iew.exec_rate 0.595248 # Inst execution rate
system.cpu1.iew.wb_sent 20641556 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 20543049 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 10275425 # num instructions producing a value
system.cpu1.iew.wb_consumers 16109782 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.588694 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.637838 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 1795274 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 515799 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 141615 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 33527734 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.589415 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.349112 # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu1.commit.committed_per_cycle::0 24087304 71.84% 71.84% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 5545630 16.54% 88.38% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1675188 5.00% 93.38% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 660381 1.97% 95.35% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 508267 1.52% 96.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 330740 0.99% 97.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 223183 0.67% 98.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 117603 0.35% 98.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 379438 1.13% 100.00% # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu1.commit.committed_per_cycle::total 33527734 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 16118487 # Number of instructions committed
system.cpu1.commit.committedOps 19761740 # Number of ops (including micro ops) committed
2011-08-19 22:08:09 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2016-10-14 00:21:40 +02:00
system.cpu1.commit.refs 7516733 # Number of memory references committed
system.cpu1.commit.loads 3994199 # Number of loads committed
system.cpu1.commit.membars 208310 # Number of memory barriers committed
system.cpu1.commit.branches 2858693 # Number of branches committed
2016-05-31 12:07:18 +02:00
system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
2016-10-14 00:21:40 +02:00
system.cpu1.commit.int_insts 17575462 # Number of committed integer instructions.
system.cpu1.commit.function_calls 459876 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu1.commit.op_class_0::IntAlu 12215165 61.81% 61.81% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 26577 0.13% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 3265 0.02% 61.96% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.96% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.96% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.96% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 3994199 20.21% 82.17% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 3522534 17.83% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu1.commit.op_class_0::total 19761740 # Class of committed instruction
system.cpu1.commit.bw_lim_events 379438 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 53719965 # The number of ROB reads
system.cpu1.rob.rob_writes 43510270 # The number of ROB writes
system.cpu1.timesIdled 58110 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 962680 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5617725351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 16085632 # Number of Instructions Simulated
system.cpu1.committedOps 19728885 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.169388 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.169388 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.460959 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.460959 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 23317955 # number of integer regfile reads
system.cpu1.int_regfile_writes 13332838 # number of integer regfile writes
system.cpu1.fp_regfile_reads 1403 # number of floating regfile reads
2016-05-31 12:07:18 +02:00
system.cpu1.fp_regfile_writes 516 # number of floating regfile writes
2016-10-14 00:21:40 +02:00
system.cpu1.cc_regfile_reads 74580678 # number of cc regfile reads
system.cpu1.cc_regfile_writes 6681708 # number of cc regfile writes
system.cpu1.misc_regfile_reads 69976526 # number of misc regfile reads
system.cpu1.misc_regfile_writes 387406 # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 185136 # number of replacements
system.cpu1.dcache.tags.tagsinuse 468.617373 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 6737062 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 185477 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 36.322897 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 89354157500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.617373 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915268 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.915268 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 14947542 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 14947542 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 3587773 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 3587773 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 2897885 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 2897885 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49072 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 49072 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78768 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 78768 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70845 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 70845 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 6485658 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 6485658 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 6534730 # number of overall hits
system.cpu1.dcache.overall_hits::total 6534730 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 212319 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 212319 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 390908 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 390908 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 29887 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 29887 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18355 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 18355 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23465 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23465 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 603227 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 603227 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 633114 # number of overall misses
system.cpu1.dcache.overall_misses::total 633114 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3545506500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3545506500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9944995958 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 9944995958 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362846000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 362846000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551070500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 551070500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 640500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 640500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 13490502458 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 13490502458 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 13490502458 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 13490502458 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 3800092 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 3800092 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 3288793 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 3288793 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 78959 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 78959 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97123 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 97123 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94310 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 94310 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 7088885 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 7088885 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 7167844 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 7167844 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055872 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.055872 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118861 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.118861 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378513 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378513 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188987 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188987 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248807 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248807 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085095 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.085095 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088327 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.088327 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16698.960055 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16698.960055 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25440.758332 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25440.758332 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19768.237537 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19768.237537 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23484.785851 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23484.785851 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-10-14 00:21:40 +02:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22363.890307 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 22363.890307 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21308.172711 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 21308.172711 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1473013 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 39225 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 37.552913 # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 185136 # number of writebacks
system.cpu1.dcache.writebacks::total 185136 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 77580 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 77580 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 301933 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 301933 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13088 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13088 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 379513 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 379513 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 379513 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 379513 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134739 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 134739 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 88975 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 88975 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28539 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 28539 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5267 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5267 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23465 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23465 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 223714 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 223714 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 252253 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 252253 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3386 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3386 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2740 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6126 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6126 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1970715500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1970715500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2395378969 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2395378969 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 480267000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 480267000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 94406500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 94406500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527620500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527620500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 625500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 625500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4366094469 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4366094469 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846361469 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4846361469 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 459425000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 459425000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 459425000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 459425000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035457 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035457 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027054 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027054 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361441 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361441 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054230 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054230 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248807 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248807 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031558 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.031558 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035192 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.035192 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14626.169854 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14626.169854 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26921.932779 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26921.932779 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16828.445285 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16828.445285 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17924.150370 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17924.150370 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22485.425101 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22485.425101 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19516.411440 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19516.411440 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19212.304587 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19212.304587 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135683.697578 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 135683.697578 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 74995.919034 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 74995.919034 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 583486 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.437314 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 7557735 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 583998 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 12.941371 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 79127078000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.437314 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975464 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975464 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu1.icache.tags.tag_accesses 16911139 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 16911139 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 7557735 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 7557735 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 7557735 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 7557735 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 7557735 # number of overall hits
system.cpu1.icache.overall_hits::total 7557735 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 605833 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 605833 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 605833 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 605833 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 605833 # number of overall misses
system.cpu1.icache.overall_misses::total 605833 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5683938295 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5683938295 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5683938295 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5683938295 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5683938295 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5683938295 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 8163568 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 8163568 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 8163568 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 8163568 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 8163568 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 8163568 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074212 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.074212 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074212 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.074212 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074212 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.074212 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9382.021605 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9382.021605 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9382.021605 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9382.021605 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9382.021605 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9382.021605 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 514122 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu1.icache.blocked::no_mshrs 41357 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.431318 # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu1.icache.writebacks::writebacks 583486 # number of writebacks
system.cpu1.icache.writebacks::total 583486 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21830 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 21830 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 21830 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 21830 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 21830 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 21830 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 584003 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 584003 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 584003 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 584003 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 584003 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 584003 # number of overall MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses
2016-10-14 00:21:40 +02:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5223422114 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5223422114 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5223422114 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5223422114 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5223422114 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5223422114 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9321999 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9321999 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9321999 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 9321999 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071538 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.071538 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.071538 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8944.170003 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92297.019802 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92297.019802 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 192037 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 192612 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 514 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.prefetcher.pfSpanPage 57820 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 43247 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 14634.111672 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 688069 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 57318 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 12.004414 # Average number of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.tags.occ_blocks::writebacks 14183.524826 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.708728 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.055002 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 436.823115 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.865694 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000715 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026662 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.893195 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 321 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13723 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 183 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8668 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3318 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.019592 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001648 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.837585 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 27096059 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 27096059 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16526 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 5997 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 22523 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 112708 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 112708 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 643666 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 643666 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 26963 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 26963 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 560151 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 560151 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97699 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 97699 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16526 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 5997 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 560151 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 124662 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 707336 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16526 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 5997 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 560151 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 124662 # number of overall hits
system.cpu1.l2cache.overall_hits::total 707336 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 498 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 291 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 789 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29191 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 29191 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23465 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 23465 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33482 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 33482 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 23849 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 23849 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 70829 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 70829 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 498 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 291 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 23849 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 104311 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 128949 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 498 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 291 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 23849 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 104311 # number of overall misses
system.cpu1.l2cache.overall_misses::total 128949 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11142500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5993500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 17136000 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12596500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 12596500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 19283000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 19283000 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 603000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 603000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1436185500 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1436185500 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 937727500 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 937727500 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1638546999 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1638546999 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11142500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5993500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 937727500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3074732499 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 4029595999 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11142500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5993500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 937727500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3074732499 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 4029595999 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17024 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6288 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 23312 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 112708 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 112708 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 643666 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 643666 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29191 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 29191 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23465 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23465 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60445 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 60445 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 584000 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 584000 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168528 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 168528 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17024 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6288 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 584000 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 228973 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 836285 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17024 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6288 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 584000 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 228973 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 836285 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.029253 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046279 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.553925 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.553925 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040837 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040837 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.420280 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.420280 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.029253 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046279 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040837 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.455560 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.154193 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.029253 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046279 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040837 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.455560 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.154193 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22374.497992 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20596.219931 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21718.631179 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 431.519989 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 431.519989 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 821.777115 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 821.777115 # average SCUpgradeReq miss latency
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42894.256615 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42894.256615 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39319.363495 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39319.363495 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23133.843468 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23133.843468 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22374.497992 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20596.219931 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39319.363495 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29476.589228 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 31249.532753 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22374.497992 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20596.219931 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39319.363495 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29476.589228 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 31249.532753 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.unused_prefetches 817 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 30888 # number of writebacks
system.cpu1.l2cache.writebacks::total 30888 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 456 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 456 # number of ReadExReq MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 69 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 69 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 525 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 525 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 535 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 498 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 290 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 788 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25130 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 25130 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29191 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29191 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23465 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23465 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33026 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 33026 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 23840 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 23840 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 70760 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 70760 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 498 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 290 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 23840 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103786 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 128414 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 498 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 290 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 23840 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103786 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25130 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 153544 # number of overall MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3386 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3487 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2740 # number of WriteReq MSHR uncacheable
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 6126 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 6227 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4235000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12389500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1120294346 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1120294346 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 448208500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 448208500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 351353500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 351353500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 513000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 513000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1175287000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1175287000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 794529500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 794529500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1211572499 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1211572499 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4235000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 794529500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2386859499 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 3193778499 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4235000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 794529500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2386859499 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1120294346 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 4314072845 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8564000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 432303000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 440867000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8564000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 432303000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 440867000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.033802 # mshr miss rate for ReadReq accesses
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546381 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546381 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040822 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.419871 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.419871 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153553 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183602 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15722.715736 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44579.958058 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15354.338666 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15354.338666 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14973.513744 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14973.513744 # average SCUpgradeReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35586.719554 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35586.719554 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33327.579698 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17122.279522 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17122.279522 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24870.952536 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28096.655324 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127673.656232 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126431.603097 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 70568.560235 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70799.261282 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 1644268 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 831312 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 115055 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106415 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8640 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 31394 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 822139 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2740 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2740 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 144852 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 655914 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 29483 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 30330 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 71834 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 85505 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 67721 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 64923 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 584003 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 271211 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 307 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1751691 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 836213 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14098 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37121 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2639123 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74720720 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29257698 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25152 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68096 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 104071666 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 343275 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 4808780 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 1162877 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.125522 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.353024 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu1.toL2Bus.snoop_fanout::0 1025550 88.19% 88.19% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 128687 11.07% 99.26% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 8640 0.74% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu1.toL2Bus.snoop_fanout::total 1162877 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 1604189995 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu1.toL2Bus.snoopLayer0.occupancy 80522049 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu1.toL2Bus.respLayer0.occupancy 876204799 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu1.toL2Bus.respLayer1.occupancy 375699214 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu1.toL2Bus.respLayer2.occupancy 7819481 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu1.toL2Bus.respLayer3.occupancy 20111970 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
system.iobus.trans_dist::WriteResp 59421 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer0.occupancy 40380000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer2.occupancy 328000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer8.occupancy 570500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer23.occupancy 6100500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer24.occupancy 33792000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer25.occupancy 187796551 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.iocache.tags.replacements 36458 # number of replacements
2016-10-14 00:21:40 +02:00
system.iocache.tags.tagsinuse 14.553749 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2016-05-31 17:55:47 +02:00
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.iocache.tags.warmup_cycle 255488373000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.553749 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.909609 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.909609 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-05-31 17:55:47 +02:00
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
2016-10-14 00:21:40 +02:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-05-31 17:55:47 +02:00
system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36476 # number of overall misses
system.iocache.overall_misses::total 36476 # number of overall misses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_miss_latency::realview.ide 40604377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 40604377 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4366091174 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4366091174 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4406695551 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4406695551 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4406695551 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4406695551 # number of overall miss cycles
2016-05-31 17:55:47 +02:00
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 161128.480159 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 161128.480159 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120530.343805 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120530.343805 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120810.822212 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120810.822212 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 5.750000 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
2016-05-31 17:55:47 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2016-05-31 17:55:47 +02:00
system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 28004377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 28004377 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2552566881 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2552566881 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2580571258 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2580571258 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2580571258 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2580571258 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111128.480159 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 111128.480159 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70466.179356 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70466.179356 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 137609 # number of replacements
system.l2c.tags.tagsinuse 65136.051895 # Cycle average of tags in use
system.l2c.tags.total_refs 548833 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 202971 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.703997 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 87466496000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 5939.611941 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.674941 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 1.061639 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 8089.660546 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 7047.830837 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37514.795432 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.739703 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.908322 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1674.813935 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2903.059558 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1945.895041 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.090631 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000239 # Average percentage of cache occupancy
2016-05-31 12:07:18 +02:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
2016-10-14 00:21:40 +02:00
system.l2c.tags.occ_percent::cpu0.inst 0.123438 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.107541 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572430 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
2016-03-16 21:03:49 +01:00
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
2016-10-14 00:21:40 +02:00
system.l2c.tags.occ_percent::cpu1.inst 0.025556 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.044297 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029692 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993897 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 33502 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 31839 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 401 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 6111 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 26990 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.l2c.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4972 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 26706 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.511200 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000320 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.485825 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6298618 # Number of tag accesses
system.l2c.tags.data_accesses 6298618 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 261626 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 261626 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 41310 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4699 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 46009 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2684 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 2210 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 4894 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 3978 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1342 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5320 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 248 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 107 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 50964 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 57616 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46197 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 67 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 21124 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 11550 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4807 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 192709 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 248 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 107 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 50964 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 61594 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 46197 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 67 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 21124 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 12892 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 4807 # number of demand (read+write) hits
system.l2c.demand_hits::total 198029 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 248 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 107 # number of overall hits
system.l2c.overall_hits::cpu0.inst 50964 # number of overall hits
system.l2c.overall_hits::cpu0.data 61594 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 46197 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 67 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits
system.l2c.overall_hits::cpu1.inst 21124 # number of overall hits
system.l2c.overall_hits::cpu1.data 12892 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 4807 # number of overall hits
system.l2c.overall_hits::total 198029 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 543 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 291 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 834 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 92 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 104 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 196 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 11177 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8193 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 19370 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 29 # number of ReadSharedReq misses
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
2016-10-14 00:21:40 +02:00
system.l2c.ReadSharedReq_misses::cpu0.inst 19953 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 9351 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131846 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 4 # number of ReadSharedReq misses
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
2016-10-14 00:21:40 +02:00
system.l2c.ReadSharedReq_misses::cpu1.inst 2712 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 981 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6675 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 171555 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses
2016-05-31 12:07:18 +02:00
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
2016-10-14 00:21:40 +02:00
system.l2c.demand_misses::cpu0.inst 19953 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 20528 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 131846 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
2016-08-12 15:12:59 +02:00
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
2016-10-14 00:21:40 +02:00
system.l2c.demand_misses::cpu1.inst 2712 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 9174 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 6675 # number of demand (read+write) misses
system.l2c.demand_misses::total 190925 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses
2016-05-31 12:07:18 +02:00
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
2016-10-14 00:21:40 +02:00
system.l2c.overall_misses::cpu0.inst 19953 # number of overall misses
system.l2c.overall_misses::cpu0.data 20528 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 131846 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
2016-10-14 00:21:40 +02:00
system.l2c.overall_misses::cpu1.inst 2712 # number of overall misses
system.l2c.overall_misses::cpu1.data 9174 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 6675 # number of overall misses
system.l2c.overall_misses::total 190925 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 8706000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 803000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 9509000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 672000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 510500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 1182500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1649911000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 752041000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2401952000 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 3955500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 249000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2094281000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 1081713000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16526295038 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 903500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 89500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 288810000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 120918000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1010031515 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 21127246053 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 3955500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 249000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 2094281000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 2731624000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16526295038 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 903500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 89500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 288810000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 872959000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1010031515 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 23529198053 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 3955500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 249000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 2094281000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 2731624000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16526295038 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 903500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 89500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 288810000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 872959000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1010031515 # number of overall miss cycles
system.l2c.overall_miss_latency::total 23529198053 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 261626 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 261626 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 41853 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4990 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 46843 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 2776 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 2314 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 5090 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 15155 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 9535 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 24690 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 277 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 110 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 70917 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 66967 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 178043 # number of ReadSharedReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 71 # number of ReadSharedReq accesses(hits+misses)
2016-10-14 00:21:40 +02:00
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 23836 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 12531 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11482 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 364264 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 277 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 110 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 70917 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 82122 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 178043 # number of demand (read+write) accesses
2016-08-12 15:12:59 +02:00
system.l2c.demand_accesses::cpu1.dtb.walker 71 # number of demand (read+write) accesses
2016-10-14 00:21:40 +02:00
system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 23836 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 22066 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11482 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 388954 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 277 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 110 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 70917 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 82122 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 178043 # number of overall (read+write) accesses
2016-08-12 15:12:59 +02:00
system.l2c.overall_accesses::cpu1.dtb.walker 71 # number of overall (read+write) accesses
2016-10-14 00:21:40 +02:00
system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 23836 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 22066 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11482 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 388954 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012974 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.058317 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.017804 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.033141 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.044944 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.038507 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.737512 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.859255 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.784528 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.104693 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027273 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.281357 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.139636 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.740529 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.056338 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.033333 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.113777 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078286 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.581345 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.470963 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.104693 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.027273 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.281357 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.249970 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.740529 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.056338 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.033333 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.113777 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.415753 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.581345 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.490868 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.104693 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.027273 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.281357 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.249970 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.740529 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.056338 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.033333 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.113777 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.415753 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.581345 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.490868 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16033.149171 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2759.450172 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 11401.678657 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7304.347826 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4908.653846 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 6033.163265 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 147616.623423 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 91790.674966 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 124003.717088 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136396.551724 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 104960.707663 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 115678.857876 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 225875 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89500 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 106493.362832 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123259.938838 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 123151.444452 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136396.551724 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 104960.707663 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 133068.199532 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 225875 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 106493.362832 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 95155.766296 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 123237.910452 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136396.551724 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 104960.707663 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 133068.199532 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 125345.441181 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 225875 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 106493.362832 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 95155.766296 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 151315.582772 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 123237.910452 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 225 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.l2c.writebacks::writebacks 101341 # number of writebacks
system.l2c.writebacks::total 101341 # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 1 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
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system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 4056 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 4056 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 543 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 291 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 834 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 92 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 104 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 196 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 11177 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 8193 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 19370 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadSharedReq MSHR misses
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
2016-10-14 00:21:40 +02:00
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19952 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9351 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131846 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadSharedReq MSHR misses
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
2016-10-14 00:21:40 +02:00
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2712 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 981 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6675 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 171554 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses
2016-05-31 12:07:18 +02:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
2016-10-14 00:21:40 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 19952 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 20528 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131846 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses
2016-08-12 15:12:59 +02:00
system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
2016-10-14 00:21:40 +02:00
system.l2c.demand_mshr_misses::cpu1.inst 2712 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 9174 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6675 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 190924 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 19952 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.l2c.overall_mshr_misses::cpu1.inst 2712 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 9174 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6675 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 190924 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable
2016-07-21 18:19:18 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
2016-10-14 00:21:40 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3383 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 38274 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 31197 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses
2016-07-21 18:19:18 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
2016-10-14 00:21:40 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6123 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 69471 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12087000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6019500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 18106500 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2426500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2307500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 4734000 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 670111000 # number of ReadExReq MSHR miss cycles
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system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3665500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 219000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1894738504 # number of ReadSharedReq MSHR miss cycles
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system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 863500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 79500 # number of ReadSharedReq MSHR miss cycles
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system.l2c.ReadSharedReq_mshr_miss_latency::total 19411677070 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3665500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 219000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 1894738504 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2526343501 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 863500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 79500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 261689501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 781219000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 943281016 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 21619928571 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3665500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 219000 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 863500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 79500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 261689501 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::total 21619928571 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 210941500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5797437001 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6745000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 371342000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6386465501 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 210941500 # number of overall MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6745000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 371342000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6386465501 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-10-14 00:21:40 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012974 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.058317 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.017804 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.033141 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.044944 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.038507 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737512 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.859255 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.784528 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.139636 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078286 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470961 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.490865 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.490865 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22259.668508 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20685.567010 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21710.431655 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26375 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22187.500000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24153.061224 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137616.578778 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 81790.674966 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 114003.691327 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105678.857876 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113259.938838 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113151.993367 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182412.592065 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109767.070647 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166861.720777 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96240.591660 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60647.068431 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 91929.949202 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 504773 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 283620 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2016-05-31 17:55:47 +02:00
system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-05-31 12:07:18 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 38274 # Transaction distribution
system.membus.trans_dist::ReadResp 210079 # Transaction distribution
system.membus.trans_dist::WriteReq 31197 # Transaction distribution
system.membus.trans_dist::WriteResp 31197 # Transaction distribution
system.membus.trans_dist::WritebackDirty 137547 # Transaction distribution
system.membus.trans_dist::CleanEvict 17007 # Transaction distribution
system.membus.trans_dist::UpgradeReq 64594 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 38710 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::ReadExReq 38808 # Transaction distribution
system.membus.trans_dist::ReadExResp 19352 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 171806 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14870 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638456 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 761276 # Packet count per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_count::total 834225 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29740 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18751880 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18944702 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_size::total 21262846 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 122284 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 36480 # Total snoop traffic (bytes)
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::samples 419616 # Request fanout histogram
system.membus.snoop_fanout::mean 0.012440 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.110839 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::0 414396 98.76% 98.76% # Request fanout histogram
system.membus.snoop_fanout::1 5220 1.24% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::total 419616 # Request fanout histogram
system.membus.reqLayer0.occupancy 81572000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.reqLayer2.occupancy 12355500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.reqLayer5.occupancy 987789803 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.respLayer2.occupancy 1102143190 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.respLayer3.occupancy 1335877 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-10-14 00:21:40 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 1044068 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 554075 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 185190 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 28829 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 27647 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 1182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 38277 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 522605 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 31197 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 31197 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 362967 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 130325 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 110585 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 43604 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 154189 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 50073 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 50073 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 484331 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 4646 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1303151 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320962 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1624113 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36235416 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5679078 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 41914494 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 390245 # Total snoops (count)
system.toL2Bus.snoopTraffic 15796172 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 900374 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.402074 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.492987 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.toL2Bus.snoop_fanout::0 539539 59.92% 59.92% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 359653 39.94% 99.87% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 1182 0.13% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.toL2Bus.snoop_fanout::total 900374 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 896925065 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.toL2Bus.respLayer0.occupancy 692605391 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.toL2Bus.respLayer1.occupancy 242340870 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2011-08-19 22:08:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-10-14 00:21:40 +02:00
system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-10-14 00:21:40 +02:00
system.cpu1.kern.inst.quiesce 2732 # number of quiesce instructions executed
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
