gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.824570                       # Number of seconds simulated
sim_ticks                                2824570221000                       # Number of ticks simulated
final_tick                               2824570221000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  42227                       # Simulator instruction rate (inst/s)
host_op_rate                                    51230                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              992732164                       # Simulator tick rate (ticks/s)
host_mem_usage                                 776620                       # Number of bytes of host memory used
host_seconds                                  2845.25                       # Real time elapsed on the host
sim_insts                                   120145307                       # Number of instructions simulated
sim_ops                                     145762315                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker         2176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           286752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1037180                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     10498560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            31952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           549024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher      1342912                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             13750604                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       286752                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        31952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          318704                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9574272                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9592016                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker           34                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              6726                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             16731                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       164040                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               566                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8602                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher        20983                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                217714                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149598                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               154034                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           770                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           136                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              101521                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              367199                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3716870                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           227                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               11312                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              194374                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       475439                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4868211                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         101521                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          11312                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             112833                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3389639                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6268                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3395921                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3389639                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          770                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          136                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             101521                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             373467                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3716870                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          227                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              11312                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             194389                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       475439                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                8264132                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        217714                       # Number of read requests accepted
system.physmem.writeReqs                       190258                       # Number of write requests accepted
system.physmem.readBursts                      217714                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     190258                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 13924352                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  11782272                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  13750604                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               11910352                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    6131                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          13778                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               13720                       # Per bank write bursts
system.physmem.perBankRdBursts::1               13621                       # Per bank write bursts
system.physmem.perBankRdBursts::2               14360                       # Per bank write bursts
system.physmem.perBankRdBursts::3               14230                       # Per bank write bursts
system.physmem.perBankRdBursts::4               15917                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12969                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13917                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13922                       # Per bank write bursts
system.physmem.perBankRdBursts::8               13602                       # Per bank write bursts
system.physmem.perBankRdBursts::9               13356                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12792                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11688                       # Per bank write bursts
system.physmem.perBankRdBursts::12              13275                       # Per bank write bursts
system.physmem.perBankRdBursts::13              14168                       # Per bank write bursts
system.physmem.perBankRdBursts::14              13342                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12689                       # Per bank write bursts
system.physmem.perBankWrBursts::0               11837                       # Per bank write bursts
system.physmem.perBankWrBursts::1               11937                       # Per bank write bursts
system.physmem.perBankWrBursts::2               12245                       # Per bank write bursts
system.physmem.perBankWrBursts::3               12130                       # Per bank write bursts
system.physmem.perBankWrBursts::4               11220                       # Per bank write bursts
system.physmem.perBankWrBursts::5               11075                       # Per bank write bursts
system.physmem.perBankWrBursts::6               11642                       # Per bank write bursts
system.physmem.perBankWrBursts::7               11554                       # Per bank write bursts
system.physmem.perBankWrBursts::8               11490                       # Per bank write bursts
system.physmem.perBankWrBursts::9               11375                       # Per bank write bursts
system.physmem.perBankWrBursts::10              11404                       # Per bank write bursts
system.physmem.perBankWrBursts::11              11050                       # Per bank write bursts
system.physmem.perBankWrBursts::12              11716                       # Per bank write bursts
system.physmem.perBankWrBursts::13              11527                       # Per bank write bursts
system.physmem.perBankWrBursts::14              11100                       # Per bank write bursts
system.physmem.perBankWrBursts::15              10796                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2824568625000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                     559                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                    3083                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  214044                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 185822                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     53286                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     76786                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     20725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     15275                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     11050                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      9711                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      8821                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      8169                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      7162                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2458                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1453                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1085                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      636                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      453                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      285                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      205                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5834                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     7123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     8138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     9675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    10762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    11991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    12258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    13286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    12907                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    12909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    12445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    12840                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10514                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    10190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    10077                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     9379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      726                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      390                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      351                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        95193                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      270.047419                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     149.647814                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     324.885603                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          47290     49.68%     49.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18811     19.76%     69.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6810      7.15%     76.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3608      3.79%     80.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3189      3.35%     83.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2125      2.23%     85.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1286      1.35%     87.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1091      1.15%     88.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10983     11.54%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          95193                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7956                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.345777                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      514.192665                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7955     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7956                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7956                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.139517                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.869319                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       20.452539                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6216     78.13%     78.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             561      7.05%     85.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              92      1.16%     86.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             246      3.09%     89.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             152      1.91%     91.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              55      0.69%     92.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              34      0.43%     92.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              37      0.47%     92.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             126      1.58%     94.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              18      0.23%     94.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              19      0.24%     94.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               9      0.11%     95.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              35      0.44%     95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              15      0.19%     95.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               9      0.11%     95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              35      0.44%     96.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              47      0.59%     96.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              11      0.14%     97.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               5      0.06%     97.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               9      0.11%     97.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              88      1.11%     98.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.04%     98.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             8      0.10%     98.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.03%     98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            17      0.21%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             6      0.08%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             8      0.10%     98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.04%     98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            29      0.36%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135            10      0.13%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.03%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.05%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             7      0.09%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             7      0.09%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             5      0.06%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             6      0.08%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.01%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             3      0.04%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             5      0.06%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-251             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7956                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8935367250                       # Total ticks spent queuing
system.physmem.totMemAccLat               13014767250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1087840000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       41069.31                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  59819.31                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.93                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           4.17                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.87                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        4.22                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.29                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.31                       # Average write queue length when enqueuing
system.physmem.readRowHits                     184937                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    121536                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   85.00                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.01                       # Row buffer hit rate for writes
system.physmem.avgGap                      6923437.45                       # Average gap between requests
system.physmem.pageHitRate                      76.29                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2697464747500                       # Time in different power states
system.physmem.memoryStateTime::REF       94318380000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       32780541250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 374477040                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 345182040                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 204327750                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 188343375                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                878716800                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                818313600                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               606787200                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               586167840                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          184486751280                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          184486751280                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           79037968995                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           78368155155                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1625406641250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1625994197250                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1890995670315                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1890787110540                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.482406                       # Core power per rank (mW)
system.physmem.averagePower::1             669.408568                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           320                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          128                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          192                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          320                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             20                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           45                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           68                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total              113                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           45                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           68                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total          113                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           45                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           68                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total             113                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups               24032454                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         15719473                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect           977282                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            14661590                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               10774814                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            73.490078                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS                3879582                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect             32449                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    17723797                       # DTB read hits
system.cpu0.dtb.read_misses                     56461                       # DTB read misses
system.cpu0.dtb.write_hits                   14648555                       # DTB write hits
system.cpu0.dtb.write_misses                     8741                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3527                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      309                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2355                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      868                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                17780258                       # DTB read accesses
system.cpu0.dtb.write_accesses               14657296                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         32372352                       # DTB hits
system.cpu0.dtb.misses                          65202                       # DTB misses
system.cpu0.dtb.accesses                     32437554                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    37754755                       # ITB inst hits
system.cpu0.itb.inst_misses                     10287                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2369                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                     1949                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                37765042                       # ITB inst accesses
system.cpu0.itb.hits                         37754755                       # DTB hits
system.cpu0.itb.misses                          10287                       # DTB misses
system.cpu0.itb.accesses                     37765042                       # DTB accesses
system.cpu0.numCycles                       126967483                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          18140354                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     112726031                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                   24032454                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          14654396                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    104803073                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles                2823208                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                    134368                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               38414                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles       364228                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       430065                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles        37874                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 37755386                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes               265155                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                   3922                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         125359980                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.084816                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.263057                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                62797458     50.09%     50.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                21463892     17.12%     67.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 8767294      6.99%     74.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                32331336     25.79%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           125359980                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.189280                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.887834                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles                19213877                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles             58702572                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                 41417912                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles              4958150                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               1067469                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved             3055480                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred               348347                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             110732586                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              3998245                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               1067469                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles                24964892                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               12028946                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles      36555738                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                 40486723                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             10256212                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             105650222                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              1060720                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents              1433198                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                161272                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                 61252                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents               6057790                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands          109732658                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            482396625                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       120923658                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups             9389                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps             98143798                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                11588857                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts           1229050                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts       1087734                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 12319550                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            18736791                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           16202841                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          1700720                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         2277601                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 102690318                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded            1694621                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                100676052                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           483863                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined        9017764                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     22481770                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        122874                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    125359980                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.803096                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.034807                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0           69212985     55.21%     55.21% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           23181797     18.49%     73.70% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           22515986     17.96%     91.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3            9334603      7.45%     99.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            1114571      0.89%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5                 38      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      125359980                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                9379077     40.75%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                    80      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.75% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               5582793     24.26%     65.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              8054863     35.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass             2273      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu             66413118     65.97%     65.97% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult               93141      0.09%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              2      0.00%     66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc          8113      0.01%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead            18432239     18.31%     84.38% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           15727166     15.62%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             100676052                       # Type of FU issued
system.cpu0.iq.rate                          0.792928                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   23016813                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.228623                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads         350180984                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        113410550                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses     98587478                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads              31776                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes             11293                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses         9721                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             123670062                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                  20530                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads          365459                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads      2006136                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses         2602                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation        19208                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      1021760                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads       106419                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked       336961                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               1067469                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                1620814                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles               189225                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          104559654                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             18736791                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            16202841                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts            876235                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 27148                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents               138418                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents         19208                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect        291783                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect       400552                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts              692335                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts             99578675                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts             17975392                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          1032310                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       174715                       # number of nop insts executed
system.cpu0.iew.exec_refs                    33511345                       # number of memory reference insts executed
system.cpu0.iew.exec_branches                16844732                       # Number of branches executed
system.cpu0.iew.exec_stores                  15535953                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.784285                       # Inst execution rate
system.cpu0.iew.wb_sent                      99047596                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                     98597199                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                 51323656                       # num instructions producing a value
system.cpu0.iew.wb_consumers                 84802398                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.776555                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.605215                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts        8524425                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls        1571747                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts           633147                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    123606126                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.768066                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.480848                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0     79269760     64.13%     64.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     24721020     20.00%     84.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2      8248963      6.67%     90.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3      3214548      2.60%     93.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4      3440916      2.78%     96.19% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      1523839      1.23%     97.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      1135185      0.92%     98.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7       534039      0.43%     98.77% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8      1517856      1.23%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    123606126                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts            78906627                       # Number of instructions committed
system.cpu0.commit.committedOps              94937680                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                      31911736                       # Number of memory references committed
system.cpu0.commit.loads                     16730655                       # Number of loads committed
system.cpu0.commit.membars                     647181                       # Number of memory barriers committed
system.cpu0.commit.branches                  16206992                       # Number of branches committed
system.cpu0.commit.fp_insts                      9708                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                 81886422                       # Number of committed integer instructions.
system.cpu0.commit.function_calls             1929931                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu        62927104     66.28%     66.28% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult          90727      0.10%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc         8113      0.01%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       16730655     17.62%     84.01% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      15181081     15.99%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total         94937680                       # Class of committed instruction
system.cpu0.commit.bw_lim_events              1517856                       # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads                   221365586                       # The number of ROB reads
system.cpu0.rob.rob_writes                  208677314                       # The number of ROB writes
system.cpu0.timesIdled                         109557                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                        1607503                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                  5522172985                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                   78784576                       # Number of Instructions Simulated
system.cpu0.committedOps                     94815629                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.611578                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.611578                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.620510                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.620510                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               110621221                       # number of integer regfile reads
system.cpu0.int_regfile_writes               59741549                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                     8143                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                    2264                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                350793071                       # number of cc regfile reads
system.cpu0.cc_regfile_writes                41074475                       # number of cc regfile writes
system.cpu0.misc_regfile_reads              246484638                       # number of misc regfile reads
system.cpu0.misc_regfile_writes               1224545                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements           712867                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          493.083932                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           28844186                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           713379                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            40.433186                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        256881000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.083932                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.963055                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.963055                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          176                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          321                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         63487140                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        63487140                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     15590249                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       15590249                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     12072536                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      12072536                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       311110                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       311110                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       363193                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       363193                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       360660                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       360660                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     27662785                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        27662785                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     27973895                       # number of overall hits
system.cpu0.dcache.overall_hits::total       27973895                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       638253                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       638253                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1832121                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1832121                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       146008                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       146008                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25001                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        25001                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20609                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20609                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2470374                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2470374                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      2616382                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2616382                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   8112547038                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   8112547038                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  24972133492                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  24972133492                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    394969003                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    394969003                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    454279790                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    454279790                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       381000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       381000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  33084680530                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  33084680530                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  33084680530                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  33084680530                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     16228502                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     16228502                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     13904657                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     13904657                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       457118                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       457118                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       388194                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       388194                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381269                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381269                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     30133159                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     30133159                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     30590277                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     30590277                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039329                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.039329                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.131763                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.131763                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.319410                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.319410                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064403                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064403                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.054054                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.054054                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081982                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.081982                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085530                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.085530                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.550578                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.550578                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13630.176987                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 13630.176987                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15798.128195                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15798.128195                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22042.786647                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22042.786647                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13392.579638                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13392.579638                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12645.202623                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12645.202623                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs         1345                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets      3372122                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               71                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         191319                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    18.943662                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    17.625651                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       512814                       # number of writebacks
system.cpu0.dcache.writebacks::total           512814                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       248043                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       248043                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1519569                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1519569                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18426                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18426                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      1767612                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1767612                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      1767612                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1767612                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       390210                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       390210                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312552                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       312552                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       101508                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       101508                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6575                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6575                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20609                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20609                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       702762                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       702762                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       804270                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       804270                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4184101504                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4184101504                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5001279356                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5001279356                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1410085492                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1410085492                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97668747                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97668747                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    412365210                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    412365210                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       359000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       359000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9185380860                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9185380860                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10595466352                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10595466352                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4216928747                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4216928747                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3186876498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3186876498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7403805245                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7403805245                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.024045                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.024045                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.022478                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022478                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.222061                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.222061                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016937                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016937                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.054054                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.054054                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023322                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023322                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026292                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.026292                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10722.691638                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10722.691638                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16001.431301                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16001.431301                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13891.373015                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13891.373015                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.562281                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.562281                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20008.986850                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20008.986850                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13070.400591                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13070.400591                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13174.016626                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13174.016626                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1263628                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.774293                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           36451354                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1264140                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            28.834903                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6311559000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.774293                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999559                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999559                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         76768570                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        76768570                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     36451354                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       36451354                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     36451354                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        36451354                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     36451354                       # number of overall hits
system.cpu0.icache.overall_hits::total       36451354                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1300843                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1300843                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1300843                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1300843                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1300843                       # number of overall misses
system.cpu0.icache.overall_misses::total      1300843                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11016228057                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  11016228057                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11016228057                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  11016228057                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11016228057                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  11016228057                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     37752197                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     37752197                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     37752197                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     37752197                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     37752197                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     37752197                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.034457                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.034457                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.034457                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.034457                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.034457                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.034457                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8468.530066                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8468.530066                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8468.530066                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8468.530066                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8468.530066                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8468.530066                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs       721640                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets           84                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs            96102                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              2                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs     7.509105                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets           42                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        36666                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        36666                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst        36666                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        36666                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst        36666                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        36666                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1264177                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1264177                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1264177                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1264177                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1264177                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1264177                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8917861032                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   8917861032                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8917861032                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   8917861032                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8917861032                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   8917861032                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    244130748                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    244130748                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    244130748                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    244130748                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033486                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033486                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033486                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.033486                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033486                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.033486                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7054.281981                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7054.281981                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7054.281981                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  7054.281981                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7054.281981                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  7054.281981                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     11568415                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       525589                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     10417206                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher       118474                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit        25510                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       481631                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       881553                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements          396536                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16205.751344                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2245612                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          412784                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            5.440162                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle    2809249850500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  4624.087674                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    10.817381                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     1.808377                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   942.420690                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1398.445665                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9228.171558                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.282232                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000660                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000110                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.057521                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.085354                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.563243                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.989121                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8089                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         8146                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           44                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          199                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         3272                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4134                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          440                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          478                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3751                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3581                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          270                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.493713                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000793                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.497192                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        43591487                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       43591487                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        54584                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        12527                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1242350                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       407474                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       1716935                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       512814                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       512814                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        15317                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        15317                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2112                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         2112                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       216670                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       216670                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        54584                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker        12527                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1242350                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       624144                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1933605                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        54584                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker        12527                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1242350                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       624144                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1933605                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          547                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          204                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        21799                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data        90709                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total       113259                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27943                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        27943                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18497                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18497                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        52796                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        52796                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          547                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          204                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        21799                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       143505                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       166055                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          547                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          204                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        21799                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       143505                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       166055                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     14446999                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4916500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst    810567190                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2703489870                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   3533420559                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    501086453                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    501086453                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    362300280                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    362300280                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       348000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       348000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2600330023                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2600330023                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     14446999                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4916500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst    810567190                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5303819893                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   6133750582                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     14446999                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4916500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst    810567190                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5303819893                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   6133750582                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        55131                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        12731                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1264149                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       498183                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      1830194                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       512814                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       512814                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        43260                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        43260                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20609                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        20609                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269466                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269466                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        55131                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        12731                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1264149                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       767649                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      2099660                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        55131                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        12731                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1264149                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       767649                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      2099660                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.009922                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.016024                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.017244                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.182080                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.061884                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.645932                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.645932                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.897521                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.897521                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.195928                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.195928                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.009922                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.016024                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.017244                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.186941                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.079087                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.009922                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.016024                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.017244                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.186941                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.079087                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26411.332724                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24100.490196                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37183.686866                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29803.987146                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31197.702249                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17932.450095                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17932.450095                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19586.975185                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19586.975185                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49252.405921                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49252.405921                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26411.332724                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24100.490196                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37183.686866                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36959.129598                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 36938.066195                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26411.332724                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24100.490196                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37183.686866                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36959.129598                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 36938.066195                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs        63742                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs            1448                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    44.020718                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       211838                       # number of writebacks
system.cpu0.l2cache.writebacks::total          211838                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         5563                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         3181                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total         8745                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         8830                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         8830                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         5563                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        12011                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        17575                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            1                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         5563                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        12011                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        17575                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          547                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          203                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        16236                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        87528                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total       104514                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       481628                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       481628                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27943                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27943                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18497                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18497                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43966                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        43966                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          547                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          203                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        16236                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       131494                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       148480                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          547                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          203                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        16236                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       131494                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       481628                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       630108                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10612999                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3482500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst    588277257                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   2016263953                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2618636709                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21954581331                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21954581331                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    482225838                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    482225838                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    249631743                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    249631743                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       271000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       271000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1320074621                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1320074621                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     10612999                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3482500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst    588277257                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3336338574                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   3938711330                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     10612999                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3482500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst    588277257                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3336338574                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21954581331                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  25893292661                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    218713750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4053750231                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4272463981                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3040098947                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3040098947                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    218713750                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7093849178                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7312562928                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.009922                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.015945                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.175694                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.057105                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.645932                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.645932                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.897521                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.897521                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.163160                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.163160                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.009922                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.015945                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.171294                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.070716                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.009922                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.015945                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.012843                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.171294                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.300100                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36232.893385                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23035.645199                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25055.367788                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45584.105017                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.482661                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.482661                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13495.796237                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13495.796237                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 30024.896989                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 30024.896989                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36232.893385                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25372.553683                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26526.881263                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19402.191956                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17155.172414                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36232.893385                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25372.553683                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45584.105017                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41093.419955                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       2021847                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1920670                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        19105                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        19105                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       512814                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       646384                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        80933                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43154                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       104914                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       291875                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       281146                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2534329                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2360353                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        29069                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       120916                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          5044667                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     80953504                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     86188042                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        50924                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       220524                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         167412994                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1039110                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      3610193                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.254626                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.435651                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5           2690945     74.54%     74.54% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6            919248     25.46%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3610193                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    1889992000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    117303500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1901297082                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1220075844                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy     16351973                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     65816442                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups               33910806                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         11562772                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect           305112                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            18755942                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               14959399                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            79.758185                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               12490105                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect              7221                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10163643                       # DTB read hits
system.cpu1.dtb.read_misses                     18794                       # DTB read misses
system.cpu1.dtb.write_hits                    6541990                       # DTB write hits
system.cpu1.dtb.write_misses                     2867                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2050                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                       58                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   373                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      409                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10182437                       # DTB read accesses
system.cpu1.dtb.write_accesses                6544857                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         16705633                       # DTB hits
system.cpu1.dtb.misses                          21661                       # DTB misses
system.cpu1.dtb.accesses                     16727294                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    43641889                       # ITB inst hits
system.cpu1.itb.inst_misses                      7003                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1205                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                      544                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                43648892                       # ITB inst accesses
system.cpu1.itb.hits                         43641889                       # DTB hits
system.cpu1.itb.misses                           7003                       # DTB misses
system.cpu1.itb.accesses                     43648892                       # DTB accesses
system.cpu1.numCycles                       104622935                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles           9986788                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     109166158                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                   33910806                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          27449504                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                     91794015                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles                3775656                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                     78908                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               31556                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles       200392                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       294710                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles         7499                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 43641278                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes               116202                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                   2270                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         104281696                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.296833                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.339781                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                47334317     45.39%     45.39% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                14034977     13.46%     58.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                 7536210      7.23%     66.08% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                35376192     33.92%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           104281696                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.324124                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       1.043425                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles                13018026                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles             61674095                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                 26725105                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles              1111367                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               1753103                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved              754241                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred               137598                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts              68060945                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              1169140                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               1753103                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles                17450583                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles                2252903                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles      56981552                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                 23380155                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles              2463400                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts              55156301                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts               230486                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents               263427                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                 35391                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                 18241                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents               1436172                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands           55002320                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            260520543                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups        58679791                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups             1657                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps             52223668                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                 2778652                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts           1878098                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts       1805410                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 13101415                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            10456972                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            6914054                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads           629493                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          831483                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                  54264321                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded             589116                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                 53908666                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           111755                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined        2291961                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined      5808692                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved         48780                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    104281696                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.516952                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       0.852554                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0           71029795     68.11%     68.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           16529290     15.85%     83.96% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           13075763     12.54%     96.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3            3359554      3.22%     99.72% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4             287282      0.28%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5                 12      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      104281696                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                2925282     45.12%     45.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                   677      0.01%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                      0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     45.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               1673331     25.81%     70.93% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              1884639     29.07%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               66      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu             36727327     68.13%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult               46544      0.09%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc          3339      0.01%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead            10380092     19.25%     87.48% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite            6751298     12.52%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total              53908666                       # Type of FU issued
system.cpu1.iq.rate                          0.515266                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                    6483929                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.120276                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads         218688932                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes         57153517                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses     51920276                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads               5780                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes              2046                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses         1784                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses              60388837                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                   3692                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads           91402                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads       490292                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses          689                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation        10197                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores       355874                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads        52006                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked        70534                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               1753103                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                 547921                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles               114364                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts           54905583                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             10456972                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts             6914054                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts            301613                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                  9861                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents                97001                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents         10197                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect         54939                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect       127326                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts              182265                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts             53638641                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             10278143                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           248381                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                        52146                       # number of nop insts executed
system.cpu1.iew.exec_refs                    16965109                       # number of memory reference insts executed
system.cpu1.iew.exec_branches                11808008                       # Number of branches executed
system.cpu1.iew.exec_stores                   6686966                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.512685                       # Inst execution rate
system.cpu1.iew.wb_sent                      53497702                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                     51922060                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                 25229975                       # num instructions producing a value
system.cpu1.iew.wb_consumers                 38490431                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.496278                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.655487                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts        3657476                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls         540336                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts           170387                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    102349842                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.498091                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.159102                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0     76769313     75.01%     75.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     14290135     13.96%     88.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2      6080073      5.94%     94.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3       704006      0.69%     95.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4      1980080      1.93%     97.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      1566587      1.53%     99.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6       444714      0.43%     99.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7       123770      0.12%     99.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8       391164      0.38%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    102349842                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts            41393585                       # Number of instructions committed
system.cpu1.commit.committedOps              50979540                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                      16524860                       # Number of memory references committed
system.cpu1.commit.loads                      9966680                       # Number of loads committed
system.cpu1.commit.membars                     209721                       # Number of memory barriers committed
system.cpu1.commit.branches                  11640060                       # Number of branches committed
system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                 45829312                       # Number of committed integer instructions.
system.cpu1.commit.function_calls             3366651                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu        34405704     67.49%     67.49% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult          45637      0.09%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc         3339      0.01%     67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead        9966680     19.55%     87.14% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite       6558180     12.86%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total         50979540                       # Class of committed instruction
system.cpu1.commit.bw_lim_events               391164                       # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads                   136558924                       # The number of ROB reads
system.cpu1.rob.rob_writes                  111202252                       # The number of ROB writes
system.cpu1.timesIdled                          53311                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                         341239                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                  5543976372                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                   41360731                       # Number of Instructions Simulated
system.cpu1.committedOps                     50946686                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              2.529523                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        2.529523                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.395331                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.395331                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads                56284724                       # number of integer regfile reads
system.cpu1.int_regfile_writes               35740870                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                     1381                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                191161936                       # number of cc regfile reads
system.cpu1.cc_regfile_writes                15560884                       # number of cc regfile writes
system.cpu1.misc_regfile_reads              205876605                       # number of misc regfile reads
system.cpu1.misc_regfile_writes                388900                       # number of misc regfile writes
system.cpu1.dcache.tags.replacements           191071                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          472.564441                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           15741519                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           191395                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            82.246239                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     102871508500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.564441                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.922977                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.922977                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          324                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          320                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.632812                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         32983738                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        32983738                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      9574548                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        9574548                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      5910552                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       5910552                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49554                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        49554                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        79147                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        79147                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71001                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71001                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     15485100                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        15485100                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     15534654                       # number of overall hits
system.cpu1.dcache.overall_hits::total       15534654                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       219354                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       219354                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       398461                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       398461                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30111                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30111                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18127                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        18127                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23403                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23403                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       617815                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        617815                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       647926                       # number of overall misses
system.cpu1.dcache.overall_misses::total       647926                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3453063988                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   3453063988                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   8746670918                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   8746670918                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    363087750                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    363087750                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    542334299                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    542334299                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       511000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       511000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  12199734906                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  12199734906                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  12199734906                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  12199734906                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      9793902                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      9793902                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6309013                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6309013                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79665                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        79665                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        97274                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        97274                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94404                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94404                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     16102915                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     16102915                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     16182580                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     16182580                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.022397                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.022397                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.063157                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.063157                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.377970                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.377970                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.186350                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.186350                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.247903                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.247903                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.038367                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.038367                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040038                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.040038                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15741.969547                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15741.969547                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21951.134284                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21951.134284                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.217355                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.217355                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23173.708456                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23173.708456                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19746.582563                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19746.582563                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18828.901612                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 18828.901612                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs          358                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets      1116392                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs               38                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets          39638                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.421053                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    28.164690                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       117580                       # number of writebacks
system.cpu1.dcache.writebacks::total           117580                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        79511                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        79511                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       306644                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total       306644                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13188                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13188                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data       386155                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total       386155                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data       386155                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total       386155                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       139843                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       139843                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91817                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        91817                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        28628                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        28628                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4939                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4939                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23403                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23403                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       231660                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       231660                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       260288                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       260288                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1827288064                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1827288064                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2196971984                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2196971984                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    494563997                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    494563997                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87258999                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87258999                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    494349701                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    494349701                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       489000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       489000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4024260048                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4024260048                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4518824045                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4518824045                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2298813494                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2298813494                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1826635494                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1826635494                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4125448988                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4125448988                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.014279                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.014279                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014553                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014553                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.359355                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.359355                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050774                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.050774                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.247903                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.247903                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014386                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.014386                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.016084                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.016084                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13066.710983                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13066.710983                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23927.725628                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23927.725628                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17275.534337                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17275.534337                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17667.341365                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17667.341365                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21123.347477                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21123.347477                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17371.406579                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17371.406579                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17360.861987                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17360.861987                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           607210                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.525690                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           43016771                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           607722                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            70.783633                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      78589984500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.525690                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975636                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975636                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         87889967                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        87889967                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     43016771                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       43016771                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     43016771                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        43016771                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     43016771                       # number of overall hits
system.cpu1.icache.overall_hits::total       43016771                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       624350                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       624350                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       624350                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        624350                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       624350                       # number of overall misses
system.cpu1.icache.overall_misses::total       624350                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5095278041                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5095278041                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5095278041                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5095278041                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5095278041                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5095278041                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     43641121                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     43641121                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     43641121                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     43641121                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     43641121                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     43641121                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014306                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.014306                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014306                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.014306                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014306                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.014306                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8160.932235                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8160.932235                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8160.932235                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8160.932235                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8160.932235                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8160.932235                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs       275120                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs            36110                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs     7.618942                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        16625                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total        16625                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst        16625                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total        16625                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst        16625                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total        16625                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       607725                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       607725                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       607725                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       607725                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       607725                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       607725                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4103508232                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4103508232                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4103508232                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4103508232                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4103508232                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4103508232                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8190250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8190250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8190250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8190250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013926                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013926                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013926                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.013926                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013926                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.013926                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6752.245229                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6752.245229                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6752.245229                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  6752.245229                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6752.245229                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  6752.245229                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      4841883                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        43038                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      4641023                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher        42756                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         5990                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       109076                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       564189                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements           85682                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15604.887972                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            847212                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs          100795                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            8.405298                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  6001.492372                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     7.158596                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.882758                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   688.413448                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1964.460870                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6940.479928                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.366302                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000437                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000176                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.042017                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.119901                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.423613                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.952447                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9541                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           24                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5548                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          308                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         8077                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1156                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          417                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4190                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          941                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.582336                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001465                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.338623                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        16881821                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       16881821                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        16379                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7476                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       601754                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       101261                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        726870                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       117580                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       117580                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         2286                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         2286                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          847                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          847                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        28888                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        28888                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        16379                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7476                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       601754                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       130149                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         755758                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        16379                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7476                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       601754                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       130149                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        755758                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          463                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          277                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst         5968                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        72129                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        78837                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28394                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28394                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22555                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22555                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32933                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32933                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          463                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          277                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst         5968                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       105062                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       111770                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          463                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          277                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst         5968                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       105062                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       111770                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     10162748                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5804000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    182703951                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1611916890                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1810587589                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    537388904                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    537388904                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    442240538                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    442240538                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       477999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       477999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1281441808                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1281441808                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     10162748                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5804000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    182703951                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2893358698                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3092029397                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     10162748                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5804000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    182703951                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2893358698                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3092029397                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        16842                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7753                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       607722                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       173390                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       805707                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       117580                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       117580                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        30680                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        30680                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23402                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23402                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        61821                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        61821                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        16842                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7753                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       607722                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       235211                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       867528                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        16842                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7753                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       607722                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       235211                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       867528                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.027491                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.035728                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.009820                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.415993                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.097848                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.925489                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.925489                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.963807                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.963807                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.532715                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.532715                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.027491                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.035728                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.009820                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.446671                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.128837                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.027491                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.035728                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.009820                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.446671                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.128837                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21949.779698                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20953.068592                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30613.932808                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22347.694963                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22966.216231                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18926.142988                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18926.142988                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19607.206296                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19607.206296                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       477999                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       477999                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38910.570188                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38910.570188                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21949.779698                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20953.068592                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30613.932808                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27539.535684                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 27664.215773                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21949.779698                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20953.068592                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30613.932808                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27539.535684                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 27664.215773                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs        21207                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs             485                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    43.725773                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        40787                       # number of writebacks
system.cpu1.l2cache.writebacks::total           40787                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           14                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst         1333                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           75                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total         1422                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1248                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         1248                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           14                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst         1333                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1323                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         2670                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           14                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst         1333                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1323                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         2670                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          463                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          263                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst         4635                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        72054                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        77415                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       109072                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       109072                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28394                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28394                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22555                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22555                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31685                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        31685                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          463                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          263                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         4635                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103739                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       109100                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          463                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          263                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         4635                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103739                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       109072                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       218172                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6919250                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3788000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    124690282                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1106071688                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1241469220                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3463800362                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3463800362                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    417384045                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    417384045                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    308383273                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    308383273                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       400999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       400999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    945118400                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    945118400                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6919250                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3788000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    124690282                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2051190088                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2186587620                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6919250                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3788000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    124690282                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2051190088                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   3463800362                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   5650387982                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7340750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2182174505                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2189515255                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1737462500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1737462500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7340750                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3919637005                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3926977755                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027491                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.033922                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.007627                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.415560                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.096083                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.925489                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.925489                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.963807                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.963807                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.512528                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.512528                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027491                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.033922                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.007627                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.441047                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.125760                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027491                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.033922                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.007627                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.441047                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.251487                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26901.894714                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.593832                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.546147                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31757.007866                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14699.726879                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14699.726879                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13672.501574                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13672.501574                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       400999                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       400999                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29828.575036                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29828.575036                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26901.894714                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19772.603245                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20042.049679                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14944.384449                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14403.041825                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26901.894714                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19772.603245                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31757.007866                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25898.777029                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1294463                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       865156                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        11871                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11871                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       117580                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       157134                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        84893                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41888                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        87131                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        79541                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        66364                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1215649                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       825187                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17442                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        37966                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2096244                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     38895824                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25442442                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        31012                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        67368                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          64436646                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     834109                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1797203                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.418253                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.493272                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5           1045518     58.17%     58.17% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6            751685     41.83%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1797203                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     659823435                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     81245999                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    912982594                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    403842731                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      9829718                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     21193613                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31016                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31016                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59439                       # Transaction distribution
system.iobus.trans_dist::WriteResp              23215                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56654                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107968                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72942                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72942                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180910                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71598                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321208                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321208                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40134000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           347117122                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84753000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36830633                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36453                       # number of replacements
system.iocache.tags.tagsinuse               14.560350                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36469                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         254140746000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.560350                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.910022                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.910022                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328239                       # Number of tag accesses
system.iocache.tags.data_accesses              328239                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          247                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              247                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          247                       # number of demand (read+write) misses
system.iocache.demand_misses::total               247                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          247                       # number of overall misses
system.iocache.overall_misses::total              247                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     30846377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     30846377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9649955112                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   9649955112                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     30846377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     30846377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     30846377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     30846377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          247                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            247                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          247                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             247                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          247                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            247                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124884.117409                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124884.117409                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266396.729019                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 266396.729019                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124884.117409                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124884.117409                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124884.117409                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124884.117409                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         57106                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7195                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.936901                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          247                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          247                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          247                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          247                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          247                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          247                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18001377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18001377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7766041378                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7766041378                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     18001377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     18001377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     18001377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     18001377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72880.068826                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72880.068826                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214389.393165                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214389.393165                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72880.068826                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72880.068826                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72880.068826                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72880.068826                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   153362                       # number of replacements
system.l2c.tags.tagsinuse                64452.240621                       # Cycle average of tags in use
system.l2c.tags.total_refs                     520061                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   218026                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.385316                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   14085.588040                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    14.542715                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     2.877015                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1413.412167                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2156.075780                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39299.191861                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.498933                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.000005                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      294.129683                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      883.808465                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  6297.115959                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.214929                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000222                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000044                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.021567                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.032899                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.599658                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000084                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.004488                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.013486                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.096086                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.983463                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        44393                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        20252                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          411                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         7759                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        36223                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           17                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          348                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4616                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        15266                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.677383                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000290                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.309021                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6595512                       # Number of tag accesses
system.l2c.tags.data_accesses                 6595512                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          297                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker          126                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              12544                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              38879                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       182049                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker           77                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           46                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst               4168                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              11674                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        44095                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 293955                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          252625                       # number of Writeback hits
system.l2c.Writeback_hits::total               252625                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           11700                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             714                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               12414                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           188                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           168                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               356                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3696                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1226                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 4922                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           297                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker           126                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               12544                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               42575                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       182049                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            77                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            46                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                4168                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               12900                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher        44095                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  298877                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          297                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker          126                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              12544                       # number of overall hits
system.l2c.overall_hits::cpu0.data              42575                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       182049                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           77                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           46                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               4168                       # number of overall hits
system.l2c.overall_hits::cpu1.data              12900                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher        44095                       # number of overall hits
system.l2c.overall_hits::total                 298877                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker           34                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            6                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             3733                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             8650                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       164264                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker           10                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              479                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1382                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher        21001                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               199560                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          8869                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2860                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11729                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          753                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1212                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1965                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data           7749                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7210                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              14959                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker           34                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            6                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              3733                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             16399                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       164264                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               479                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8592                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher        21001                       # number of demand (read+write) misses
system.l2c.demand_misses::total                214519                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker           34                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            6                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             3733                       # number of overall misses
system.l2c.overall_misses::cpu0.data            16399                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       164264                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker           10                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              479                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8592                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher        21001                       # number of overall misses
system.l2c.overall_misses::total               214519                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2746500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       450000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    351602993                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    773076495                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  19011653853                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       762250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker       318000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     47746000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    122164750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher   2528718655                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    22839239496                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      7000718                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      3239366                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     10240084                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1399947                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1250448                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2650395                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data    713784680                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    563377983                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1277162663                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      2746500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       450000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    351602993                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1486861175                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  19011653853                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       762250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker       318000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     47746000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    685542733                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   2528718655                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     24116402159                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      2746500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       450000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    351602993                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1486861175                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19011653853                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       762250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker       318000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     47746000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    685542733                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   2528718655                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    24116402159                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          331                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker          132                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          16277                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          47529                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       346313                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker           87                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           47                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst           4647                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          13056                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        65096                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             493515                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       252625                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           252625                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        20569                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3574                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           24143                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          941                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1380                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2321                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        11445                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         8436                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            19881                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          331                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker          132                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           16277                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           58974                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       346313                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           87                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           47                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst            4647                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           21492                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        65096                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              513396                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          331                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker          132                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          16277                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          58974                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       346313                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           87                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           47                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst           4647                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          21492                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        65096                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             513396                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.102719                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.045455                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.229342                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.181994                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.474322                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.114943                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.021277                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.103077                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.105852                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.322616                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.404365                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.431183                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.800224                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.485814                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.800213                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.878261                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.846618                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.677064                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.854670                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.752427                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.102719                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.045455                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.229342                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.278072                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.474322                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.114943                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.021277                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.103077                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.399777                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.322616                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.417843                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.102719                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.045455                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.229342                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.278072                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.474322                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.114943                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.021277                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.103077                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.399777                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.322616                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.417843                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80779.411765                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 94187.782748                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 89373.005202                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 115738.408008                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        76225                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker       318000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 99678.496868                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88397.069465                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 120409.440265                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 114447.983043                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   789.346939                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1132.645455                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   873.056868                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1859.159363                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1031.722772                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1348.801527                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92113.134598                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78138.416505                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 85377.542817                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80779.411765                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 94187.782748                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 90667.795292                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 115738.408008                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        76225                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker       318000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 99678.496868                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 79788.493133                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120409.440265                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 112420.821275                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80779.411765                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 94187.782748                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 90667.795292                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 115738.408008                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        76225                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker       318000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 99678.496868                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 79788.493133                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120409.440265                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 112420.821275                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               117                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        6                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     19.500000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              113392                       # number of writebacks
system.l2c.writebacks::total                   113392                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst             2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                24                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 24                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher           18                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                24                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           34                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            6                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         3733                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         8649                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       164261                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          477                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1382                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        20983                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          199536                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8869                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2860                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11729                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          753                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1212                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1965                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data         7749                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7210                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         14959                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker           34                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         3733                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        16398                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       164261                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          477                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8592                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        20983                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           214495                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker           34                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         3733                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        16398                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       164261                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker           10                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          477                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8592                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        20983                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          214495                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2325500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       375000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    305475493                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    665719995                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16992433103                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       638750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker       305500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     41657500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    104989750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   2271307905                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  20385228496                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     90096780                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     28958843                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    119055623                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7837704                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     12202201                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     20039905                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    617896318                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    472413013                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1090309331                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2325500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       375000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    305475493                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1283616313                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  16992433103                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       638750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       305500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     41657500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    577402763                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   2271307905                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  21475537827                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2325500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       375000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    305475493                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1283616313                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16992433103                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       638750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       305500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     41657500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    577402763                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2271307905                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  21475537827                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    159081750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3686294748                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5350750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1919867500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   5770594748                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2713847001                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1535209500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4249056501                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    159081750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6400141749                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5350750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3455077000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10019651249                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.102719                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.045455                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.229342                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.181973                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474314                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.114943                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.021277                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.102647                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.105852                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.322339                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.404316                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.431183                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.800224                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.485814                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.800213                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.878261                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.846618                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.677064                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.854670                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.752427                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.102719                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.045455                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.229342                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.278055                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474314                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.114943                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.021277                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.102647                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.399777                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.322339                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.417796                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.102719                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.045455                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.229342                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.278055                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.474314                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.114943                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.021277                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.102647                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.399777                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.322339                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.417796                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81831.099116                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76970.747485                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        63875                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker       305500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 87332.285115                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75969.428365                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 102163.161014                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.617657                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10125.469580                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10150.534828                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10408.637450                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10067.822607                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10198.424936                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79738.846045                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65521.915811                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 72886.511866                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81831.099116                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78278.833577                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        63875                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       305500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 87332.285115                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67202.369995                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 100121.391300                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68397.058824                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81831.099116                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78278.833577                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103447.763638                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        63875                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       305500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 87332.285115                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67202.369995                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108245.146309                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 100121.391300                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              237783                       # Transaction distribution
system.membus.trans_dist::ReadResp             237783                       # Transaction distribution
system.membus.trans_dist::WriteReq              30976                       # Transaction distribution
system.membus.trans_dist::WriteResp             30976                       # Transaction distribution
system.membus.trans_dist::Writeback            149598                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            79558                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40675                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           13780                       # Transaction distribution
system.membus.trans_dist::ReadExReq             31194                       # Transaction distribution
system.membus.trans_dist::ReadExResp            14873                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107968                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13732                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       708374                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       830114                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 939030                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27464                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     21024476                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     21215108                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4636480                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4636480                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                25851588                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123388                       # Total snoops (count)
system.membus.snoop_fanout::samples            537032                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  537032    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              537032                       # Request fanout histogram
system.membus.reqLayer0.occupancy            81237991                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               26500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11614997                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1967612498                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2113693587                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38580367                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             659684                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            659669                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30976                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30976                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           252625                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           91886                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41031                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         132917                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           22                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           22                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            40129                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           40129                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1298615                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       426559                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1725174                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     40738026                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8562330                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               49300356                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          291348                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1083611                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.033657                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.180345                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                1047140     96.63%     96.63% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36471      3.37%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1083611                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1586551162                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1044000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2272414912                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         846278221                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1853                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2766                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------