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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
sim_seconds 2.605649 # Number of seconds simulated
sim_ticks 2605649343000 # Number of ticks simulated
final_tick 2605649343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
host_inst_rate 57764 # Simulator instruction rate (inst/s)
host_op_rate 74374 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2397402056 # Simulator tick rate (ticks/s)
host_mem_usage 474764 # Number of bytes of host memory used
host_seconds 1086.86 # Real time elapsed on the host
sim_insts 62781325 # Number of instructions simulated
sim_ops 80834116 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bytes_read::cpu0.inst 383680 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5448188 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 438080 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4125688 # Number of bytes read from this memory
system.physmem.bytes_read::total 131508276 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 383680 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 438080 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4229952 # Number of bytes written to this memory
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bytes_written::total 7259088 # Number of bytes written to this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.num_reads::cpu0.inst 5995 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 85202 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6845 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 64492 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15301383 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66093 # Number of write requests responded to by this memory
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.num_writes::total 823377 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 46479979 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 393 # Total read bandwidth from this memory (bytes/s)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bw_read::cpu0.inst 147249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 2090914 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 368 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 168127 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1583363 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50470443 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 147249 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 168127 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 315376 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1623377 # Write bandwidth from this memory (bytes/s)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bw_write::cpu1.data 1156002 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2785904 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1623377 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 46479979 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bw_total::cpu0.inst 147249 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2097438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 368 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 168127 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2739365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53256346 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15301383 # Number of read requests accepted
system.physmem.writeReqs 823377 # Number of write requests accepted
system.physmem.readBursts 15301383 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 823377 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 973889408 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 5399104 # Total number of bytes read from write queue
system.physmem.bytesWritten 7284800 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 131508276 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7259088 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 84361 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 709522 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 14082 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 956098 # Per bank write bursts
system.physmem.perBankRdBursts::1 950020 # Per bank write bursts
system.physmem.perBankRdBursts::2 950090 # Per bank write bursts
system.physmem.perBankRdBursts::3 949980 # Per bank write bursts
system.physmem.perBankRdBursts::4 956223 # Per bank write bursts
system.physmem.perBankRdBursts::5 949119 # Per bank write bursts
system.physmem.perBankRdBursts::6 948884 # Per bank write bursts
system.physmem.perBankRdBursts::7 948711 # Per bank write bursts
system.physmem.perBankRdBursts::8 956337 # Per bank write bursts
system.physmem.perBankRdBursts::9 950158 # Per bank write bursts
system.physmem.perBankRdBursts::10 948908 # Per bank write bursts
system.physmem.perBankRdBursts::11 948900 # Per bank write bursts
system.physmem.perBankRdBursts::12 955944 # Per bank write bursts
system.physmem.perBankRdBursts::13 949314 # Per bank write bursts
system.physmem.perBankRdBursts::14 949393 # Per bank write bursts
system.physmem.perBankRdBursts::15 948943 # Per bank write bursts
system.physmem.perBankWrBursts::0 7119 # Per bank write bursts
system.physmem.perBankWrBursts::1 7037 # Per bank write bursts
system.physmem.perBankWrBursts::2 7071 # Per bank write bursts
system.physmem.perBankWrBursts::3 7168 # Per bank write bursts
system.physmem.perBankWrBursts::4 7696 # Per bank write bursts
system.physmem.perBankWrBursts::5 7220 # Per bank write bursts
system.physmem.perBankWrBursts::6 7070 # Per bank write bursts
system.physmem.perBankWrBursts::7 6913 # Per bank write bursts
system.physmem.perBankWrBursts::8 7415 # Per bank write bursts
system.physmem.perBankWrBursts::9 7415 # Per bank write bursts
system.physmem.perBankWrBursts::10 6887 # Per bank write bursts
system.physmem.perBankWrBursts::11 6788 # Per bank write bursts
system.physmem.perBankWrBursts::12 7071 # Per bank write bursts
system.physmem.perBankWrBursts::13 6872 # Per bank write bursts
system.physmem.perBankWrBursts::14 7197 # Per bank write bursts
system.physmem.perBankWrBursts::15 6886 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.totGap 2605648115500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.readPktSize::2 109 # Read request sizes (log2)
system.physmem.readPktSize::3 15138816 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.readPktSize::6 162458 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.writePktSize::2 757284 # Write request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.writePktSize::6 66093 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1062706 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 998935 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 950903 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 959607 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 945820 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 946342 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2754714 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2746120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3637640 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 38272 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 34182 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 34523 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 32360 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 30630 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 22253 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 21644 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 254 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1998 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 2401 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4700 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5971 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6079 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 6821 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 6509 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6071 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 2256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 774 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 680 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 711 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 674 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 604 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 634 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 601 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 590 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 593 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 556 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 578 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 550 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 543 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 541 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 540 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 543 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 541 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 547 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 965097 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 1010.691593 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 992.992769 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 104.599429 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 5712 0.59% 0.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 4413 0.46% 1.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 2116 0.22% 1.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1499 0.16% 1.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1121 0.12% 1.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 815 0.08% 1.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 661 0.07% 1.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 851 0.09% 1.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 947909 98.22% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 965097 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5955 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 2555.332662 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 92927.024688 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-262143 5949 99.90% 99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 2 0.03% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5955 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5955 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.114190 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.218740 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.431880 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3971 66.68% 66.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 19 0.32% 67.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 175 2.94% 69.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 1141 19.16% 89.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 44 0.74% 89.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 19 0.32% 90.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 21 0.35% 90.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 10 0.17% 90.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 6 0.10% 90.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 3 0.05% 90.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 4 0.07% 90.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 1 0.02% 90.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 1 0.02% 90.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34 1 0.02% 90.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39 1 0.02% 90.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40 1 0.02% 90.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41 146 2.45% 93.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42 311 5.22% 98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43 13 0.22% 98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44 13 0.22% 99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45 16 0.27% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46 22 0.37% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47 9 0.15% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48 4 0.07% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::49 3 0.05% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5955 # Writes before turning the bus around for reads
system.physmem.totQLat 579051796250 # Total ticks spent queuing
system.physmem.totMemAccLat 683715373750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 76085110000 # Total ticks spent in databus transfers
system.physmem.totBankLat 28578467500 # Total ticks spent accessing banks
system.physmem.avgQLat 38052.90 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 1878.06 # Average bank access latency per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgMemAccLat 44930.96 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 373.76 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.47 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.busUtil 2.94 # Data bus utilization in percentage
system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgRdQLen 6.53 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.75 # Average write queue length when enqueuing
system.physmem.readRowHits 14231578 # Number of row buffer hits during reads
system.physmem.writeRowHits 96073 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 84.38 # Row buffer hit rate for writes
system.physmem.avgGap 161592.99 # Average gap between requests
system.physmem.pageHitRate 93.46 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 4.22 # Percentage of time for which DRAM has all the banks in precharge state
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.throughput 54186995 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16352581 # Transaction distribution
system.membus.trans_dist::ReadResp 16352581 # Transaction distribution
system.membus.trans_dist::WriteReq 769189 # Transaction distribution
system.membus.trans_dist::WriteResp 769189 # Transaction distribution
system.membus.trans_dist::Writeback 66093 # Transaction distribution
system.membus.trans_dist::UpgradeReq 35785 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 18271 # Transaction distribution
system.membus.trans_dist::UpgradeResp 14082 # Transaction distribution
system.membus.trans_dist::ReadExReq 137406 # Transaction distribution
system.membus.trans_dist::ReadExResp 137045 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384396 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13840 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1974294 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4374590 # Packet count per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.pkt_count::total 34652222 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392725 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27680 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17656836 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 20081781 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.tot_pkt_size::total 141192309 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 141192309 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.reqLayer0.occupancy 1488242000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.reqLayer2.occupancy 11807000 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.reqLayer6.occupancy 17652470999 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.respLayer1.occupancy 4843604815 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.respLayer2.occupancy 37703679634 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.tags.replacements 72164 # number of replacements
system.l2c.tags.tagsinuse 53016.131060 # Cycle average of tags in use
system.l2c.tags.total_refs 1876966 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 137304 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 13.670148 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.tags.occ_blocks::writebacks 37702.356015 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 7.377107 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000365 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4186.473555 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2957.675740 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.683393 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 4035.806716 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 4115.758170 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.575292 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000113 # Average percentage of cache occupancy
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.063881 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.045131 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.061582 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.062801 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.808962 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65136 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 8263 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53454 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.993896 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 18860644 # Number of tag accesses
system.l2c.tags.data_accesses 18860644 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 23595 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 5577 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 409210 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 169724 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 33221 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 5824 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 593571 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 196649 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1437371 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 582434 # number of Writeback hits
system.l2c.Writeback_hits::total 582434 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 737 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1202 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1939 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 203 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 149 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 352 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 52746 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 54725 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 107471 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 23595 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 5577 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 409210 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 222470 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 33221 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 5824 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 593571 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 251374 # number of demand (read+write) hits
system.l2c.demand_hits::total 1544842 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 23595 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 5577 # number of overall hits
system.l2c.overall_hits::cpu0.inst 409210 # number of overall hits
system.l2c.overall_hits::cpu0.data 222470 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 33221 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 5824 # number of overall hits
system.l2c.overall_hits::cpu1.inst 593571 # number of overall hits
system.l2c.overall_hits::cpu1.data 251374 # number of overall hits
system.l2c.overall_hits::total 1544842 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 16 # number of ReadReq misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.ReadReq_misses::cpu0.inst 5877 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6190 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 6810 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 6416 # number of ReadReq misses
system.l2c.ReadReq_misses::total 25326 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 5271 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4770 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 10041 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 769 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 576 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1345 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 80429 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 59312 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 139741 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 16 # number of demand (read+write) misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.demand_misses::cpu0.inst 5877 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 86619 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 6810 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 65728 # number of demand (read+write) misses
system.l2c.demand_misses::total 165067 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 16 # number of overall misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.overall_misses::cpu0.inst 5877 # number of overall misses
system.l2c.overall_misses::cpu0.data 86619 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses
system.l2c.overall_misses::cpu1.inst 6810 # number of overall misses
system.l2c.overall_misses::cpu1.data 65728 # number of overall misses
system.l2c.overall_misses::total 165067 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1263000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 158000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 424519750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 461015999 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1424250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 503203750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 495567749 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1887152498 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 8440130 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 13402927 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 21843057 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 510978 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2957372 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 3468350 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 5751042289 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4687313508 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10438355797 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 1263000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 158000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 424519750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 6212058288 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 1424250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 503203750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 5182881257 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 12325508295 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 1263000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 158000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 424519750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 6212058288 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 1424250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 503203750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 5182881257 # number of overall miss cycles
system.l2c.overall_miss_latency::total 12325508295 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 23611 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 5579 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 415087 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 175914 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 33236 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 5824 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 600381 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 203065 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1462697 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 582434 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 582434 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 6008 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5972 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 11980 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 972 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 725 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1697 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 133175 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 114037 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247212 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 23611 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 5579 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 415087 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 309089 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 33236 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 5824 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 600381 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 317102 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1709909 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 23611 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 5579 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 415087 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 309089 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 33236 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 5824 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 600381 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 317102 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1709909 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000678 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000358 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014158 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.035188 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.011343 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.031596 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.017315 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.877330 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.798727 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.838147 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.791152 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.794483 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.792575 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.603935 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.520112 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.565268 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000678 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000358 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014158 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.280240 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.011343 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.207277 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.096536 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000678 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000358 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014158 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.280240 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.011343 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.207277 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.096536 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78937.500000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72234.090522 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74477.544265 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 94950 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73891.886931 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77239.362375 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 74514.431730 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1601.238854 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2809.837945 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 2175.386615 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 664.470741 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5134.326389 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 2578.698885 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71504.585274 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79028.080456 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 74697.875334 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78937.500000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 72234.090522 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 71717.040003 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94950 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73891.886931 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 78853.475794 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 74669.729837 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78937.500000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 72234.090522 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 71717.040003 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94950 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73891.886931 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 78853.475794 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 74669.729837 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.writebacks::writebacks 66093 # number of writebacks
system.l2c.writebacks::total 66093 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 40 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 26 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 26 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 26 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 16 # number of ReadReq MSHR misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 5872 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 6150 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 6802 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 6390 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 25247 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 5271 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4770 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 10041 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 769 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 576 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1345 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 80429 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 59312 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 139741 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 16 # number of demand (read+write) MSHR misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.demand_mshr_misses::cpu0.inst 5872 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 86579 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 6802 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 65702 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 164988 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 16 # number of overall MSHR misses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.overall_mshr_misses::cpu0.inst 5872 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 86579 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 6802 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 65702 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 164988 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1063000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 133500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 350406250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 380974999 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1239250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 417280250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 414218499 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1565315748 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 52852722 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 48053192 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 100905914 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7702266 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5777069 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 13479335 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4750287699 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3948467988 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8698755687 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1063000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 133500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 350406250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 5131262698 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1239250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 417280250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 4362686487 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 10264071435 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1063000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 133500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 350406250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 5131262698 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1239250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 417280250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 4362686487 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 10264071435 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6908499 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 110354445727 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2586249 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 56865414992 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167229355467 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1097294498 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16505203944 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 17602498442 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6908499 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 111451740225 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2586249 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 73370618936 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184831853909 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000678 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000358 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014146 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.034960 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.031468 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.877330 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.798727 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.838147 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.791152 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.794483 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.792575 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.603935 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.520112 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.565268 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000678 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000358 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014146 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.280110 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.207195 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.096489 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000678 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000358 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014146 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.280110 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.207195 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.096489 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61947.154309 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64822.926291 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 62000.069236 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.076836 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10074.044444 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.388905 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.950585 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.633681 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10021.810409 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.876923 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66571.148975 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 62249.130084 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59266.827961 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66401.121534 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 62211.017983 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59674.088896 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59266.827961 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61346.699500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66401.121534 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 62211.017983 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.throughput 58721934 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2742702 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2742701 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 769189 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 769189 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 582434 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 35028 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 18623 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 53651 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 259025 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 259025 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831060 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2542800 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15169 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56113 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1201524 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 3348368 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 16175 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 77084 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 8088293 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26573504 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 39205457 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 22316 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94444 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38427456 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 43600612 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132944 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 148080029 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 148080029 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 4928740 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4918843977 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.respLayer0.occupancy 1872939397 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.respLayer1.occupancy 2324821689 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.respLayer2.occupancy 9616940 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.respLayer3.occupancy 32646700 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.respLayer6.occupancy 2706859206 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.respLayer7.occupancy 2444231662 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.respLayer8.occupancy 10370957 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.respLayer9.occupancy 44131664 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.throughput 47398263 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16322928 # Transaction distribution
system.iobus.trans_dist::ReadResp 16322928 # Transaction distribution
system.iobus.trans_dist::WriteReq 8086 # Transaction distribution
system.iobus.trans_dist::WriteResp 8086 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30960 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8852 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.pkt_count_system.bridge.master::total 2384396 # Packet count per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.pkt_count::total 32662028 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40729 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17704 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.tot_pkt_size_system.bridge.master::total 2392725 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.tot_pkt_size::total 123503253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 123503253 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21724000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.reqLayer1.occupancy 4432000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.respLayer0.occupancy 2376310000 # Layer occupancy (ticks)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.respLayer1.occupancy 37739478366 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
system.cpu0.branchPred.lookups 6715650 # Number of BP lookups
system.cpu0.branchPred.condPredicted 5214611 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 297509 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 4164563 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 3259277 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.branchPred.BTBHitPct 78.262161 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 722080 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 28659 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dtb.read_hits 30314049 # DTB read hits
system.cpu0.dtb.read_misses 28675 # DTB read misses
system.cpu0.dtb.write_hits 5612279 # DTB write hits
system.cpu0.dtb.write_misses 4120 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dtb.flush_entries 1934 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1024 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 30342724 # DTB read accesses
system.cpu0.dtb.write_accesses 5616399 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dtb.hits 35926328 # DTB hits
system.cpu0.dtb.misses 32795 # DTB misses
system.cpu0.dtb.accesses 35959123 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.itb.inst_hits 4601822 # ITB inst hits
system.cpu0.itb.inst_misses 5333 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.itb.flush_entries 1359 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.itb.perms_faults 1531 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.itb.inst_accesses 4607155 # ITB inst accesses
system.cpu0.itb.hits 4601822 # DTB hits
system.cpu0.itb.misses 5333 # DTB misses
system.cpu0.itb.accesses 4607155 # DTB accesses
system.cpu0.numCycles 298758505 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.fetch.icacheStallCycles 12556555 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 35349888 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6715650 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 3981357 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 8343175 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1485021 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 73668 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 62934939 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 43768 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 1358657 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 326 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 4600051 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 159705 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 86381436 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.526874 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.794731 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.fetch.rateDist::0 78045507 90.35% 90.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 675063 0.78% 91.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 847046 0.98% 92.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 783211 0.91% 93.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 1013921 1.17% 94.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 572462 0.66% 94.86% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 659407 0.76% 95.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 359642 0.42% 96.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 3425177 3.97% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.fetch.rateDist::total 86381436 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.022479 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.118323 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 13622847 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 63604727 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 7412124 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 742617 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 999121 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 974392 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 66422 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 44125799 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 218867 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 999121 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 14363042 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 26099881 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 33731509 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 7356267 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3831616 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 43013829 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 321 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 629927 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 2476084 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 94 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 43352703 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 198103413 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 178854732 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 5396 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 34867311 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 8485392 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 643580 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 598183 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 7434614 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 8769305 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6206849 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1218439 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1296110 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 40716219 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1133567 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 61584494 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 78672 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 6465857 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 13399979 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 300001 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 86381436 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.712937 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.420531 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iq.issued_per_cycle::0 63313818 73.30% 73.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 8088215 9.36% 82.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3310781 3.83% 86.49% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2721682 3.15% 89.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 7122842 8.25% 97.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1038791 1.20% 99.09% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 532976 0.62% 99.71% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 192156 0.22% 99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 60175 0.07% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iq.issued_per_cycle::total 86381436 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iq.fu_full::IntAlu 26298 0.46% 0.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 452 0.01% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.47% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5416194 95.59% 96.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 223026 3.94% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iq.FU_type_0::No_OpClass 15923 0.03% 0.03% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 24790294 40.25% 40.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 50109 0.08% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 806 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 40.36% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 30788025 49.99% 90.36% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5939307 9.64% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iq.FU_type_0::total 61584494 # Type of FU issued
system.cpu0.iq.rate 0.206135 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 5665970 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.092003 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 215315704 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 48322789 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 38367249 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 11842 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 6226 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 5089 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 67228191 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 6350 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 325894 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 1367932 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2587 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 13911 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 563678 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 22510150 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 5899 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iew.iewSquashCycles 999121 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 20412775 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 272757 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 41952562 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 83343 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 8769305 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6206849 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 796686 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 50755 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 3694 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 13911 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 151015 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 116203 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 267218 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 61206576 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 30649831 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 377918 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iew.exec_nop 102776 # number of nop insts executed
system.cpu0.iew.exec_refs 36543183 # number of memory reference insts executed
system.cpu0.iew.exec_branches 5550332 # Number of branches executed
system.cpu0.iew.exec_stores 5893352 # Number of stores executed
system.cpu0.iew.exec_rate 0.204870 # Inst execution rate
system.cpu0.iew.wb_sent 61019070 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 38372338 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 20674113 # num instructions producing a value
system.cpu0.iew.wb_consumers 38142518 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.iew.wb_rate 0.128439 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.542023 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.commit.commitSquashedInsts 6195680 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 833566 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 232261 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 85382315 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.412432 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.299663 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.commit.committed_per_cycle::0 71262923 83.46% 83.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 7740236 9.07% 92.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2004904 2.35% 94.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1114217 1.30% 96.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 806577 0.94% 97.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 503262 0.59% 97.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 497454 0.58% 98.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 227564 0.27% 98.57% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1225178 1.43% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.commit.committed_per_cycle::total 85382315 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 26835114 # Number of instructions committed
system.cpu0.commit.committedOps 35214409 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.commit.refs 13044544 # Number of memory references committed
system.cpu0.commit.loads 7401373 # Number of loads committed
system.cpu0.commit.membars 236456 # Number of memory barriers committed
system.cpu0.commit.branches 4918099 # Number of branches committed
system.cpu0.commit.fp_insts 5062 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 31243705 # Number of committed integer instructions.
system.cpu0.commit.function_calls 531450 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1225178 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.rob.rob_reads 124649951 # The number of ROB reads
system.cpu0.rob.rob_writes 83821170 # The number of ROB writes
system.cpu0.timesIdled 1018994 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 212377069 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 4911896145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 26765511 # Number of Instructions Simulated
system.cpu0.committedOps 35144806 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 26765511 # Number of Instructions Simulated
system.cpu0.cpi 11.162070 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 11.162070 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.089589 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.089589 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 273626518 # number of integer regfile reads
system.cpu0.int_regfile_writes 37917674 # number of integer regfile writes
system.cpu0.fp_regfile_reads 4695 # number of floating regfile reads
system.cpu0.fp_regfile_writes 986 # number of floating regfile writes
system.cpu0.misc_regfile_reads 148789996 # number of misc regfile reads
system.cpu0.misc_regfile_writes 678362 # number of misc regfile writes
system.cpu0.icache.tags.replacements 415188 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.568306 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 4152259 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 415700 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 9.988595 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 7103550250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.568306 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999157 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999157 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.icache.tags.tag_accesses 5015647 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 5015647 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 4152259 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 4152259 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 4152259 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 4152259 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 4152259 # number of overall hits
system.cpu0.icache.overall_hits::total 4152259 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 447663 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 447663 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 447663 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 447663 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 447663 # number of overall misses
system.cpu0.icache.overall_misses::total 447663 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6158685000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6158685000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6158685000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6158685000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6158685000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6158685000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 4599922 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 4599922 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 4599922 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 4599922 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 4599922 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 4599922 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097320 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.097320 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097320 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.097320 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097320 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.097320 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13757.413501 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13757.413501 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13757.413501 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13757.413501 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4464 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.730539 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31938 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 31938 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 31938 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 31938 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 31938 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 31938 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 415725 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 415725 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 415725 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 415725 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 415725 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 415725 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5022987594 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5022987594 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5022987594 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5022987594 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5022987594 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5022987594 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9487250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9487250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9487250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 9487250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090377 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.090377 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.090377 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12082.476623 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12082.476623 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12082.476623 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dcache.tags.replacements 298882 # number of replacements
system.cpu0.dcache.tags.tagsinuse 483.456705 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 10027143 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 299266 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 33.505787 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 44230250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.456705 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944251 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.944251 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 48541082 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 48541082 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6144970 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6144970 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3563655 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3563655 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 144672 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 144672 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142233 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 142233 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 9708625 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 9708625 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 9708625 # number of overall hits
system.cpu0.dcache.overall_hits::total 9708625 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 393929 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 393929 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1644577 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1644577 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9244 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9244 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7866 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7866 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2038506 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2038506 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2038506 # number of overall misses
system.cpu0.dcache.overall_misses::total 2038506 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5542234631 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5542234631 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82471404032 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 82471404032 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94602484 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 94602484 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50293768 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 50293768 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 88013638663 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 88013638663 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 88013638663 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 88013638663 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6538899 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6538899 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5208232 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5208232 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153916 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 153916 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150099 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 150099 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 11747131 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 11747131 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 11747131 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 11747131 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.060244 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.060244 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.315765 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.315765 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060059 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060059 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052405 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052405 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173532 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.173532 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.173532 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.173532 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.120656 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.120656 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50147.487185 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 50147.487185 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10233.933795 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10233.933795 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6393.817442 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6393.817442 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 43175.560270 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 43175.560270 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 10878 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 5936 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 678 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.044248 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 51.172414 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dcache.writebacks::writebacks 278268 # number of writebacks
system.cpu0.dcache.writebacks::total 278268 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201648 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 201648 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493557 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1493557 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 632 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 632 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1695205 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1695205 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1695205 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1695205 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 192281 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 192281 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 151020 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 151020 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8612 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8612 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7866 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7866 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 343301 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 343301 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 343301 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 343301 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2438332267 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2438332267 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6681240000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6681240000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70543016 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70543016 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34562232 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34562232 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9119572267 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9119572267 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9119572267 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 9119572267 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 120538982283 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 120538982283 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1232045382 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1232045382 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 121771027665 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 121771027665 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029406 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029406 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028996 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028996 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055953 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055953 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052405 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052405 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029224 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029224 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12681.087923 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12681.087923 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44240.762813 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44240.762813 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8191.246633 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.246633 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4393.876430 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4393.876430 # average StoreCondReq mshr miss latency
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.branchPred.lookups 8689698 # Number of BP lookups
system.cpu1.branchPred.condPredicted 7082612 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 415349 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 5570453 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 4730059 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.branchPred.BTBHitPct 84.913363 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 759549 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 43595 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.dtb.read_hits 21626734 # DTB read hits
system.cpu1.dtb.read_misses 38691 # DTB read misses
system.cpu1.dtb.write_hits 6575784 # DTB write hits
system.cpu1.dtb.write_misses 12298 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.dtb.flush_entries 1712 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 3023 # Number of TLB faults due to alignment restrictions
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.dtb.perms_faults 600 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 21665425 # DTB read accesses
system.cpu1.dtb.write_accesses 6588082 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.dtb.hits 28202518 # DTB hits
system.cpu1.dtb.misses 50989 # DTB misses
system.cpu1.dtb.accesses 28253507 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.itb.inst_hits 7394895 # ITB inst hits
system.cpu1.itb.inst_misses 5860 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.itb.flush_entries 1207 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.itb.perms_faults 1503 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.itb.inst_accesses 7400755 # ITB inst accesses
system.cpu1.itb.hits 7394895 # DTB hits
system.cpu1.itb.misses 5860 # DTB misses
system.cpu1.itb.accesses 7400755 # DTB accesses
system.cpu1.numCycles 185247782 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.fetch.icacheStallCycles 18767441 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 58413381 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 8689698 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 5489608 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 12630025 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3326163 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 70879 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 38401480 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5864 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 46813 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 1518730 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 7393189 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 549179 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3073 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 73717325 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.969397 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.351920 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.fetch.rateDist::0 61095045 82.88% 82.88% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 712004 0.97% 83.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 939814 1.27% 85.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 1614257 2.19% 87.31% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1180828 1.60% 88.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 579149 0.79% 89.70% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1971485 2.67% 92.37% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 418985 0.57% 92.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 5205758 7.06% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.fetch.rateDist::total 73717325 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.046909 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.315326 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 19856835 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 39689565 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 11370888 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 621997 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 2178040 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1113164 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 99384 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 67504859 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 329486 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 2178040 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 20884497 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 13732674 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 23091492 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 10921071 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 2909551 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 63553177 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 150 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 495727 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 1775459 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 454 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 67243012 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 295535307 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 271726361 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 4962 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 47019288 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 20223723 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 581683 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 523637 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 6484055 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 11835207 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 7683859 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 982260 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1485488 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 58475771 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 951228 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 65019700 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 99369 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 13400197 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 36106127 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 236520 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 73717325 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.882014 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.585621 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iq.issued_per_cycle::0 50542925 68.56% 68.56% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 7121407 9.66% 78.22% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 4031042 5.47% 83.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3362905 4.56% 88.25% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 5367239 7.28% 95.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1894348 2.57% 98.10% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 1048738 1.42% 99.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 275398 0.37% 99.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 73323 0.10% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iq.issued_per_cycle::total 73717325 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iq.fu_full::IntAlu 33869 1.02% 1.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 996 0.03% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 2994112 90.44% 91.49% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 281623 8.51% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 12895 0.02% 0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 35505233 54.61% 54.63% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 59031 0.09% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 1556 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.72% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 22501549 34.61% 89.33% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6939400 10.67% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iq.FU_type_0::total 65019700 # Type of FU issued
system.cpu1.iq.rate 0.350988 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 3310600 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.050917 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 207206368 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 72837982 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 50730101 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 11167 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 5978 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5058 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 68311542 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 5863 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 343642 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 2877094 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3994 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 17361 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1094953 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 11606945 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 675630 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iew.iewSquashCycles 2178040 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 10295917 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 191116 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 59545170 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 114100 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 11835207 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 7683859 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 664311 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 56460 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 4454 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 17361 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 204103 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 160517 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 364620 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 63283569 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 21990431 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1736131 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iew.exec_nop 118171 # number of nop insts executed
system.cpu1.iew.exec_refs 28863200 # number of memory reference insts executed
system.cpu1.iew.exec_branches 6787528 # Number of branches executed
system.cpu1.iew.exec_stores 6872769 # Number of stores executed
system.cpu1.iew.exec_rate 0.341616 # Inst execution rate
system.cpu1.iew.wb_sent 62514610 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 50735159 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 28199774 # num instructions producing a value
system.cpu1.iew.wb_consumers 51433237 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.iew.wb_rate 0.273877 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.548279 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.commit.commitSquashedInsts 13377367 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 714708 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 317605 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 71539285 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.639790 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.672504 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.commit.committed_per_cycle::0 55665383 77.81% 77.81% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 7811223 10.92% 88.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 2101815 2.94% 91.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1189986 1.66% 93.33% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 946066 1.32% 94.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 613597 0.86% 95.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 912617 1.28% 96.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 531458 0.74% 97.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1767140 2.47% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.commit.committed_per_cycle::total 71539285 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 36096592 # Number of instructions committed
system.cpu1.commit.committedOps 45770088 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.commit.refs 15547019 # Number of memory references committed
system.cpu1.commit.loads 8958113 # Number of loads committed
system.cpu1.commit.membars 191016 # Number of memory barriers committed
system.cpu1.commit.branches 5856523 # Number of branches committed
system.cpu1.commit.fp_insts 5022 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 40800338 # Number of committed integer instructions.
system.cpu1.commit.function_calls 520894 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1767140 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.rob.rob_reads 127901171 # The number of ROB reads
system.cpu1.rob.rob_writes 120555711 # The number of ROB writes
system.cpu1.timesIdled 777241 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 111530457 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5026003021 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 36015814 # Number of Instructions Simulated
system.cpu1.committedOps 45689310 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 36015814 # Number of Instructions Simulated
system.cpu1.cpi 5.143512 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 5.143512 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.194420 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.194420 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 292255401 # number of integer regfile reads
system.cpu1.int_regfile_writes 53047565 # number of integer regfile writes
system.cpu1.fp_regfile_reads 3797 # number of floating regfile reads
system.cpu1.fp_regfile_writes 1766 # number of floating regfile writes
system.cpu1.misc_regfile_reads 133121160 # number of misc regfile reads
system.cpu1.misc_regfile_writes 545345 # number of misc regfile writes
system.cpu1.icache.tags.replacements 600500 # number of replacements
system.cpu1.icache.tags.tagsinuse 498.750005 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 6745926 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 601012 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 11.224278 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 74974413000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.750005 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974121 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.974121 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.icache.tags.tag_accesses 7994182 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 7994182 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 6745926 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 6745926 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 6745926 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 6745926 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 6745926 # number of overall hits
system.cpu1.icache.overall_hits::total 6745926 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 647211 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 647211 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 647211 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 647211 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 647211 # number of overall misses
system.cpu1.icache.overall_misses::total 647211 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8801556837 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 8801556837 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 8801556837 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 8801556837 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 8801556837 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 8801556837 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 7393137 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 7393137 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 7393137 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 7393137 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 7393137 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 7393137 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.087542 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.087542 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.087542 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.087542 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.087542 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.087542 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13599.207734 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13599.207734 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13599.207734 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13599.207734 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 3107 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 341 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 199 # number of cycles access was blocked
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.613065 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 341 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46165 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 46165 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 46165 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 46165 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 46165 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 46165 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 601046 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 601046 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 601046 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 601046 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 601046 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 601046 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7178040035 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 7178040035 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7178040035 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 7178040035 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7178040035 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 7178040035 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3605250 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3605250 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3605250 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 3605250 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.081298 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.081298 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.081298 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11942.580160 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11942.580160 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11942.580160 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.dcache.tags.replacements 339082 # number of replacements
system.cpu1.dcache.tags.tagsinuse 482.965075 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 12423447 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 339594 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 36.583235 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 71024759250 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.965075 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943291 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.943291 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 57544569 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 57544569 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 8247311 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 8247311 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 3935666 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 3935666 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94453 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 94453 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 92037 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 92037 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 12182977 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 12182977 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 12182977 # number of overall hits
system.cpu1.dcache.overall_hits::total 12182977 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 400036 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 400036 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 1501327 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1501327 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13642 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 13642 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10758 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10758 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 1901363 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 1901363 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 1901363 # number of overall misses
system.cpu1.dcache.overall_misses::total 1901363 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6052529769 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 6052529769 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75305143416 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 75305143416 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124772740 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 124772740 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57202570 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 57202570 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 81357673185 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 81357673185 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 81357673185 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 81357673185 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 8647347 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 8647347 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5436993 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 5436993 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 108095 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 108095 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102795 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 102795 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 14084340 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 14084340 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 14084340 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 14084340 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046261 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.046261 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.276132 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.276132 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126204 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126204 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104655 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104655 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134998 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.134998 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134998 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.134998 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15129.962726 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15129.962726 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50159.054900 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 50159.054900 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9146.220496 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9146.220496 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5317.212307 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5317.212307 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 42789.132420 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 42789.132420 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 27478 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 17677 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 175 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.517669 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 101.011429 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.dcache.writebacks::writebacks 304166 # number of writebacks
system.cpu1.dcache.writebacks::total 304166 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172051 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 172051 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1358464 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 1358464 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1244 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1244 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1530515 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1530515 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1530515 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1530515 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227985 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 227985 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 142863 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 142863 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12398 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12398 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10758 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10758 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 370848 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 370848 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 370848 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 370848 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2835218608 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2835218608 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5632564954 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5632564954 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86730259 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86730259 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35684430 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35684430 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8467783562 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 8467783562 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8467783562 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 8467783562 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 62130810008 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 62130810008 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25850406364 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25850406364 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 87981216372 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 87981216372 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026365 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026365 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026276 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026276 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.114695 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.114695 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104655 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104655 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026331 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026331 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12435.987490 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12435.987490 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39426.338198 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39426.338198 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6995.504033 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6995.504033 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3317.013385 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3317.013385 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1737834287366 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1737834287366 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.kern.inst.quiesce 45161 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu1.kern.inst.quiesce 47884 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
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