stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes throughout.
This commit is contained in:
Andreas Hansson
parent
1d61224a8b
commit
d9193d1b20
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 47.460623 # Nu
|
|||
sim_ticks 47460623015500 # Number of ticks simulated
|
||||
final_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1174285 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1381255 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 63679173545 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 746696 # Number of bytes of host memory used
|
||||
host_seconds 745.31 # Real time elapsed on the host
|
||||
host_inst_rate 731783 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 860761 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 39683148028 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 744736 # Number of bytes of host memory used
|
||||
host_seconds 1195.99 # Real time elapsed on the host
|
||||
sim_insts 875204273 # Number of instructions simulated
|
||||
sim_ops 1029460892 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -1151,6 +1151,7 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.l2cache.unused_prefetches 39383 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu0.l2cache.writebacks::writebacks 1473434 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::total 1473434 # number of writebacks
|
||||
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5831 # number of ReadExReq MSHR hits
|
||||
|
|
@ -2133,6 +2134,7 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.l2cache.unused_prefetches 39620 # number of HardPF blocks evicted w/o reference
|
||||
system.cpu1.l2cache.writebacks::writebacks 1103180 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::total 1103180 # number of writebacks
|
||||
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6962 # number of ReadExReq MSHR hits
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.225711 # Number of seconds simulated
|
||||
sim_ticks 225710988500 # Number of ticks simulated
|
||||
final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.223533 # Number of seconds simulated
|
||||
sim_ticks 223532962500 # Number of ticks simulated
|
||||
final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 329346 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 329346 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 186465123 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304340 # Number of bytes of host memory used
|
||||
host_seconds 1210.47 # Real time elapsed on the host
|
||||
host_inst_rate 354404 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 354404 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 198715635 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 258580 # Number of bytes of host memory used
|
||||
host_seconds 1124.89 # Real time elapsed on the host
|
||||
sim_insts 398664665 # Number of instructions simulated
|
||||
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 249088 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3892 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7870 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1103571 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1127956 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2231526 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1103571 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1103571 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1103571 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1127956 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2231526 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1114323 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1138946 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2253269 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1114323 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1114323 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1114323 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1138946 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2253269 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7870 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7870 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -41,15 +41,15 @@ system.physmem.bytesWrittenSys 0 # To
|
|||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 549 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 676 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 471 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::0 548 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 675 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 473 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 633 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 474 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 477 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 563 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 562 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 560 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 470 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 471 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 437 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 354 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 323 # Per bank write bursts
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 225710901000 # Total gap between requests
|
||||
system.physmem.totGap 223532875000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr
|
|||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 969 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1545 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 324.680906 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 194.047178 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 332.516800 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 535 34.63% 34.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 349 22.59% 57.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 192 12.43% 69.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 105 6.80% 76.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 65 4.21% 80.65% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 39 2.52% 83.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 33 2.14% 85.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 33 2.14% 87.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 194 12.56% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1545 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 52849750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 200412250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 325.149903 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 194.496255 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 330.966466 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 538 34.91% 34.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 340 22.06% 56.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 192 12.46% 69.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 106 6.88% 76.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 56 3.63% 79.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 49 3.18% 83.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 40 2.60% 85.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 36 2.34% 88.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 184 11.94% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 51693000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 199255500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 39350000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6715.34 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6568.36 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25465.34 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 25318.36 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
||||
|
|
@ -216,70 +216,74 @@ system.physmem.busUtilRead 0.02 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6317 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6320 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 80.30 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 28679911.18 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6743520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3679500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 34132800 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 28403160.74 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.30 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6751080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3683625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 34125000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 14742137280 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5830950375 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 130309976250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 150927619725 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.685069 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 216780859000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7536880000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5792542920 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 129035577000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 149472420105 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.696853 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 214662823500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7464080000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1390733500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1403552000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 4936680 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2693625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 27003600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 26933400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 14742137280 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5568136200 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 130540515000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 150885422385 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.498114 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 217165940000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7536880000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5529545775 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 129266276250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 149430056100 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.507329 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 215046035000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7464080000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1005282000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1017823750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 46155674 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 26673496 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 964868 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 25433927 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 21299796 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 45898041 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 26691639 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 566044 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 25194489 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 18810772 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 83.745605 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8306241 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 74.662249 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8282157 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 322 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 2248490 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 2235007 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 13483 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 95501420 # DTB read hits
|
||||
system.cpu.dtb.read_misses 115 # DTB read misses
|
||||
system.cpu.dtb.read_hits 95357145 # DTB read hits
|
||||
system.cpu.dtb.read_misses 114 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 95501535 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73594615 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 95357259 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73594596 # DTB write hits
|
||||
system.cpu.dtb.write_misses 852 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73595467 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 169096035 # DTB hits
|
||||
system.cpu.dtb.data_misses 967 # DTB misses
|
||||
system.cpu.dtb.write_accesses 73595448 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168951741 # DTB hits
|
||||
system.cpu.dtb.data_misses 966 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 169097002 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 98403660 # ITB hits
|
||||
system.cpu.itb.fetch_misses 1242 # ITB misses
|
||||
system.cpu.dtb.data_accesses 168952707 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 96790867 # ITB hits
|
||||
system.cpu.itb.fetch_misses 1237 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 98404902 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 96792104 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -293,26 +297,61 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 451421977 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 447065925 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664665 # Number of instructions committed
|
||||
system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 4268732 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 2363843 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.132335 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.883131 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 447606238 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3815739 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.121408 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.891736 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 141652567 35.53% 41.33% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 94754511 23.77% 81.56% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 73520765 18.44% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 398664665 # Class of committed instruction
|
||||
system.cpu.tickCycles 443407678 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3658247 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 771 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3291.720604 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 167948311 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3291.617120 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 167826980 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40323.724130 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40294.593037 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.720604 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.803643 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803643 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.617120 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.803617 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803617 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
||||
|
|
@ -320,40 +359,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 216
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 335915017 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 335915017 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94433513 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94433513 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 167948311 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 167948311 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 167948311 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 167948311 # number of overall hits
|
||||
system.cpu.dcache.tags.tag_accesses 335672353 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 335672353 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94312181 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94312181 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 167826980 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 167826980 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 167826980 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 167826980 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1183 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1183 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 7115 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7115 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7115 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7115 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 87406500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 87406500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 430164000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 430164000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 517570500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 517570500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 517570500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 517570500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94434696 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94434696 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 7114 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7114 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7114 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7114 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88520000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 88520000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 429316500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 429316500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 517836500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 517836500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 517836500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 517836500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94313364 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94313364 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 167955426 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 167955426 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 167955426 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 167955426 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 167834094 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 167834094 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 167834094 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 167834094 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses
|
||||
|
|
@ -362,14 +401,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73885.460693 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73885.460693 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72515.846258 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 72515.846258 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72743.569923 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72743.569923 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72743.569923 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72743.569923 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74826.711750 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 74826.711750 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72385.179565 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 72385.179565 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72791.186393 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72791.186393 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -382,12 +421,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu
|
|||
system.cpu.dcache.writebacks::total 654 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 214 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2950 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2950 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2950 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2950 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2949 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2949 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2949 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2949 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
|
||||
|
|
@ -396,14 +435,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165
|
|||
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70744000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 70744000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240380000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 240380000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 311124000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 311124000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 311124000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 311124000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 71272000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 71272000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239421000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 239421000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310693000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 310693000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310693000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 310693000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -412,68 +451,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73007.223942 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73007.223942 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75212.765957 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75212.765957 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74699.639856 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74699.639856 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74699.639856 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74699.639856 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73552.115583 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73552.115583 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74912.703379 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74912.703379 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 3187 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1919.659270 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 98398495 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 5165 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19051.015489 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 3190 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1919.630000 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 96785699 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 5168 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18727.882933 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.659270 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.937334 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.937334 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.630000 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.937319 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.937319 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 196812485 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 196812485 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 98398495 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 98398495 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 98398495 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 98398495 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 98398495 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 98398495 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5165 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5165 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5165 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5165 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5165 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5165 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 317382500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 317382500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 317382500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 317382500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 317382500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 317382500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 98403660 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 98403660 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 98403660 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 98403660 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 98403660 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 98403660 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.693127 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61448.693127 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.693127 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61448.693127 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.693127 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61448.693127 # average overall miss latency
|
||||
system.cpu.icache.tags.tag_accesses 193586902 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 193586902 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 96785699 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 96785699 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 96785699 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 96785699 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 96785699 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 96785699 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5168 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5168 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5168 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5168 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5168 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5168 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 316704500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 316704500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 316704500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 316704500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 316704500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 316704500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 96790867 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 96790867 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 96790867 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 96790867 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 96790867 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 96790867 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61281.830495 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61281.830495 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61281.830495 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61281.830495 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61281.830495 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61281.830495 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -482,70 +521,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 3187 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3187 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5165 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 5165 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 5165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 5165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 5165 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 5165 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312217500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 312217500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312217500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 312217500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312217500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 312217500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60448.693127 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60448.693127 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60448.693127 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60448.693127 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60448.693127 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60448.693127 # average overall mshr miss latency
|
||||
system.cpu.icache.writebacks::writebacks 3190 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3190 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 5168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 5168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 5168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 5168 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 5168 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311536500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 311536500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311536500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 311536500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311536500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 311536500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60281.830495 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60281.830495 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4422.016724 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4792 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 4421.902302 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4798 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5270 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.909298 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.910436 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 372.106243 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3407.923384 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 641.987096 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011356 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.134949 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 372.081904 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3407.854115 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 641.966284 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011355 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103999 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019591 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.134946 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5270 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 114772 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 114772 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 114820 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 114820 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 3187 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 3187 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 3190 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 3190 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1273 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1273 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1276 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1276 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1273 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1276 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1460 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1273 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1276 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1460 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1463 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3892 # number of ReadCleanReq misses
|
||||
|
|
@ -558,58 +597,58 @@ system.cpu.l2cache.demand_misses::total 7870 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3892 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7870 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 235063000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 235063000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 291102500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 291102500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 67816500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 67816500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 291102500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 302879500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 593982000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 291102500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 302879500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 593982000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234104000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 234104000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 290385500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 290385500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68345000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 68345000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 290385500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 302449000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 592834500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 290385500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 302449000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 592834500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 3187 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 3187 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 3190 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 3190 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5165 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 5165 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5168 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 5168 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 5165 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 5168 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9330 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 5165 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 9333 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 5168 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9330 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9333 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753533 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753533 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753096 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753096 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753533 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753096 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.843516 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.843244 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753096 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.843516 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74932.419509 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74932.419509 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74795.092497 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74795.092497 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80637.931034 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80637.931034 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74795.092497 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76138.637506 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75474.205845 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74795.092497 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76138.637506 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75474.205845 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.843244 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.713420 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.713420 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74610.868448 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74610.868448 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81266.349584 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81266.349584 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74610.868448 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76030.417295 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75328.398983 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74610.868448 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76030.417295 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75328.398983 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -630,78 +669,78 @@ system.cpu.l2cache.demand_mshr_misses::total 7870
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3892 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7870 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203693000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203693000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252182500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252182500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59406500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59406500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252182500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 263099500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 515282000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252182500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 263099500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 515282000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 202734000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 202734000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 251465500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 251465500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59935000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59935000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251465500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262669000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 514134500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251465500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262669000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 514134500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753533 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753096 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843516 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843244 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843516 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64932.419509 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64932.419509 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64795.092497 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64795.092497 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.931034 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.931034 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64795.092497 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843244 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.713420 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.713420 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64610.868448 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64610.868448 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71266.349584 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71266.349584 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 13288 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3958 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 13294 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3961 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 6135 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 3187 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 3190 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5165 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5168 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13517 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13526 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 22618 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 22627 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 842944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 843328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 9330 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 9333 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 9330 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 9333 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 9330 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10485000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 9333 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10491000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7747500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7752000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -724,9 +763,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7870 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 9171000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 9176500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 41782250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 41781750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,42 +1,42 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.051911 # Number of seconds simulated
|
||||
sim_ticks 51910606500 # Number of ticks simulated
|
||||
final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.051906 # Number of seconds simulated
|
||||
sim_ticks 51905634500 # Number of ticks simulated
|
||||
final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 362776 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 362776 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 204910533 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303308 # Number of bytes of host memory used
|
||||
host_seconds 253.33 # Real time elapsed on the host
|
||||
host_inst_rate 327219 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 327219 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 184808729 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257300 # Number of bytes of host memory used
|
||||
host_seconds 280.86 # Real time elapsed on the host
|
||||
sim_insts 91903089 # Number of instructions simulated
|
||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 340416 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 340480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5319 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 3905791 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2651944 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6557735 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3905791 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3905791 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3905791 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2651944 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6557735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 5319 # Number of read requests accepted
|
||||
system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 3907399 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2652198 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6559596 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3907399 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3907399 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3907399 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2652198 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6559596 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 5320 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 5319 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 340416 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 340416 # Total read bytes from the system interface side
|
||||
system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
|
|
@ -49,7 +49,7 @@ system.physmem.perBankRdBursts::4 224 # Pe
|
|||
system.physmem.perBankRdBursts::5 238 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 222 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 289 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 251 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 252 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 282 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 254 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 261 # Per bank write bursts
|
||||
|
|
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 51910519000 # Total gap between requests
|
||||
system.physmem.totGap 51905547000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 5319 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 5320 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
|
|
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 4921 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 979 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 346.541369 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 213.036393 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 328.369108 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 309 31.56% 31.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 207 21.14% 52.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 105 10.73% 63.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 89 9.09% 72.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 71 7.25% 79.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 31 3.17% 82.94% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 35329750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 135061000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6642.18 # Average queueing delay per DRAM burst
|
||||
system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 346.395112 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 212.989816 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 328.326928 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 308 31.36% 31.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 213 21.69% 53.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 101 10.29% 63.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 90 9.16% 72.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 71 7.23% 79.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 37 3.77% 83.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 21 2.14% 85.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 29 2.95% 88.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 112 11.41% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 32661000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 132411000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6139.29 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25392.18 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24889.29 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -216,70 +216,74 @@ system.physmem.busUtilRead 0.05 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 4332 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 4334 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 81.47 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9759450.84 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3507840 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1914000 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 9756681.77 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.47 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 19983600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 1735573905 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 29619608250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 34770500355 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 669.907919 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 49271583750 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 1736098875 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 29619147750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 34770724710 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 669.912241 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 49270880000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 898672500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 899376250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 3885840 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2120250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 21309600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1825260840 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 29540935500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 34783420965 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 670.156855 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 49142724000 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 1812535875 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 29552097750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 34782010275 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 670.129676 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 49159142250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1030067000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 11441088 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 765853 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 6077536 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5340604 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 11440185 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 6076858 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5316207 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 87.874494 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1173808 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 87.482824 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1173724 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 26312 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 24255 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 2057 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20417089 # DTB read hits
|
||||
system.cpu.dtb.read_misses 43350 # DTB read misses
|
||||
system.cpu.dtb.read_hits 20416195 # DTB read hits
|
||||
system.cpu.dtb.read_misses 43360 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20460439 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6579898 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 20459555 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6579893 # DTB write hits
|
||||
system.cpu.dtb.write_misses 278 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6580176 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26996987 # DTB hits
|
||||
system.cpu.dtb.data_misses 43628 # DTB misses
|
||||
system.cpu.dtb.write_accesses 6580171 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26996088 # DTB hits
|
||||
system.cpu.dtb.data_misses 43638 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 27040615 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 22953519 # ITB hits
|
||||
system.cpu.dtb.data_accesses 27039726 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 22951506 # ITB hits
|
||||
system.cpu.itb.fetch_misses 90 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 22953609 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 22951596 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -293,26 +297,61 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 103821213 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 103811269 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 91903089 # Number of instructions committed
|
||||
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2183676 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 2181586 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.129681 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.885205 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.129573 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.885290 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 91903089 # Class of committed instruction
|
||||
system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1447.424803 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11915.885202 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424803 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.414267 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.353373 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.353373 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||
|
|
@ -320,56 +359,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 227
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 53155492 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 53155492 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20075007 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20075007 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6498193 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26573200 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26573200 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26573200 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26573200 # number of overall hits
|
||||
system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26572424 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26572424 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26572424 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26572424 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2910 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3431 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3431 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3431 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3431 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 214034000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 214034000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 254246500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 254246500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 254246500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 254246500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3429 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3429 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3429 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3429 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40464500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 40464500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 214055500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 214055500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 254520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 254520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 254520000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 254520000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20074750 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20074750 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 26576631 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26576631 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 26576631 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26576631 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 26575853 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26575853 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 26575853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26575853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 74102.739726 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 74102.739726 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77666.986564 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 77666.986564 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73609.181568 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73609.181568 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 74225.721785 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 74225.721785 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -382,12 +421,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu
|
|||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1165 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1201 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1201 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1201 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1201 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1199 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1199 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1199 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1199 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses
|
||||
|
|
@ -396,14 +435,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230
|
|||
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131706500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131706500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168813500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 168813500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168813500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 168813500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36953000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36953000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131397000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131397000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168350000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 168350000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168350000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 168350000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -412,69 +451,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76191.752577 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76191.752577 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75299.140401 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75299.140401 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13850 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1640.456655 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 13853 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15818 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1449.973891 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456655 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1642.330146 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.801919 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.801919 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 671 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 672 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 45922853 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 45922853 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22937703 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22937703 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22937703 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22937703 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22937703 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22937703 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15816 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15816 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15816 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15816 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15816 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15816 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 408931500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 408931500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 408931500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 408931500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 408931500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 408931500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22953519 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22953519 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22953519 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22953519 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22953519 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22953519 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22935687 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22935687 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22935687 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15819 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15819 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15819 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15819 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15819 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15819 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 406827000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 406827000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 406827000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 406827000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 406827000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 406827000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22951506 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22951506 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22951506 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22951506 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22951506 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22951506 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25855.557663 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25855.557663 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25855.557663 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25855.557663 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25855.557663 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25855.557663 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25717.618054 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25717.618054 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25717.618054 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25717.618054 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -483,135 +522,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 13850 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13850 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15816 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 15816 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 15816 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 15816 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15816 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15816 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393116500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 393116500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393116500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 393116500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393116500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 393116500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.writebacks::writebacks 13853 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13853 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15819 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 15819 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 15819 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 15819 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15819 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15819 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 391009000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 391009000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 391009000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 391009000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 391009000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 391009000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24855.620890 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24855.620890 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24855.620890 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24855.620890 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24717.681269 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24717.681269 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2477.794192 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 26614 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3666 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.259684 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3667 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.259067 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.781001 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046719 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 359.966473 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.780381 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.965355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 359.965124 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064088 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064147 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010985 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.075616 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3666 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.075675 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3667 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2505 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111877 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 261827 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 261827 # Number of data accesses
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 13850 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 13850 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 13853 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12647 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 12647 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12649 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 12649 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 12647 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 12649 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 12726 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 12647 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 12728 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 12649 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 12726 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 12728 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1719 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3168 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 3168 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3169 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 3169 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 432 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 432 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3168 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3169 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 2151 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 5319 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses
|
||||
system.cpu.l2cache.demand_misses::total 5320 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3169 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5319 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128816000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 128816000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236598500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 236598500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35817000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35817000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 236598500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 164633000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 401231500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 236598500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 164633000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 401231500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_misses::total 5320 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128506000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 128506000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 234465500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 234465500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35663000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35663000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 234465500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 164169000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 398634500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 234465500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 164169000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 398634500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 13850 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 13850 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 13853 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 13853 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15815 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 15815 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15818 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 15818 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 485 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 485 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 15815 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 15818 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 18045 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 15815 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 18048 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 15818 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 18045 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 18048 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200316 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200316 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200341 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200341 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.890722 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.890722 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200316 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200341 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.294763 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200316 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.294770 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200341 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.294763 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.294770 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74756.253636 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74756.253636 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73987.219943 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73987.219943 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82553.240741 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82553.240741 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74931.296992 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74931.296992 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -622,113 +661,113 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3168 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3168 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 5319 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111626000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111626000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204918500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204918500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204918500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143123000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 348041500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204918500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143123000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 348041500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111316000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111316000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202775500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202775500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31343000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31343000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202775500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 142659000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 345434500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202775500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 142659000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 345434500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200316 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200341 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294770 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294770 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64756.253636 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64756.253636 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63987.219943 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63987.219943 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72553.240741 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72553.240741 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 32058 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14010 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13850 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15818 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45489 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898560 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 50106 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2048128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2048512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18045 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18048 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18045 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18048 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18045 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 29983000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18048 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 29989000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 23727000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 3600 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3601 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 3600 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10638 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10638 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 340416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 5319 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 5320 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 5319 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5319 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 6412500 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 5320 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 6419000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 28165250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 28167750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.130773 # Number of seconds simulated
|
||||
sim_ticks 130772642500 # Number of ticks simulated
|
||||
final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.130383 # Number of seconds simulated
|
||||
sim_ticks 130382890500 # Number of ticks simulated
|
||||
final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 239563 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 252538 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 181805529 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 322304 # Number of bytes of host memory used
|
||||
host_seconds 719.30 # Real time elapsed on the host
|
||||
host_inst_rate 248644 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 262111 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188134778 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275596 # Number of bytes of host memory used
|
||||
host_seconds 693.03 # Real time elapsed on the host
|
||||
sim_insts 172317810 # Number of instructions simulated
|
||||
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138112 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3866 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 130772548000 # Total gap between requests
|
||||
system.physmem.totGap 130382796000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 905 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 271.628729 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 179.806384 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 277.022098 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 259 28.62% 28.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 352 38.90% 67.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 86 9.50% 77.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 59 6.52% 83.54% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 34 3.76% 87.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 21 2.32% 89.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 27654500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 27071500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.01 # Data bus utilization in percentage
|
||||
|
|
@ -216,49 +216,53 @@ system.physmem.busUtilRead 0.01 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 2957 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 2948 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 33826318.68 # Average gap between requests
|
||||
system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 33725503.36 # Average gap between requests
|
||||
system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.826558 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.831686 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.811714 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.803682 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 49732170 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5592247 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 24154061 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 23128262 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 49622074 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 95.753099 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1888632 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -377,69 +381,104 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 261545285 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 260765781 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 172317810 # Number of instructions committed
|
||||
system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 11660914 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.517808 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.658845 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.513284 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.660815 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 181650743 # Class of committed instruction
|
||||
system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 42 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 81519460 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 81519460 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 28348467 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 28348467 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12362639 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 12362639 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 40711106 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40711106 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40711568 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40711568 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 794 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 794 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1648 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1648 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40709659 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2442 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2443 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2441 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
|
||||
|
|
@ -448,10 +487,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40713548 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40713548 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40714011 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40714011 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
|
||||
|
|
@ -462,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -480,34 +519,34 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 550 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 550 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -518,71 +557,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2888 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 2881 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 142037650 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 142037650 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 71011798 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 71011798 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 71011798 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 71011798 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 71011798 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 71011798 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4685 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4685 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4685 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4685 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 71016483 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 71016483 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 71016483 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 70779397 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4678 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 198432500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 198432500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 70784075 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 70784075 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 70784075 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 70784075 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 70784075 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 70784075 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -591,135 +630,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 2888 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2888 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4685 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.writebacks::writebacks 2881 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2881 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193755500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 193755500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193755500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 193755500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 193755500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 193755500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2000.604140 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5191 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2784 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.864583 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 489.811820 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045983 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.061054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2784 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045981 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.061021 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2783 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 151 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084961 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 76658 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 76658 # Number of data accesses
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2566 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 2566 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2524 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2524 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2524 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2612 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 2524 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2612 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 81 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 81 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2517 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 89 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2606 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 2517 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 89 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2606 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2161 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2161 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 631 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 631 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3883 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83327500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 83327500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161329500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 161329500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49900500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 49900500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 161329500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 133228000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 294557500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83479000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 83479000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 159937500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 159937500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50622000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 50622000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 159937500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 134101000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 294038500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 159937500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 134101000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 294038500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2566 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 2566 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 4685 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 4678 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4685 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 6495 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4685 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 6495 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461259 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461259 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461259 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.597844 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4678 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -738,97 +777,97 @@ system.cpu.l2cache.demand_mshr_hits::total 16 #
|
|||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 618 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 618 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.460832 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2888 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12257 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 15919 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 484608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 601472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.257064 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 6033 92.89% 92.89% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 462 7.11% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6495 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7616500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 2776 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1090 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1090 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 2776 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2775 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -844,9 +883,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3866 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000038 # Number of seconds simulated
|
||||
sim_ticks 37629000 # Number of ticks simulated
|
||||
final_tick 37629000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000037 # Number of seconds simulated
|
||||
sim_ticks 37494000 # Number of ticks simulated
|
||||
final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 36642 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 36638 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 214955628 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 227692 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_inst_rate 257461 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 257361 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1504149892 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252900 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 6413 # Number of instructions simulated
|
||||
sim_ops 6413 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu
|
|||
sim_ticks 22532000 # Number of ticks simulated
|
||||
final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 22135 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22134 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 99411388 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226732 # Number of bytes of host memory used
|
||||
host_seconds 0.23 # Real time elapsed on the host
|
||||
host_inst_rate 106399 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 106364 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 479269632 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251364 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 4999 # Number of instructions simulated
|
||||
sim_ops 4999 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -889,10 +889,10 @@ system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22234500
|
|||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6512000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6512000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22234500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 32253500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22234500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 32253500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -933,7 +933,7 @@ system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 #
|
|||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 959 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -959,9 +959,9 @@ system.membus.trans_dist::ReadResp 419 # Tr
|
|||
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 936 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 469 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue