2006-10-06 10:23:27 +02:00
---------- Begin Simulation Statistics ----------
2016-10-14 00:21:40 +02:00
sim_seconds 0.000027 # Number of seconds simulated
sim_ticks 26661500 # Number of ticks simulated
final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2006-10-06 10:23:27 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-11-30 23:12:59 +01:00
host_inst_rate 29979 # Simulator instruction rate (inst/s)
host_op_rate 29977 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 62584510 # Simulator tick rate (ticks/s)
host_mem_usage 237004 # Number of bytes of host memory used
host_seconds 0.43 # Real time elapsed on the host
2016-03-17 18:32:53 +01:00
sim_insts 12770 # Number of instructions simulated
sim_ops 12770 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 21888 # Number of bytes read from this memory
system.physmem.bytes_read::total 61888 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 342 # Number of read requests responded to by this memory
system.physmem.num_reads::total 967 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1500290681 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 820959061 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2321249742 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1500290681 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1500290681 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1500290681 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 820959061 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2321249742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 968 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2016-10-14 00:21:40 +02:00
system.physmem.readBursts 968 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2016-10-14 00:21:40 +02:00
system.physmem.bytesReadDRAM 61952 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2016-10-14 00:21:40 +02:00
system.physmem.bytesReadSys 61952 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::0 84 # Per bank write bursts
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::1 150 # Per bank write bursts
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::2 77 # Per bank write bursts
system.physmem.perBankRdBursts::3 58 # Per bank write bursts
system.physmem.perBankRdBursts::4 90 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::5 45 # Per bank write bursts
system.physmem.perBankRdBursts::6 33 # Per bank write bursts
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::7 50 # Per bank write bursts
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::8 42 # Per bank write bursts
system.physmem.perBankRdBursts::9 38 # Per bank write bursts
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::10 28 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::11 34 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::13 120 # Per bank write bursts
2016-04-08 18:01:45 +02:00
system.physmem.perBankRdBursts::14 67 # Per bank write bursts
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::15 37 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-10-14 00:21:40 +02:00
system.physmem.totGap 26630500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.readPktSize::6 968 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.rdQLenPdf::0 332 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 313 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 185 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 94 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.bytesPerActivate::samples 202 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 289.584158 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 180.299588 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 295.891915 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 69 34.16% 34.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 55 27.23% 61.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 20 9.90% 71.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 16 7.92% 79.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 9 4.46% 83.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 7 3.47% 87.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation
2016-11-30 23:12:59 +01:00
system.physmem.totQLat 15941250 # Total ticks spent queuing
system.physmem.totMemAccLat 34091250 # Total ticks spent from burst creation until serviced by the DRAM
2016-10-14 00:21:40 +02:00
system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers
2016-11-30 23:12:59 +01:00
system.physmem.avgQLat 16468.23 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-11-30 23:12:59 +01:00
system.physmem.avgMemAccLat 35218.23 # Average memory access latency per DRAM burst
2016-10-14 00:21:40 +02:00
system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2016-10-14 00:21:40 +02:00
system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-10-14 00:21:40 +02:00
system.physmem.busUtil 18.15 # Data bus utilization in percentage
system.physmem.busUtilRead 18.15 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2016-08-12 15:12:59 +02:00
system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2016-10-14 00:21:40 +02:00
system.physmem.readRowHits 755 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2016-10-14 00:21:40 +02:00
system.physmem.readRowHitRate 78.00 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2016-10-14 00:21:40 +02:00
system.physmem.avgGap 27510.85 # Average gap between requests
system.physmem.pageHitRate 78.00 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 849660 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 436425 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
2016-11-30 23:12:59 +01:00
system.physmem_0.actBackEnergy 6126930 # Energy for active background per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ)
2016-11-30 23:12:59 +01:00
system.physmem_0.actPowerDownEnergy 5973030 # Energy for active power-down per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ)
system.physmem_0.averagePower 730.243038 # Core power per rank (mW)
system.physmem_0.totalIdleTime 12953500 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
2016-10-14 00:21:40 +02:00
system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states
system.physmem_0.memoryStateTime::ACT 12735000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 13102250 # Time in different power states
system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 330165 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
2016-11-30 23:12:59 +01:00
system.physmem_1.actBackEnergy 4611870 # Energy for active background per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ)
2016-11-30 23:12:59 +01:00
system.physmem_1.actPowerDownEnergy 6909540 # Energy for active power-down per rank (pJ)
2016-10-14 00:21:40 +02:00
system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ)
system.physmem_1.averagePower 660.971589 # Core power per rank (mW)
system.physmem_1.totalIdleTime 16131250 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 312000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
2016-10-14 00:21:40 +02:00
system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 973000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 9438250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 15158250 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 4864 # Number of BP lookups
system.cpu.branchPred.condPredicted 2895 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 795 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 3714 # Number of BTB lookups
system.cpu.branchPred.BTBHits 1183 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-10-14 00:21:40 +02:00
system.cpu.branchPred.BTBHitPct 31.852450 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 710 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 762 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 147 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 615 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 133 # Number of mispredicted indirect branches.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
2016-11-30 23:12:59 +01:00
system.cpu.dtb.read_hits 4131 # DTB read hits
2016-10-14 00:21:40 +02:00
system.cpu.dtb.read_misses 76 # DTB read misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
2016-11-30 23:12:59 +01:00
system.cpu.dtb.read_accesses 4207 # DTB read accesses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.write_hits 2011 # DTB write hits
system.cpu.dtb.write_misses 48 # DTB write misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
2016-10-14 00:21:40 +02:00
system.cpu.dtb.write_accesses 2059 # DTB write accesses
2016-11-30 23:12:59 +01:00
system.cpu.dtb.data_hits 6142 # DTB hits
2016-10-14 00:21:40 +02:00
system.cpu.dtb.data_misses 124 # DTB misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
2016-11-30 23:12:59 +01:00
system.cpu.dtb.data_accesses 6266 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu.itb.fetch_hits 3836 # ITB hits
2016-08-12 15:12:59 +02:00
system.cpu.itb.fetch_misses 50 # ITB misses
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
2016-10-14 00:21:40 +02:00
system.cpu.itb.fetch_accesses 3886 # ITB accesses
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
2016-10-14 00:21:40 +02:00
system.cpu.pwrStateResidencyTicks::ON 26661500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 53324 # number of cpu cycles simulated
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-10-14 00:21:40 +02:00
system.cpu.fetch.icacheStallCycles 748 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 27869 # Number of instructions fetch has processed
system.cpu.fetch.Branches 4864 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2040 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9408 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 875 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed
2016-11-30 23:12:59 +01:00
system.cpu.fetch.rateDist::samples 26305 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.059456 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.449327 # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-11-30 23:12:59 +01:00
system.cpu.fetch.rateDist::0 21280 80.90% 80.90% # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total)
2016-11-30 23:12:59 +01:00
system.cpu.fetch.rateDist::3 446 1.70% 86.00% # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 276 1.05% 92.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-11-30 23:12:59 +01:00
system.cpu.fetch.rateDist::total 26305 # Number of instructions fetched each cycle (Total)
2016-10-14 00:21:40 +02:00
system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle
2016-11-30 23:12:59 +01:00
system.cpu.decode.IdleCycles 36539 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 10373 # Number of cycles decode is blocked
2016-10-14 00:21:40 +02:00
system.cpu.decode.RunCycles 3958 # Number of cycles decode is running
2016-11-30 23:12:59 +01:00
system.cpu.decode.UnblockCycles 496 # Number of cycles decode is unblocking
2016-10-14 00:21:40 +02:00
system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction
2016-11-30 23:12:59 +01:00
system.cpu.decode.DecodedInsts 24588 # Number of instructions handled by decode
2016-10-14 00:21:40 +02:00
system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing
2016-11-30 23:12:59 +01:00
system.cpu.rename.IdleCycles 36883 # Number of cycles rename is idle
2016-10-14 00:21:40 +02:00
system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst
2016-11-30 23:12:59 +01:00
system.cpu.rename.RunCycles 4115 # Number of cycles rename is running
2016-10-14 00:21:40 +02:00
system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
2016-11-30 23:12:59 +01:00
system.cpu.rename.IQFullEvents 222 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 329 # Number of times rename has blocked due to LQ full
2016-10-14 00:21:40 +02:00
system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 29514 # Number of integer rename lookups
2013-10-16 16:44:12 +02:00
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
2016-03-17 18:32:53 +01:00
system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed
2016-10-14 00:21:40 +02:00
system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing
2016-04-08 18:01:45 +02:00
system.cpu.rename.serializingInsts 57 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed
2016-11-30 23:12:59 +01:00
system.cpu.rename.skidInsts 1617 # count of insts added to the skid buffer
2016-10-14 00:21:40 +02:00
system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.memDep1.insertedLoads 2578 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep1.insertedStores 1286 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep1.conflictingLoads 15 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
2016-11-30 23:12:59 +01:00
system.cpu.iq.iqInstsIssued 19298 # Number of instructions issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling
2016-11-30 23:12:59 +01:00
system.cpu.iq.iqSquashedOperandsExamined 4750 # Number of squashed operands that are examined and possibly removed from graph
2016-10-14 00:21:40 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
2016-11-30 23:12:59 +01:00
system.cpu.iq.issued_per_cycle::samples 26305 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.733625 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.450843 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-11-30 23:12:59 +01:00
system.cpu.iq.issued_per_cycle::0 18975 72.13% 72.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 2364 8.99% 81.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1624 6.17% 87.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1293 4.92% 92.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1059 4.03% 96.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 566 2.15% 98.39% # Number of insts issued each cycle
2016-10-14 00:21:40 +02:00
system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-11-30 23:12:59 +01:00
system.cpu.iq.issued_per_cycle::total 26305 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-11-30 23:12:59 +01:00
system.cpu.iq.fu_full::IntAlu 29 9.60% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 193 63.91% 73.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 77 25.50% 99.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite 3 0.99% 100.00% # attempts to use FU when none available
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
2016-11-30 23:12:59 +01:00
system.cpu.iq.FU_type_0::IntAlu 5886 66.05% 66.07% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_0::MemRead 2014 22.60% 88.70% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 999 11.21% 99.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite 7 0.08% 100.00% # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-11-30 23:12:59 +01:00
system.cpu.iq.FU_type_0::total 8912 # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued
system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 65.99% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 65.99% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu.iq.FU_type_1::MemRead 2410 23.20% 89.20% # Type of FU issued
system.cpu.iq.FU_type_1::MemWrite 1114 10.73% 99.92% # Type of FU issued
system.cpu.iq.FU_type_1::FloatMemRead 1 0.01% 99.93% # Type of FU issued
system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu.iq.FU_type_1::total 10386 # Type of FU issued
2016-11-30 23:12:59 +01:00
system.cpu.iq.FU_type::total 19298 0.00% 0.00% # Type of FU issued
system.cpu.iq.rate 0.361901 # Inst issue rate
system.cpu.iq.fu_busy_cnt::0 154 # FU busy when requested
2016-08-12 15:12:59 +02:00
system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested
2016-11-30 23:12:59 +01:00
system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested
system.cpu.iq.fu_busy_rate::0 0.007980 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::1 0.007669 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_busy_rate::total 0.015649 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 65211 # Number of integer instruction queue reads
2016-10-14 00:21:40 +02:00
system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes
2016-11-30 23:12:59 +01:00
system.cpu.iq.int_inst_queue_wakeup_accesses 17509 # Number of integer instruction queue wakeup accesses
2016-10-19 12:20:04 +02:00
system.cpu.iq.fp_inst_queue_reads 43 # Number of floating instruction queue reads
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
2016-11-30 23:12:59 +01:00
system.cpu.iq.int_alu_accesses 19573 # Number of integer alu accesses
2016-10-19 12:20:04 +02:00
system.cpu.iq.fp_alu_accesses 23 # Number of floating point alu accesses
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 740 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 228 # Number of stores squashed
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2012-10-30 14:35:32 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread1.forwLoads 97 # Number of loads that had data forwarded from stores
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread1.squashedLoads 1393 # Number of loads squashed
system.cpu.iew.lsq.thread1.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations
system.cpu.iew.lsq.thread1.squashedStores 421 # Number of stores squashed
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
2016-10-14 00:21:40 +02:00
system.cpu.iew.lsq.thread1.cacheBlocked 234 # Number of times an access to memory failed due to the cache being blocked
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-10-14 00:21:40 +02:00
system.cpu.iew.iewSquashCycles 725 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1992 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 420 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 21985 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 4503 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2379 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 390 # Number of times the LSQ has become full, causing a stall
2016-04-08 18:01:45 +02:00
system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
2016-10-14 00:21:40 +02:00
system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute
2016-11-30 23:12:59 +01:00
system.cpu.iew.iewExecutedInsts 18590 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts::0 1946 # Number of load instructions executed
2016-10-14 00:21:40 +02:00
system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed
2016-11-30 23:12:59 +01:00
system.cpu.iew.iewExecLoadInsts::total 4210 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
2016-10-14 00:21:40 +02:00
system.cpu.iew.exec_nop::0 63 # number of nop insts executed
system.cpu.iew.exec_nop::1 71 # number of nop insts executed
system.cpu.iew.exec_nop::total 134 # number of nop insts executed
2016-11-30 23:12:59 +01:00
system.cpu.iew.exec_refs::0 2943 # number of memory reference insts executed
2016-10-14 00:21:40 +02:00
system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed
2016-11-30 23:12:59 +01:00
system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed
2016-10-14 00:21:40 +02:00
system.cpu.iew.exec_branches::0 1393 # Number of branches executed
system.cpu.iew.exec_branches::1 1580 # Number of branches executed
system.cpu.iew.exec_branches::total 2973 # Number of branches executed
system.cpu.iew.exec_stores::0 997 # Number of stores executed
system.cpu.iew.exec_stores::1 1074 # Number of stores executed
system.cpu.iew.exec_stores::total 2071 # Number of stores executed
2016-11-30 23:12:59 +01:00
system.cpu.iew.exec_rate 0.348624 # Inst execution rate
system.cpu.iew.wb_sent::0 8287 # cumulative count of insts sent to commit
2016-10-14 00:21:40 +02:00
system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit
2016-11-30 23:12:59 +01:00
system.cpu.iew.wb_sent::total 17783 # cumulative count of insts sent to commit
system.cpu.iew.wb_count::0 8202 # cumulative count of insts written-back
2016-10-14 00:21:40 +02:00
system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back
2016-11-30 23:12:59 +01:00
system.cpu.iew.wb_count::total 17529 # cumulative count of insts written-back
system.cpu.iew.wb_producers::0 4343 # num instructions producing a value
system.cpu.iew.wb_producers::1 4920 # num instructions producing a value
system.cpu.iew.wb_producers::total 9263 # num instructions producing a value
system.cpu.iew.wb_consumers::0 5887 # num instructions consuming a value
system.cpu.iew.wb_consumers::1 6620 # num instructions consuming a value
system.cpu.iew.wb_consumers::total 12507 # num instructions consuming a value
system.cpu.iew.wb_rate::0 0.153814 # insts written-back per cycle
2016-10-14 00:21:40 +02:00
system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle
2016-11-30 23:12:59 +01:00
system.cpu.iew.wb_rate::total 0.328726 # insts written-back per cycle
system.cpu.iew.wb_fanout::0 0.737727 # average fanout of values written-back
system.cpu.iew.wb_fanout::1 0.743202 # average fanout of values written-back
system.cpu.iew.wb_fanout::total 0.740625 # average fanout of values written-back
2016-10-14 00:21:40 +02:00
system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit
2006-10-06 10:23:27 +02:00
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
2016-10-14 00:21:40 +02:00
system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted
2016-11-30 23:12:59 +01:00
system.cpu.commit.committed_per_cycle::samples 26287 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.487085 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.404867 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-11-30 23:12:59 +01:00
system.cpu.commit.committed_per_cycle::0 21303 81.04% 81.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 2500 9.51% 90.55% # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle
2016-11-30 23:12:59 +01:00
system.cpu.commit.committed_per_cycle::3 402 1.53% 95.60% # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle
2016-11-30 23:12:59 +01:00
system.cpu.commit.committed_per_cycle::5 154 0.59% 97.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 214 0.81% 97.95% # Number of insts commited each cycle
2016-10-14 00:21:40 +02:00
system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle
2016-11-30 23:12:59 +01:00
system.cpu.commit.committed_per_cycle::8 423 1.61% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-11-30 23:12:59 +01:00
system.cpu.commit.committed_per_cycle::total 26287 # Number of insts commited each cycle
2016-03-17 18:32:53 +01:00
system.cpu.commit.committedInsts::0 6402 # Number of instructions committed
system.cpu.commit.committedInsts::1 6402 # Number of instructions committed
system.cpu.commit.committedInsts::total 12804 # Number of instructions committed
system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
2016-03-17 18:32:53 +01:00
system.cpu.commit.refs::0 2050 # Number of memory references committed
system.cpu.commit.refs::1 2050 # Number of memory references committed
system.cpu.commit.refs::total 4100 # Number of memory references committed
system.cpu.commit.loads::0 1185 # Number of loads committed
system.cpu.commit.loads::1 1185 # Number of loads committed
system.cpu.commit.loads::total 2370 # Number of loads committed
2011-04-20 03:45:23 +02:00
system.cpu.commit.membars::0 0 # Number of memory barriers committed
system.cpu.commit.membars::1 0 # Number of memory barriers committed
system.cpu.commit.membars::total 0 # Number of memory barriers committed
2016-03-17 18:32:53 +01:00
system.cpu.commit.branches::0 1056 # Number of branches committed
system.cpu.commit.branches::1 1056 # Number of branches committed
system.cpu.commit.branches::total 2112 # Number of branches committed
2011-07-10 19:56:09 +02:00
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
2016-03-17 18:32:53 +01:00
system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions.
system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions.
system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions.
2011-07-10 19:56:09 +02:00
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction
system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction
system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction
system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.98% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu.commit.op_class_1::MemRead 1184 18.49% 86.47% # Class of committed instruction
system.cpu.commit.op_class_1::MemWrite 858 13.40% 99.88% # Class of committed instruction
system.cpu.commit.op_class_1::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
system.cpu.commit.op_class_1::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-03-17 18:32:53 +01:00
system.cpu.commit.op_class_1::total 6402 # Class of committed instruction
system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction
2016-11-30 23:12:59 +01:00
system.cpu.commit.bw_lim_events 423 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 113065 # The number of ROB reads
2016-10-14 00:21:40 +02:00
system.cpu.rob.rob_writes 45570 # The number of ROB writes
system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself
2016-11-30 23:12:59 +01:00
system.cpu.idleCycles 27019 # Total number of cycles that the CPU has spent unscheduled due to idling
2016-03-17 18:32:53 +01:00
system.cpu.committedInsts::0 6385 # Number of Instructions Simulated
system.cpu.committedInsts::1 6385 # Number of Instructions Simulated
system.cpu.committedInsts::total 12770 # Number of Instructions Simulated
system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated
system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated
2016-10-14 00:21:40 +02:00
system.cpu.cpi::0 8.351449 # CPI: Cycles Per Instruction
system.cpu.cpi::1 8.351449 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.175724 # CPI: Total CPI of All Threads
system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle
system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads
2016-11-30 23:12:59 +01:00
system.cpu.int_regfile_reads 23483 # number of integer regfile reads
system.cpu.int_regfile_writes 13138 # number of integer regfile writes
2011-02-08 04:23:13 +01:00
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
2011-07-10 19:56:09 +02:00
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
2016-11-30 23:12:59 +01:00
system.cpu.dcache.tags.tagsinuse 216.020896 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4237 # Total number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks.
2016-11-30 23:12:59 +01:00
system.cpu.dcache.tags.avg_refs 12.388889 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-11-30 23:12:59 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 216.020896 # Average occupied blocks per requestor
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id
2016-11-30 23:12:59 +01:00
system.cpu.dcache.tags.tag_accesses 10870 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 10870 # Number of data accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
2016-11-30 23:12:59 +01:00
system.cpu.dcache.ReadReq_hits::cpu.data 3225 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3225 # number of ReadReq hits
2016-10-14 00:21:40 +02:00
system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits
2016-11-30 23:12:59 +01:00
system.cpu.dcache.demand_hits::cpu.data 4237 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4237 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4237 # number of overall hits
system.cpu.dcache.overall_hits::total 4237 # number of overall hits
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses
system.cpu.dcache.overall_misses::total 1027 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24016000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24016000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 51330451 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 51330451 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 75346451 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.dcache.ReadReq_accesses::cpu.data 3534 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3534 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
2016-11-30 23:12:59 +01:00
system.cpu.dcache.demand_accesses::cpu.data 5264 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 5264 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 5264 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 5264 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087436 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.087436 # miss rate for ReadReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
2016-11-30 23:12:59 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.195099 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.195099 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.195099 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.195099 # miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 71490.878830 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73365.580331 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73365.580331 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5997 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.dcache.blocked::no_mshrs 108 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.527778 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 110 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 574 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 574 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 343 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17847000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17847000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12459487 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12459487 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056310 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056310 # mshr miss rate for ReadReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
2016-11-30 23:12:59 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.065160 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.065160 # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86524.215278 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.replacements::0 7 # number of replacements
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements::1 0 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.replacements::total 7 # number of replacements
2016-11-30 23:12:59 +01:00
system.cpu.icache.tags.tagsinuse 318.054191 # Cycle average of tags in use
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.total_refs 2937 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-11-30 23:12:59 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 318.054191 # Average occupied blocks per requestor
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.155300 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.155300 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 8292 # Number of tag accesses
system.cpu.icache.tags.data_accesses 8292 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 2937 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2937 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2937 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2937 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2937 # number of overall hits
system.cpu.icache.overall_hits::total 2937 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 895 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 895 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 895 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 895 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 895 # number of overall misses
system.cpu.icache.overall_misses::total 895 # number of overall misses
2016-11-30 23:12:59 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 72804995 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 72804995 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 72804995 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 72804995 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 72804995 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 72804995 # number of overall miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233559 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.233559 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.233559 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.233559 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.233559 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.233559 # miss rate for overall accesses
2016-11-30 23:12:59 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81346.363128 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 81346.363128 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 81346.363128 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 81346.363128 # average overall miss latency
2016-10-14 00:21:40 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 3504 # number of cycles access was blocked
2009-04-22 19:25:17 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 60.413793 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.icache.writebacks::writebacks 7 # number of writebacks
system.cpu.icache.writebacks::total 7 # number of writebacks
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 267 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 267 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 267 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 267 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses
2016-11-30 23:12:59 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54756996 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 54756996 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54756996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 54756996 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54756996 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 54756996 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163883 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.163883 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.163883 # mshr miss rate for overall accesses
2016-11-30 23:12:59 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87192.668790 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87192.668790 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.tags.tagsinuse 534.673891 # Cycle average of tags in use
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.sampled_refs 967 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.010341 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.518306 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155585 # Average occupied blocks per requestor
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009720 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006597 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.016317 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 306 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029510 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 625 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 625 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 198 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 625 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 343 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 968 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 343 # number of overall misses
system.cpu.l2cache.overall_misses::total 968 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12308500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12308500 # number of ReadExReq miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53777000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 53777000 # number of ReadCleanReq miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17466000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17466000 # number of ReadSharedReq miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 53777000 # number of demand (read+write) miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.data 29774500 # number of demand (read+write) miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_miss_latency::total 83551500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 53777000 # number of overall miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.data 29774500 # number of overall miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.overall_miss_latency::total 83551500 # number of overall miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses)
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 628 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 628 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 198 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 628 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 343 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 628 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 343 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995223 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995223 # miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995223 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_miss_rate::total 0.996910 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995223 # miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_miss_rate::total 0.996910 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897 # average ReadExReq miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86043.200000 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86043.200000 # average ReadCleanReq miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212 # average ReadSharedReq miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_avg_miss_latency::total 86313.533058 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.overall_avg_miss_latency::total 86313.533058 # average overall miss latency
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 625 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 625 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 968 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10858500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10858500 # number of ReadExReq MSHR miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47527000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47527000 # number of ReadCleanReq MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15496000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15496000 # number of ReadSharedReq MSHR miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47527000 # number of demand (read+write) MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26354500 # number of demand (read+write) MSHR miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::total 73881500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47527000 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26354500 # number of overall MSHR miss cycles
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::total 73881500 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995223 # mshr miss rate for ReadCleanReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.996910 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for overall accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76043.200000 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76043.200000 # average ReadCleanReq mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency
2016-11-30 23:12:59 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter.
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 825 # Transaction distribution
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 628 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1263 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 685 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1948 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40640 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21888 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 971 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.002060 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_fanout::0 969 99.79% 99.79% # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_fanout::total 971 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 496000 # Layer occupancy (ticks)
2016-04-08 18:01:45 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 942000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 513000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 968 # Total number of requests made to the snoop filter.
2016-08-12 15:12:59 +02:00
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 822 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::ReadExReq 145 # Transaction distribution
system.membus.trans_dist::ReadExResp 145 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::ReadSharedReq 823 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1935 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1935 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61888 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 61888 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::samples 968 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::0 968 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::total 968 # Request fanout histogram
system.membus.reqLayer0.occupancy 1179500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 4.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 5127250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 19.2 # Layer utilization (%)
2006-10-06 10:23:27 +02:00
---------- End Simulation Statistics ----------
