2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
2016-12-05 22:48:34 +01:00
sim_seconds 2.826654 # Number of seconds simulated
sim_ticks 2826653666000 # Number of ticks simulated
final_tick 2826653666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-12-05 22:48:34 +01:00
host_inst_rate 170078 # Simulator instruction rate (inst/s)
host_op_rate 206349 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4004321035 # Simulator tick rate (ticks/s)
host_mem_usage 626896 # Number of bytes of host memory used
host_seconds 705.90 # Real time elapsed on the host
sim_insts 120058397 # Number of instructions simulated
sim_ops 145661611 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-12-05 22:48:34 +01:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1325840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1300840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8393920 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
2016-12-05 22:48:34 +01:00
system.physmem.bytes_read::cpu1.inst 176672 # Number of bytes read from this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_read::cpu1.data 586900 # Number of bytes read from this memory
2016-12-05 22:48:34 +01:00
system.physmem.bytes_read::cpu1.l2cache.prefetcher 432960 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-12-05 22:48:34 +01:00
system.physmem.bytes_read::total 12220460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1325840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 176672 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1502512 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8774720 # Number of bytes written to this memory
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
2016-12-05 22:48:34 +01:00
system.physmem.bytes_written::total 8792284 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 22967 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 20846 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 131155 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
2016-12-05 22:48:34 +01:00
system.physmem.num_reads::cpu1.inst 2828 # Number of read requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_reads::cpu1.data 9191 # Number of read requests responded to by this memory
2016-12-05 22:48:34 +01:00
system.physmem.num_reads::cpu1.l2cache.prefetcher 6765 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-12-05 22:48:34 +01:00
system.physmem.num_reads::total 193804 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 137105 # Number of write requests responded to by this memory
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
2016-12-05 22:48:34 +01:00
system.physmem.num_writes::total 141496 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 91 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 469049 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 460205 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2969561 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_read::cpu1.inst 62502 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 207631 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 153171 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_read::total 4323296 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 469049 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 62502 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 531552 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3104278 # Write bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_write::total 3110492 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3104278 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 91 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 469049 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 466405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2969561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_total::cpu1.inst 62502 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 207645 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 153171 # Total bandwidth to/from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.physmem.bw_total::total 7433788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 193805 # Number of read requests accepted
system.physmem.writeReqs 141496 # Number of write requests accepted
system.physmem.readBursts 193805 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 141496 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12392576 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 10880 # Total number of bytes read from write queue
system.physmem.bytesWritten 8805056 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12220524 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8792284 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 170 # Number of DRAM read bursts serviced by the write queue
2016-10-14 00:21:40 +02:00
system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-12-05 22:48:34 +01:00
system.physmem.perBankRdBursts::0 11925 # Per bank write bursts
system.physmem.perBankRdBursts::1 11855 # Per bank write bursts
system.physmem.perBankRdBursts::2 12297 # Per bank write bursts
system.physmem.perBankRdBursts::3 12187 # Per bank write bursts
system.physmem.perBankRdBursts::4 14909 # Per bank write bursts
system.physmem.perBankRdBursts::5 12660 # Per bank write bursts
system.physmem.perBankRdBursts::6 12587 # Per bank write bursts
system.physmem.perBankRdBursts::7 12794 # Per bank write bursts
system.physmem.perBankRdBursts::8 12033 # Per bank write bursts
system.physmem.perBankRdBursts::9 12070 # Per bank write bursts
system.physmem.perBankRdBursts::10 11247 # Per bank write bursts
system.physmem.perBankRdBursts::11 10141 # Per bank write bursts
system.physmem.perBankRdBursts::12 11323 # Per bank write bursts
system.physmem.perBankRdBursts::13 11835 # Per bank write bursts
system.physmem.perBankRdBursts::14 11954 # Per bank write bursts
system.physmem.perBankRdBursts::15 11817 # Per bank write bursts
system.physmem.perBankWrBursts::0 8684 # Per bank write bursts
system.physmem.perBankWrBursts::1 8734 # Per bank write bursts
system.physmem.perBankWrBursts::2 9001 # Per bank write bursts
system.physmem.perBankWrBursts::3 8790 # Per bank write bursts
system.physmem.perBankWrBursts::4 8747 # Per bank write bursts
system.physmem.perBankWrBursts::5 9254 # Per bank write bursts
system.physmem.perBankWrBursts::6 9144 # Per bank write bursts
system.physmem.perBankWrBursts::7 9206 # Per bank write bursts
system.physmem.perBankWrBursts::8 8582 # Per bank write bursts
system.physmem.perBankWrBursts::9 8592 # Per bank write bursts
system.physmem.perBankWrBursts::10 8144 # Per bank write bursts
system.physmem.perBankWrBursts::11 7450 # Per bank write bursts
system.physmem.perBankWrBursts::12 8375 # Per bank write bursts
system.physmem.perBankWrBursts::13 8211 # Per bank write bursts
system.physmem.perBankWrBursts::14 8456 # Per bank write bursts
system.physmem.perBankWrBursts::15 8209 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-12-05 22:48:34 +01:00
system.physmem.numWrRetry 72 # Number of times write queue was full causing retry
system.physmem.totGap 2826653384500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::2 551 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 28 # Read request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.readPktSize::4 3091 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-12-05 22:48:34 +01:00
system.physmem.readPktSize::6 190135 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-12-05 22:48:34 +01:00
system.physmem.writePktSize::6 137105 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 58100 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 70874 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 15772 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12783 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8291 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7517 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 6372 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5340 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4622 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1482 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1128 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 762 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 318 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 269 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-12-05 22:48:34 +01:00
system.physmem.wrQLenPdf::15 2435 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3327 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3886 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4434 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5302 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5614 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10030 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8694 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 10301 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8578 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1036 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 736 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 601 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 443 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 313 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 278 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 265 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 243 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 164 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 84669 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 250.358833 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 141.923887 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 307.724934 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 42961 50.74% 50.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17699 20.90% 71.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6074 7.17% 78.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3410 4.03% 82.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2753 3.25% 86.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1498 1.77% 87.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 998 1.18% 89.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 977 1.15% 90.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8299 9.80% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 84669 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6797 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.488009 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 564.388330 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6795 99.97% 99.97% # Reads before turning the bus around for writes
2016-05-31 12:07:18 +02:00
system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
2016-05-31 17:55:47 +02:00
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
2016-12-05 22:48:34 +01:00
system.physmem.rdPerTurnAround::total 6797 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6797 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.241136 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.514528 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 14.610339 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 6111 89.91% 89.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 128 1.88% 91.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 273 4.02% 95.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 31 0.46% 96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 13 0.19% 96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 14 0.21% 96.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 146 2.15% 98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 13 0.19% 99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 11 0.16% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 7 0.10% 99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 8 0.12% 99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 5 0.07% 99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 4 0.06% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 8 0.12% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 6 0.09% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 2 0.03% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 1 0.01% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 3 0.04% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 2 0.03% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 5 0.07% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 4 0.06% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-327 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6797 # Writes before turning the bus around for reads
system.physmem.totQLat 9919718835 # Total ticks spent queuing
system.physmem.totMemAccLat 13550356335 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 968170000 # Total ticks spent in databus transfers
system.physmem.avgQLat 51228.96 # Average queueing delay per DRAM burst
2016-10-14 00:21:40 +02:00
system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst
2016-12-05 22:48:34 +01:00
system.physmem.avgMemAccLat 69978.86 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.06 # Data bus utilization in percentage
2016-08-12 15:12:59 +02:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-11-06 09:26:50 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2016-12-05 22:48:34 +01:00
system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing
system.physmem.readRowHits 161407 # Number of row buffer hits during reads
system.physmem.writeRowHits 85137 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 61.87 # Row buffer hit rate for writes
system.physmem.avgGap 8430196.70 # Average gap between requests
system.physmem.pageHitRate 74.43 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 316180620 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 168053985 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 722667960 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 373543200 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 4556326320.000001 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 4729873110 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 240133440 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 9128983770 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 6579538080 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 667569876735 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 694387365510 # Total energy per rank (pJ)
system.physmem_0.averagePower 245.657037 # Core power per rank (mW)
system.physmem_0.totalIdleTime 2815586462334 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 417040689 # Time in different power states
system.physmem_0.memoryStateTime::REF 1935564000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 2778497008500 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 17134268560 # Time in different power states
system.physmem_0.memoryStateTime::ACT 8650044977 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 20019739274 # Time in different power states
system.physmem_1.actEnergy 288356040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 153264870 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 659878800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 344619180 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4568619120.000001 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 4738351860 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 236664480 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 8828064240 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 6766632480 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 667633644195 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 694220207745 # Total energy per rank (pJ)
system.physmem_1.averagePower 245.597901 # Core power per rank (mW)
system.physmem_1.totalIdleTime 2815641624954 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 407791169 # Time in different power states
system.physmem_1.memoryStateTime::REF 1940956000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 2778660280000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 17621547350 # Time in different power states
system.physmem_1.memoryStateTime::ACT 8663293877 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 19359797604 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
2016-12-05 22:48:34 +01:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2016-12-05 22:48:34 +01:00
system.cpu0.branchPred.lookups 53099847 # Number of BP lookups
system.cpu0.branchPred.condPredicted 24413538 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 933900 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 32114969 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 13973138 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-12-05 22:48:34 +01:00
system.cpu0.branchPred.BTBHitPct 43.509735 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 15469071 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 33231 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 10119740 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 9963994 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 155746 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 49057 # Number of mispredicted indirect branches.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-12-05 22:48:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-12-05 22:48:34 +01:00
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 65583 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 65583 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25222 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18949 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 21412 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 44171 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 487.310679 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 3087.040611 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191 42986 97.32% 97.32% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383 897 2.03% 99.35% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.63% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767 93 0.21% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959 33 0.07% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535 15 0.03% 100.00% # Table walker wait (enqueue to first request) latency
2016-04-21 10:48:24 +02:00
system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-12-05 22:48:34 +01:00
system.cpu0.dtb.walker.walkWaitTime::total 44171 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 16005 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 11349.047173 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 9735.111358 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 7638.174811 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 14581 91.10% 91.10% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1176 7.35% 98.45% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 210 1.31% 99.76% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::114688-131071 7 0.04% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455 12 0.07% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 16005 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 82168586356 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.591771 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.502145 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 82111702356 99.93% 99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 39388000 0.05% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 7963500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 4902500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 2427000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 777000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 938000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 463500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 24500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 82168586356 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5127 78.72% 78.72% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1386 21.28% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6513 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65583 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-12-05 22:48:34 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65583 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6513 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-12-05 22:48:34 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6513 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 72096 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-12-05 22:48:34 +01:00
system.cpu0.dtb.read_hits 23662283 # DTB read hits
system.cpu0.dtb.read_misses 55655 # DTB read misses
system.cpu0.dtb.write_hits 17589226 # DTB write hits
system.cpu0.dtb.write_misses 9928 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-12-05 22:48:34 +01:00
system.cpu0.dtb.flush_entries 3427 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2234 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-12-05 22:48:34 +01:00
system.cpu0.dtb.perms_faults 915 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 23717938 # DTB read accesses
system.cpu0.dtb.write_accesses 17599154 # DTB write accesses
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-12-05 22:48:34 +01:00
system.cpu0.dtb.hits 41251509 # DTB hits
system.cpu0.dtb.misses 65583 # DTB misses
system.cpu0.dtb.accesses 41317092 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-12-05 22:48:34 +01:00
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 10907 # Table walker walks requested
system.cpu0.itb.walker.walksShort 10907 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3899 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5942 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 1066 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 9841 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 431.460217 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 2241.549622 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095 9464 96.17% 96.17% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191 172 1.75% 97.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383 49 0.50% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479 6 0.06% 99.73% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575 19 0.19% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency
2016-10-14 00:21:40 +02:00
system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
2016-12-05 22:48:34 +01:00
system.cpu0.itb.walker.walkWaitTime::total 9841 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 3645 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12380.384088 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11386.423562 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 5549.123195 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 601 16.49% 16.49% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 2727 74.81% 91.30% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 175 4.80% 96.10% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 87 2.39% 98.49% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
2016-10-14 00:21:40 +02:00
system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
2016-12-05 22:48:34 +01:00
system.cpu0.itb.walker.walkCompletionTime::total 3645 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 22038229712 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.837207 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.369334 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 3588883500 16.28% 16.28% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 18448211212 83.71% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 1065000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 22038229712 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2246 87.09% 87.09% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 333 12.91% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-12-05 22:48:34 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10907 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10907 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-12-05 22:48:34 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 13486 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 72758108 # ITB inst hits
system.cpu0.itb.inst_misses 10907 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-12-05 22:48:34 +01:00
system.cpu0.itb.flush_entries 2282 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-12-05 22:48:34 +01:00
system.cpu0.itb.perms_faults 1937 # Number of TLB faults due to permissions restrictions
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-12-05 22:48:34 +01:00
system.cpu0.itb.inst_accesses 72769015 # ITB inst accesses
system.cpu0.itb.hits 72758108 # DTB hits
system.cpu0.itb.misses 10907 # DTB misses
system.cpu0.itb.accesses 72769015 # DTB accesses
system.cpu0.numPwrStateTransitions 3670 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 1835 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 1484523232.318801 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 23903491534.812244 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 1057 57.60% 57.60% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.13% 99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-12-05 22:48:34 +01:00
system.cpu0.pwrStateClkGateDist::max_value 499970835992 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 1835 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 102553534695 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724100131305 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 205108250 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-12-05 22:48:34 +01:00
system.cpu0.fetch.icacheStallCycles 20843459 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 195936196 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 53099847 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 39406203 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 175823444 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 5691288 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 148299 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 58157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 416860 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 413792 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 98564 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 72757810 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 257476 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 5315 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 200648219 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.193498 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.306871 # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu0.fetch.rateDist::0 95712766 47.70% 47.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 30373277 15.14% 62.84% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 14586568 7.27% 70.11% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 59975608 29.89% 100.00% # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu0.fetch.rateDist::total 200648219 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.258887 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.955282 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 25818393 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 108480918 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 58863420 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 4969304 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2516184 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 3061987 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 333558 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 154376244 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 3806825 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 2516184 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 34429607 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 12873889 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 83899455 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 55085453 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 11843631 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 137696782 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 1037438 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1493634 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 164344 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 57817 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 7635337 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 141807029 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 635200062 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 152788581 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 130609661 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 11197357 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 2697375 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 2554361 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 22576827 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 24592847 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 19077592 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1691886 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2320615 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 134759616 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1714081 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 132897861 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 450666 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10595447 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 21697472 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 119702 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 200648219 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.662343 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 0.961216 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu0.iq.issued_per_cycle::0 123885975 61.74% 61.74% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 33618455 16.75% 78.50% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 31280513 15.59% 94.09% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 10734778 5.35% 99.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1128444 0.56% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 54 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu0.iq.issued_per_cycle::total 200648219 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-12-05 22:48:34 +01:00
system.cpu0.iq.fu_full::IntAlu 10806493 43.96% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 67 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMisc 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5620315 22.86% 66.82% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 8146085 33.14% 99.96% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemRead 2848 0.01% 99.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMemWrite 7137 0.03% 100.00% # attempts to use FU when none available
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu0.iq.FU_type_0::IntAlu 89788621 67.56% 67.56% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 110178 0.08% 67.65% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.65% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 67.65% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.65% # Type of FU issued
2016-10-19 12:20:04 +02:00
system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 67.65% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.65% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.65% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.65% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.65% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 8088 0.01% 67.65% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.65% # Type of FU issued
2016-10-14 00:21:40 +02:00
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu0.iq.FU_type_0::MemRead 24348007 18.32% 85.97% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 18629393 14.02% 99.99% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemRead 3106 0.00% 99.99% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMemWrite 8193 0.01% 100.00% # Type of FU issued
2011-08-19 22:08:09 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu0.iq.FU_type_0::total 132897861 # Type of FU issued
system.cpu0.iq.rate 0.647940 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 24582945 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.184976 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 491444928 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 147076893 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 129373990 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 32623 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11320 # Number of floating instruction queue writes
2016-10-14 00:21:40 +02:00
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses
2016-12-05 22:48:34 +01:00
system.cpu0.iq.int_alu_accesses 157457242 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 21291 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 367347 # Number of loads that had data forwarded from stores
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-12-05 22:48:34 +01:00
system.cpu0.iew.lsq.thread0.squashedLoads 1915298 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2464 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 19139 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 903377 # Number of stores squashed
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-12-05 22:48:34 +01:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 121005 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 360360 # Number of times an access to memory failed due to the cache being blocked
2011-08-19 22:08:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-12-05 22:48:34 +01:00
system.cpu0.iew.iewSquashCycles 2516184 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1671558 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 251575 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 136626375 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-12-05 22:48:34 +01:00
system.cpu0.iew.iewDispLoadInsts 24592847 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 19077592 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 875905 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 27780 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 199746 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 19139 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 262595 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 398520 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 661115 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 131868425 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 23910267 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 963966 # Number of squashed instructions skipped in execute
2011-08-19 22:08:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
2016-12-05 22:48:34 +01:00
system.cpu0.iew.exec_nop 152678 # number of nop insts executed
system.cpu0.iew.exec_refs 42387378 # number of memory reference insts executed
system.cpu0.iew.exec_branches 25593933 # Number of branches executed
system.cpu0.iew.exec_stores 18477111 # Number of stores executed
system.cpu0.iew.exec_rate 0.642921 # Inst execution rate
system.cpu0.iew.wb_sent 131315181 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 129383707 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 66018205 # num instructions producing a value
system.cpu0.iew.wb_consumers 106739719 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.630807 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.618497 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 9567606 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1594379 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 604440 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 197485844 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.638022 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.337140 # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu0.commit.committed_per_cycle::0 137054336 69.40% 69.40% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 33455560 16.94% 86.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 12646051 6.40% 92.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3243439 1.64% 94.39% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 4914257 2.49% 96.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 2777569 1.41% 98.28% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1312207 0.66% 98.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 555201 0.28% 99.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1527224 0.77% 100.00% # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu0.commit.committed_per_cycle::total 197485844 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 104056922 # Number of instructions committed
system.cpu0.commit.committedOps 126000293 # Number of ops (including micro ops) committed
2011-08-19 22:08:09 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
2016-12-05 22:48:34 +01:00
system.cpu0.commit.refs 40851763 # Number of memory references committed
system.cpu0.commit.loads 22677548 # Number of loads committed
system.cpu0.commit.membars 647714 # Number of memory barriers committed
system.cpu0.commit.branches 24989662 # Number of branches committed
2016-05-31 12:07:18 +02:00
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
2016-12-05 22:48:34 +01:00
system.cpu0.commit.int_insts 109983283 # Number of committed integer instructions.
system.cpu0.commit.function_calls 4835482 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu0.commit.op_class_0::IntAlu 85032586 67.49% 67.49% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 107857 0.09% 67.57% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.57% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 67.57% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu0.commit.op_class_0::SimdFloatMisc 8087 0.01% 67.58% # Class of committed instruction
2016-10-14 00:21:40 +02:00
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu0.commit.op_class_0::MemRead 22675292 18.00% 85.57% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 18166767 14.42% 99.99% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu0.commit.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMemWrite 7448 0.01% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu0.commit.op_class_0::total 126000293 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1527224 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 308240127 # The number of ROB reads
system.cpu0.rob.rob_writes 274288918 # The number of ROB writes
system.cpu0.timesIdled 136024 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 4460031 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5448199500 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 103934870 # Number of Instructions Simulated
system.cpu0.committedOps 125878241 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.973431 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.973431 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.506732 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.506732 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 142861191 # number of integer regfile reads
system.cpu0.int_regfile_writes 81742978 # number of integer regfile writes
system.cpu0.fp_regfile_reads 8188 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2265 # number of floating regfile writes
system.cpu0.cc_regfile_reads 465378109 # number of cc regfile reads
system.cpu0.cc_regfile_writes 49818068 # number of cc regfile writes
system.cpu0.misc_regfile_reads 395692849 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1225433 # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 712812 # number of replacements
system.cpu0.dcache.tags.tagsinuse 499.246418 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 37680999 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 713324 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 52.824522 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit.
2016-12-05 22:48:34 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.246418 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975091 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.975091 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu0.dcache.tags.tag_accesses 81225267 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 81225267 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 21467047 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 21467047 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 14989931 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 14989931 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307917 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 307917 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363108 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 363108 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361279 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 361279 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 36456978 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 36456978 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 36764895 # number of overall hits
system.cpu0.dcache.overall_hits::total 36764895 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 649306 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 649306 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1896144 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1896144 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148546 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 148546 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25295 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 25295 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20257 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20257 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2545450 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2545450 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2693996 # number of overall misses
system.cpu0.dcache.overall_misses::total 2693996 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9384044500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 9384044500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32956196365 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 32956196365 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 411578000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 411578000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 478843500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 478843500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 432000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 432000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 42340240865 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 42340240865 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 42340240865 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 42340240865 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 22116353 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 22116353 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 16886075 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 16886075 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456463 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 456463 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388403 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 388403 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381536 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381536 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 39002428 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 39002428 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 39458891 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 39458891 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029359 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.029359 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112290 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.112290 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325428 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325428 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065126 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065126 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053093 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053093 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065264 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.065264 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068273 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.068273 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14452.422279 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14452.422279 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17380.640060 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17380.640060 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16271.120775 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.120775 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23638.421286 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23638.421286 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-12-05 22:48:34 +01:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16633.695757 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16633.695757 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15716.519574 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15716.519574 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 757 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 4969613 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 42 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 201973 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.023810 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 24.605333 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 712815 # number of writebacks
system.cpu0.dcache.writebacks::total 712815 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260774 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 260774 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570443 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1570443 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18576 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18576 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1831217 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1831217 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1831217 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1831217 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388532 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 388532 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325701 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 325701 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102377 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 102377 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6719 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6719 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20257 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20257 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 714233 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 714233 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 816610 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 816610 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32008 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28682 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60690 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5031436500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5031436500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6631878895 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6631878895 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1714108500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1714108500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107735000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107735000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 458598500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458598500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 420000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 420000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11663315395 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 11663315395 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13377423895 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 13377423895 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6681974000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6681974000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6681974000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6681974000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017568 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017568 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019288 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019288 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224283 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224283 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017299 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017299 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053093 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053093 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018313 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.018313 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020695 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.020695 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12949.863846 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12949.863846 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20361.862245 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20361.862245 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16743.101478 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16743.101478 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16034.380116 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16034.380116 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22639.013674 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22639.013674 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-12-05 22:48:34 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16329.846696 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16329.846696 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16381.655741 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16381.655741 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208759.497626 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208759.497626 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110100.082386 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110100.082386 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1249331 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.757700 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 71450204 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1249842 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 57.167389 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6584638000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757700 # Average occupied blocks per requestor
2016-10-14 00:21:40 +02:00
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 125 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu0.icache.tags.tag_accesses 146758301 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 146758301 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 71450207 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 71450207 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 71450207 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 71450207 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 71450207 # number of overall hits
system.cpu0.icache.overall_hits::total 71450207 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1303999 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1303999 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1303999 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1303999 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1303999 # number of overall misses
system.cpu0.icache.overall_misses::total 1303999 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14174791933 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14174791933 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14174791933 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14174791933 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14174791933 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14174791933 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 72754206 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 72754206 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 72754206 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 72754206 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 72754206 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 72754206 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017923 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.017923 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017923 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.017923 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017923 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.017923 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10870.247549 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10870.247549 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10870.247549 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10870.247549 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1760744 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 1640 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 114723 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.347786 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 126.153846 # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 1249331 # number of writebacks
system.cpu0.icache.writebacks::total 1249331 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54109 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 54109 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 54109 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 54109 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 54109 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 54109 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1249890 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1249890 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1249890 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1249890 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1249890 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1249890 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses
2016-12-05 22:48:34 +01:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12814231927 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 12814231927 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12814231927 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 12814231927 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12814231927 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 12814231927 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles
2016-12-05 22:48:34 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017180 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.017180 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.017180 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10252.287743 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846767 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1849379 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 2365 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.prefetcher.pfSpanPage 236461 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 270933 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15649.129225 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 1883932 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 286558 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.574348 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.tags.occ_blocks::writebacks 14546.798617 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.022626 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.137647 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1090.170335 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.887866 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000734 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066539 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.955147 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 298 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15316 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 145 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 80 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1433 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7528 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4690 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1338 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018188 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934814 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 67601036 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 67601036 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54858 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13069 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 67927 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 483646 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 483646 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 1447155 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 1447155 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221212 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 221212 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1179291 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1179291 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 390010 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 390010 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54858 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13069 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1179291 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 611222 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1858440 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54858 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13069 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1179291 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 611222 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1858440 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 514 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 209 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 723 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55801 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 55801 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20257 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 20257 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48873 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 48873 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70560 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 70560 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107498 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 107498 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 514 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 209 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 70560 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 156371 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 227654 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 514 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 209 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 70560 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 156371 # number of overall misses
system.cpu0.l2cache.overall_misses::total 227654 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 15837500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5057000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 20894500 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 37580500 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 37580500 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9656000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9656000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 401500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 401500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3379601499 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 3379601499 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3771387500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3771387500 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3519117997 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3519117997 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 15837500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5057000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3771387500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 6898719496 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 10691001496 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 15837500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5057000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3771387500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 6898719496 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 10691001496 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55372 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13278 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 68650 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 483646 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 483646 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 1447155 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 1447155 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55802 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 55802 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20257 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20257 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270085 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 270085 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1249851 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 1249851 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 497508 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 497508 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55372 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13278 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1249851 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 767593 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2086094 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55372 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13278 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1249851 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 767593 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2086094 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015740 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.010532 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses
2016-03-16 21:03:49 +01:00
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180954 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180954 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056455 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056455 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216073 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216073 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015740 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056455 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.203716 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.109129 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015740 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056455 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.203716 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.109129 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24196.172249 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28899.723375 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 673.473594 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 673.473594 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 476.674730 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 476.674730 # average SCUpgradeReq miss latency
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69150.686453 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69150.686453 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53449.369331 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53449.369331 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32736.590420 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32736.590420 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24196.172249 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53449.369331 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44117.640074 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 46961.623762 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24196.172249 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53449.369331 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44117.640074 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 46961.623762 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 28.714286 # average number of cycles each access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.unused_prefetches 10601 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 229825 # number of writebacks
system.cpu0.l2cache.writebacks::total 229825 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5836 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 5836 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 40 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 40 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 788 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 788 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 40 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6624 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 6668 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 40 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6624 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 6668 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 513 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 206 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 719 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262614 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 262614 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55801 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55801 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20257 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20257 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43037 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 43037 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 70520 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 70520 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106710 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106710 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 513 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 206 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70520 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149747 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 220986 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 513 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 206 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70520 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149747 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262614 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 483600 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35016 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28682 # number of WriteReq MSHR uncacheable
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63698 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3770500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 16512000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17165691219 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17165691219 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 965407999 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 965407999 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 305528000 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 305528000 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 329500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 329500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2246676499 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2246676499 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3346200500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3346200500 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2833954497 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2833954497 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3770500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3346200500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5080630996 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 8443343496 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3770500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3346200500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5080630996 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17165691219 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 25609034715 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6425579500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6690665500 # number of ReadReq MSHR uncacheable cycles
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6425579500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6690665500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010473 # mshr miss rate for ReadReq accesses
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
2016-03-16 21:03:49 +01:00
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159346 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159346 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056423 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214489 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214489 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105933 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231821 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22965.229485 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65364.722441 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17300.908568 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300.908568 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15082.588735 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.588735 # average SCUpgradeReq mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52203.371494 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52203.371494 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47450.375780 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26557.534411 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26557.534411 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38207.594581 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52954.993207 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200749.172082 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191074.523075 # average ReadReq mshr uncacheable latency
2016-10-14 00:21:40 +02:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency
2016-12-05 22:48:34 +01:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105875.424287 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 105037.293165 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 4075722 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058160 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32446 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 214641 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212781 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1860 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 113949 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1910077 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28682 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28682 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 713807 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 1478497 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 89121 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 330731 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 113662 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 288564 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 284982 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1249890 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587175 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 3237 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3755087 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2622795 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29061 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 118492 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 6525435 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159995712 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99013924 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53112 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 221488 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 259284236 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 927446 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 18848064 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 3052004 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.088140 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.285640 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu0.toL2Bus.snoop_fanout::0 2784861 91.25% 91.25% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 265283 8.69% 99.94% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 1860 0.06% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu0.toL2Bus.snoop_fanout::total 3052004 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 4075635489 # Layer occupancy (ticks)
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu0.toL2Bus.snoopLayer0.occupancy 114371967 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu0.toL2Bus.respLayer0.occupancy 1878285609 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu0.toL2Bus.respLayer1.occupancy 1237556949 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu0.toL2Bus.respLayer2.occupancy 15793479 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu0.toL2Bus.respLayer3.occupancy 63149938 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu1.branchPred.lookups 4617850 # Number of BP lookups
system.cpu1.branchPred.condPredicted 2715513 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 269466 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 2413279 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 1525969 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-12-05 22:48:34 +01:00
system.cpu1.branchPred.BTBHitPct 63.232183 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 876806 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 7196 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 247807 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 212871 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 34936 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 10588 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-12-05 22:48:34 +01:00
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 21585 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 21585 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8697 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5905 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 6983 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 14602 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 620.599918 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 3321.361869 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 13932 95.41% 95.41% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.74% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287 228 1.56% 98.30% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383 109 0.75% 99.05% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.21% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575 26 0.18% 99.39% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671 9 0.06% 99.45% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 7 0.05% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 6 0.04% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 14602 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 5436 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11628.403238 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 9929.194928 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 8303.343609 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 1858 34.18% 34.18% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2915 53.62% 87.80% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 446 8.20% 96.01% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 133 2.45% 98.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 34 0.63% 99.08% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.46% 99.54% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343 6 0.11% 99.65% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495 11 0.20% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687 7 0.13% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 5436 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 81885681356 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.177146 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.385706 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 67426452132 82.34% 82.34% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 14437765724 17.63% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2 12512000 0.02% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3 4018500 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4 1336000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5 984500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6 1256500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7 435000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8 231000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9 183500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10 98500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11 31000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12 125000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14 29500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15 188500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 81885681356 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1913 75.20% 75.20% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 631 24.80% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2544 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21585 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-12-05 22:48:34 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21585 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2544 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-12-05 22:48:34 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2544 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 24129 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-12-05 22:48:34 +01:00
system.cpu1.dtb.read_hits 4154069 # DTB read hits
system.cpu1.dtb.read_misses 18709 # DTB read misses
system.cpu1.dtb.write_hits 3480708 # DTB write hits
system.cpu1.dtb.write_misses 2876 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-12-05 22:48:34 +01:00
system.cpu1.dtb.flush_entries 1944 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 52 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-12-05 22:48:34 +01:00
system.cpu1.dtb.perms_faults 381 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 4172778 # DTB read accesses
system.cpu1.dtb.write_accesses 3483584 # DTB write accesses
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-12-05 22:48:34 +01:00
system.cpu1.dtb.hits 7634777 # DTB hits
system.cpu1.dtb.misses 21585 # DTB misses
system.cpu1.dtb.accesses 7656362 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-12-05 22:48:34 +01:00
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 5903 # Table walker walks requested
system.cpu1.itb.walker.walksShort 5903 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2681 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2633 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 589 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 5314 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 359.427926 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 2179.481540 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-2047 5115 96.26% 96.26% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::2048-4095 44 0.83% 97.08% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-6143 38 0.72% 97.80% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.40% 98.19% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-10239 22 0.41% 98.61% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::10240-12287 26 0.49% 99.10% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-14335 16 0.30% 99.40% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.09% 99.49% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-18431 7 0.13% 99.62% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.06% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-22527 3 0.06% 99.74% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.08% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-26623 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.08% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 5314 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1751 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12219.588806 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11149.776616 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5813.276337 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191 298 17.02% 17.02% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383 1260 71.96% 88.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575 107 6.11% 95.09% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767 68 3.88% 98.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959 8 0.46% 99.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.29% 99.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343 3 0.17% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.06% 99.94% # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
2016-12-05 22:48:34 +01:00
system.cpu1.itb.walker.walkCompletionTime::total 1751 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 17441612916 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.860137 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.346964 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 2440154764 13.99% 13.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 15000736652 86.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 721500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 17441612916 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 992 85.37% 85.37% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 170 14.63% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1162 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-12-05 22:48:34 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5903 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5903 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-12-05 22:48:34 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1162 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1162 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 7065 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 8146400 # ITB inst hits
system.cpu1.itb.inst_misses 5903 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-12-05 22:48:34 +01:00
system.cpu1.itb.flush_entries 1127 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-12-05 22:48:34 +01:00
system.cpu1.itb.perms_faults 570 # Number of TLB faults due to permissions restrictions
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-12-05 22:48:34 +01:00
system.cpu1.itb.inst_accesses 8152303 # ITB inst accesses
system.cpu1.itb.hits 8146400 # DTB hits
system.cpu1.itb.misses 5903 # DTB misses
system.cpu1.itb.accesses 8152303 # DTB accesses
system.cpu1.numPwrStateTransitions 5563 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 2782 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 1009807188.625809 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 25701428342.991928 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 1977 71.06% 71.06% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.72% 99.78% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.89% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state
2016-10-14 00:21:40 +02:00
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-12-05 22:48:34 +01:00
system.cpu1.pwrStateClkGateDist::max_value 959983958132 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 2782 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 17370067243 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809283598757 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 34740953 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-12-05 22:48:34 +01:00
system.cpu1.fetch.icacheStallCycles 8935699 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 24503906 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 4617850 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 2615646 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 23842655 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 779742 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 80208 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 31335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 166914 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 295220 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 22708 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 8145254 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 111581 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 33764610 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.884848 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.220160 # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu1.fetch.rateDist::0 20042304 59.36% 59.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 4827845 14.30% 73.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 1634677 4.84% 78.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 7259784 21.50% 100.00% # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-12-05 22:48:34 +01:00
system.cpu1.fetch.rateDist::total 33764610 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.132922 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.705332 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 7349000 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 16390631 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 8692861 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1069281 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 262837 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 706015 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 129761 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 23185557 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 1033744 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 262837 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 8748161 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2379135 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 11360118 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 8342372 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 2671987 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 22035257 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 184232 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 261771 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 36717 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 15492 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1677749 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 21981180 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 102687971 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 25443797 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 19631101 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 2350079 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 398085 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 327427 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 2832658 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 4406260 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 3798525 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 616794 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 601017 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 21230855 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 553061 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 21048993 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 91520 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 2000545 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 4635811 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 42283 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 33764610 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.623404 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.949604 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu1.iq.issued_per_cycle::0 21364495 63.27% 63.27% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 6105280 18.08% 81.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 4197946 12.43% 93.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 1839743 5.45% 99.24% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 257138 0.76% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-12-05 22:48:34 +01:00
system.cpu1.iq.issued_per_cycle::total 33764610 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-12-05 22:48:34 +01:00
system.cpu1.iq.fu_full::IntAlu 1397917 29.28% 29.28% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 677 0.01% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMisc 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.30% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1598296 33.48% 62.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 1774858 37.18% 99.96% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemRead 659 0.01% 99.97% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMemWrite 1349 0.03% 100.00% # attempts to use FU when none available
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu1.iq.FU_type_0::IntAlu 12978869 61.66% 61.66% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 28429 0.14% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.80% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.81% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 4359753 20.71% 82.52% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 3676453 17.47% 99.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemRead 718 0.00% 99.99% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMemWrite 1404 0.01% 100.00% # Type of FU issued
2011-08-19 22:08:09 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-12-05 22:48:34 +01:00
system.cpu1.iq.FU_type_0::total 21048993 # Type of FU issued
system.cpu1.iq.rate 0.605884 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 4773756 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.226793 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 80721609 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 23791762 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 20591914 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 6263 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2082 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1787 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 25818553 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 4130 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 87577 # Number of loads that had data forwarded from stores
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-12-05 22:48:34 +01:00
system.cpu1.iew.lsq.thread0.squashedLoads 404936 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 702 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 9416 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 250549 # Number of stores squashed
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-12-05 22:48:34 +01:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 40531 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 75671 # Number of times an access to memory failed due to the cache being blocked
2011-08-19 22:08:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-12-05 22:48:34 +01:00
system.cpu1.iew.iewSquashCycles 262837 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 524383 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 105080 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 21825012 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-12-05 22:48:34 +01:00
system.cpu1.iew.iewDispLoadInsts 4406260 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 3798525 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 290384 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 7837 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 90528 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 9416 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 33554 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 119405 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 152959 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 20820702 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 4265911 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 206727 # Number of squashed instructions skipped in execute
2011-08-19 22:08:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
2016-12-05 22:48:34 +01:00
system.cpu1.iew.exec_nop 41096 # number of nop insts executed
system.cpu1.iew.exec_refs 7893380 # number of memory reference insts executed
system.cpu1.iew.exec_branches 3012609 # Number of branches executed
system.cpu1.iew.exec_stores 3627469 # Number of stores executed
system.cpu1.iew.exec_rate 0.599313 # Inst execution rate
system.cpu1.iew.wb_sent 20691409 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 20593701 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 10296891 # num instructions producing a value
system.cpu1.iew.wb_consumers 16154886 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.592779 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.637386 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 1790740 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 510778 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 142432 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 33360276 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.594007 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.352197 # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu1.commit.committed_per_cycle::0 23884731 71.60% 71.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 5569703 16.70% 88.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1678289 5.03% 93.32% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 665043 1.99% 95.32% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 510124 1.53% 96.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 336609 1.01% 97.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 218533 0.66% 98.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 117875 0.35% 98.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 379369 1.14% 100.00% # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-12-05 22:48:34 +01:00
system.cpu1.commit.committed_per_cycle::total 33360276 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 16156383 # Number of instructions committed
system.cpu1.commit.committedOps 19816226 # Number of ops (including micro ops) committed
2011-08-19 22:08:09 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2016-12-05 22:48:34 +01:00
system.cpu1.commit.refs 7549300 # Number of memory references committed
system.cpu1.commit.loads 4001324 # Number of loads committed
system.cpu1.commit.membars 208499 # Number of memory barriers committed
system.cpu1.commit.branches 2862007 # Number of branches committed
2016-05-31 12:07:18 +02:00
system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
2016-12-05 22:48:34 +01:00
system.cpu1.commit.int_insts 17632180 # Number of committed integer instructions.
system.cpu1.commit.function_calls 461985 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu1.commit.op_class_0::IntAlu 12236255 61.75% 61.75% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 27370 0.14% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.89% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 61.90% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.90% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.90% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.90% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 4000808 20.19% 82.09% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 3546708 17.90% 99.99% # Class of committed instruction
2016-10-19 12:20:04 +02:00
system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 99.99% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.01% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-12-05 22:48:34 +01:00
system.cpu1.commit.op_class_0::total 19816226 # Class of committed instruction
system.cpu1.commit.bw_lim_events 379369 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 53607539 # The number of ROB reads
system.cpu1.rob.rob_writes 43609460 # The number of ROB writes
system.cpu1.timesIdled 58654 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 976343 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5617999605 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 16123527 # Number of Instructions Simulated
system.cpu1.committedOps 19783370 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.154675 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.154675 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.464107 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.464107 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 23404305 # number of integer regfile reads
system.cpu1.int_regfile_writes 13364979 # number of integer regfile writes
system.cpu1.fp_regfile_reads 1400 # number of floating regfile reads
2016-05-31 12:07:18 +02:00
system.cpu1.fp_regfile_writes 516 # number of floating regfile writes
2016-12-05 22:48:34 +01:00
system.cpu1.cc_regfile_reads 74742517 # number of cc regfile reads
system.cpu1.cc_regfile_writes 6682824 # number of cc regfile writes
system.cpu1.misc_regfile_reads 68331723 # number of misc regfile reads
system.cpu1.misc_regfile_writes 381677 # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 186538 # number of replacements
system.cpu1.dcache.tags.tagsinuse 471.297864 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 6754124 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 186882 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 36.141116 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 89307598000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.297864 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920504 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.920504 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.671875 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 14996504 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 14996504 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 3592307 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 3592307 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 2912324 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 2912324 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49253 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 49253 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78431 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 78431 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70573 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 70573 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 6504631 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 6504631 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 6553884 # number of overall hits
system.cpu1.dcache.overall_hits::total 6553884 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 213962 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 213962 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 393973 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 393973 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30075 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30075 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18449 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 18449 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23608 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23608 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 607935 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 607935 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 638010 # number of overall misses
system.cpu1.dcache.overall_misses::total 638010 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3561244000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3561244000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10027675956 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 10027675956 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 364257500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 364257500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554259000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 554259000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 434000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 434000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 13588919956 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 13588919956 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 13588919956 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 13588919956 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 3806269 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 3806269 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 3306297 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 3306297 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79328 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 79328 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96880 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 96880 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94181 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 94181 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 7112566 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 7112566 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 7191894 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 7191894 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056213 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.056213 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.119158 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.119158 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379122 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379122 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190431 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190431 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250666 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250666 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085473 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.085473 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088712 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.088712 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16644.282630 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16644.282630 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25452.698423 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25452.698423 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19744.024066 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19744.024066 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23477.592342 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23477.592342 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-12-05 22:48:34 +01:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22352.586964 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 22352.586964 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21298.913741 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 21298.913741 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 300 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1464130 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 31 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 39463 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.677419 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 37.101335 # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 186538 # number of writebacks
system.cpu1.dcache.writebacks::total 186538 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78472 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 78472 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 304164 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 304164 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13133 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13133 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 382636 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 382636 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 382636 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 382636 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 135490 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 135490 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89809 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 89809 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28779 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 28779 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5316 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5316 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23608 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23608 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 254078 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 254078 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2880 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2880 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2230 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5110 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5110 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1973019500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1973019500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2438757966 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2438757966 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 489881500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 489881500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95317000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95317000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 530661000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 530661000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 424000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 424000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4411777466 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4411777466 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4901658966 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4901658966 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 386538000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 386538000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 386538000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 386538000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035597 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035597 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027163 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027163 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362785 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362785 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054872 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054872 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250666 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250666 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031676 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.031676 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035328 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.035328 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.104214 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14562.104214 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27154.939549 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27154.939549 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17022.186316 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17022.186316 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17930.210685 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17930.210685 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22478.015927 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22478.015927 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-12-05 22:48:34 +01:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19581.877709 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19581.877709 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19291.945647 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19291.945647 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134214.583333 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 134214.583333 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 75643.444227 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 75643.444227 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 594968 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.436901 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 7527273 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 595480 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 12.640681 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 79132209500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.436901 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975463 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975463 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-12-05 22:48:34 +01:00
system.cpu1.icache.tags.tag_accesses 16885432 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 16885432 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 7527273 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 7527273 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 7527273 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 7527273 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 7527273 # number of overall hits
system.cpu1.icache.overall_hits::total 7527273 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 617701 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 617701 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 617701 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 617701 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 617701 # number of overall misses
system.cpu1.icache.overall_misses::total 617701 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5784933521 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5784933521 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5784933521 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5784933521 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5784933521 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5784933521 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 8144974 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 8144974 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 8144974 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 8144974 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 8144974 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 8144974 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.075838 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.075838 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.075838 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.075838 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.075838 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.075838 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9365.264944 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9365.264944 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9365.264944 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9365.264944 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 523604 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 40 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 42411 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.345948 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 40 # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 594968 # number of writebacks
system.cpu1.icache.writebacks::total 594968 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22217 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 22217 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 22217 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 22217 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 22217 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 22217 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 595484 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 595484 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 595484 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 595484 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 595484 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 595484 # number of overall MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses
2016-12-05 22:48:34 +01:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5318077800 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5318077800 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5318077800 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5318077800 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5318077800 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5318077800 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9663500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9663500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9663500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 9663500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.073111 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.073111 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.073111 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8930.681261 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95678.217822 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95678.217822 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 194116 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 194726 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 546 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.prefetcher.pfSpanPage 59858 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 43575 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 14594.735842 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 700816 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 57699 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 12.146068 # Average number of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.tags.occ_blocks::writebacks 14193.075757 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.827460 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.968470 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 387.864155 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.866277 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000661 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023673 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.890792 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 356 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13738 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 202 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 139 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1740 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8639 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3359 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021729 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001831 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.838501 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 27539438 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 27539438 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17059 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6202 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 23261 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 113931 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 113931 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 655101 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 655101 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27113 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 27113 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 571525 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 571525 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98074 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 98074 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17059 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6202 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 571525 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 125187 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 719973 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17059 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6202 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 571525 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 125187 # number of overall hits
system.cpu1.l2cache.overall_hits::total 719973 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 502 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 304 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 806 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29460 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 29460 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23607 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 23607 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33905 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 33905 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 23957 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 23957 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71492 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 71492 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 502 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 304 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 23957 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 105397 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 130160 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 502 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 304 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 23957 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 105397 # number of overall misses
system.cpu1.l2cache.overall_misses::total 130160 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10772500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6194000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 16966500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12496500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 12496500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 18899500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 18899500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 407499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 407499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1469375000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1469375000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 945511500 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 945511500 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1646741997 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1646741997 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10772500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6194000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 945511500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3116116997 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 4078594997 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10772500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6194000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 945511500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3116116997 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 4078594997 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17561 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6506 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 24067 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113931 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 113931 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 655101 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 655101 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29460 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 29460 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23607 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23607 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61018 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 61018 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 595482 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 595482 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 169566 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 169566 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17561 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6506 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 595482 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 230584 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 850133 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17561 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6506 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 595482 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 230584 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 850133 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046726 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.033490 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555656 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555656 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040231 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040231 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421618 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421618 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046726 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040231 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.457087 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.153105 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046726 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040231 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.457087 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.153105 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20375 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21050.248139 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 424.185336 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 424.185336 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 800.588808 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 800.588808 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 407499 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407499 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43338.003244 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43338.003244 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39467.024252 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39467.024252 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23033.933825 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23033.933825 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20375 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39467.024252 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29565.518914 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 31335.241219 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20375 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39467.024252 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29565.518914 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 31335.241219 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 23.400000 # average number of cycles each access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.unused_prefetches 799 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 31397 # number of writebacks
system.cpu1.l2cache.writebacks::total 31397 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 430 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 430 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 65 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 495 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 505 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 495 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 505 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 501 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 302 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25004 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 25004 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29460 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29460 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23607 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23607 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33475 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 33475 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 23950 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 23950 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71427 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71427 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 501 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 302 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 23950 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104902 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 129655 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 501 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 302 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 23950 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104902 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25004 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 154659 # number of overall MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2880 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 2981 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2230 # number of WriteReq MSHR uncacheable
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5110 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5211 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4342500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12091000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1098165233 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1098165233 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453245500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453245500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 353298500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 353298500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 347499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 347499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1209651000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1209651000 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 801689000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 801689000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1215836497 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1215836497 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4342500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 801689000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2425487497 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 3239267497 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4342500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 801689000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2425487497 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1098165233 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 4337432730 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8906000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 363460500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 372366500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8906000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 363460500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 372366500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548609 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548609 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040220 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.421234 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.421234 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152511 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181923 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15057.285181 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43919.582187 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15385.115411 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15385.115411 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.836404 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.836404 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347499 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347499 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36135.952203 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36135.952203 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33473.444676 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17022.085444 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17022.085444 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24983.745301 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28045.136268 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126201.562500 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124913.284133 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 71127.299413 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 71457.781616 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 1670520 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 844468 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 115035 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106284 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8751 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 31435 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 834833 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2230 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2230 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 146689 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 667575 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 29225 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 30255 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 73183 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41990 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 85875 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 68405 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 65523 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 595484 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 273707 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 370 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1786136 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839744 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14453 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38068 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2678401 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76190416 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29457424 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26024 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70244 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 105744108 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 346325 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 4857548 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 1179057 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.123952 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.351329 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu1.toL2Bus.snoop_fanout::0 1041662 88.35% 88.35% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 128644 10.91% 99.26% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 8751 0.74% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.cpu1.toL2Bus.snoop_fanout::total 1179057 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 1629779992 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu1.toL2Bus.snoopLayer0.occupancy 80742792 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu1.toL2Bus.respLayer0.occupancy 893427297 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu1.toL2Bus.respLayer1.occupancy 378082159 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu1.toL2Bus.respLayer2.occupancy 7957978 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.cpu1.toL2Bus.respLayer3.occupancy 20520473 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.iobus.trans_dist::WriteReq 59420 # Transaction distribution
system.iobus.trans_dist::WriteResp 59420 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56598 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71542 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.iobus.pkt_size::total 2484040 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40388000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer1.occupancy 114000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer7.occupancy 90000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer8.occupancy 573500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer16.occupancy 53000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer23.occupancy 6114001 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer24.occupancy 33826000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.reqLayer25.occupancy 187862511 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iobus.respLayer0.occupancy 84716000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.iocache.tags.replacements 36458 # number of replacements
2016-12-05 22:48:34 +01:00
system.iocache.tags.tagsinuse 14.554422 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2016-05-31 17:55:47 +02:00
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-12-05 22:48:34 +01:00
system.iocache.tags.warmup_cycle 255374847000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.554422 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.909651 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.909651 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-05-31 17:55:47 +02:00
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
2016-12-05 22:48:34 +01:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-05-31 17:55:47 +02:00
system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36476 # number of overall misses
system.iocache.overall_misses::total 36476 # number of overall misses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 39163375 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 39163375 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4357678136 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4357678136 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4396841511 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4396841511 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4396841511 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4396841511 # number of overall miss cycles
2016-05-31 17:55:47 +02:00
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 155410.218254 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 155410.218254 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120298.093419 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120298.093419 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120540.670879 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120540.670879 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 87 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 21.750000 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
2016-05-31 17:55:47 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2016-05-31 17:55:47 +02:00
system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 26563375 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 26563375 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2544616232 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2544616232 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2571179607 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2571179607 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2571179607 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2571179607 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-12-05 22:48:34 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 105410.218254 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 105410.218254 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70246.693684 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70246.693684 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 137305 # number of replacements
system.l2c.tags.tagsinuse 65135.020938 # Cycle average of tags in use
system.l2c.tags.total_refs 548309 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 202660 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.705561 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 87489923000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 6043.335191 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.875782 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 1.068168 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 8238.246856 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6901.068519 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37215.588563 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.685294 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909748 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1676.975803 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 3036.574639 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2001.692374 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.092214 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000258 # Average percentage of cache occupancy
2016-05-31 12:07:18 +02:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
2016-12-05 22:48:34 +01:00
system.l2c.tags.occ_percent::cpu0.inst 0.125706 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.105302 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567865 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
2016-03-16 21:03:49 +01:00
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
2016-12-05 22:48:34 +01:00
system.l2c.tags.occ_percent::cpu1.inst 0.025589 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.046334 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030543 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993882 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 33214 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 32119 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 6015 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 27014 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4859 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 27124 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.506805 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.490097 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6291007 # Number of tag accesses
system.l2c.tags.data_accesses 6291007 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 261222 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 261222 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 41572 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4769 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 46341 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2758 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 2241 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 4999 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 3976 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1584 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5560 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 265 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 106 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 50549 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 57222 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46457 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 49 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 21200 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 11593 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4929 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 192388 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 265 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 106 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 50549 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 61198 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 46457 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 21200 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 13177 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 4929 # number of demand (read+write) hits
system.l2c.demand_hits::total 197948 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 265 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 106 # number of overall hits
system.l2c.overall_hits::cpu0.inst 50549 # number of overall hits
system.l2c.overall_hits::cpu0.data 61198 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 46457 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits
system.l2c.overall_hits::cpu1.inst 21200 # number of overall hits
system.l2c.overall_hits::cpu1.data 13177 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 4929 # number of overall hits
system.l2c.overall_hits::total 197948 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 525 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 273 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 798 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 53 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 86 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 139 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 11064 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8230 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 19294 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 26 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 4 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 19971 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 9413 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131312 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
2016-12-05 22:48:34 +01:00
system.l2c.ReadSharedReq_misses::cpu1.inst 2746 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 945 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6765 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 171189 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 26 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 19971 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 20477 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 131312 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 6 # number of demand (read+write) misses
2016-08-12 15:12:59 +02:00
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
2016-12-05 22:48:34 +01:00
system.l2c.demand_misses::cpu1.inst 2746 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 9175 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 6765 # number of demand (read+write) misses
system.l2c.demand_misses::total 190483 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 26 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu0.inst 19971 # number of overall misses
system.l2c.overall_misses::cpu0.data 20477 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 131312 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 6 # number of overall misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
2016-12-05 22:48:34 +01:00
system.l2c.overall_misses::cpu1.inst 2746 # number of overall misses
system.l2c.overall_misses::cpu1.data 9175 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 6765 # number of overall misses
system.l2c.overall_misses::total 190483 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 10093000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 519000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 10612000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 709500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 365000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 1074500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1647098500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 779902000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2427000500 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4012500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 353000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2097163000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106791000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 538500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 90000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 295133500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 115926000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 20927340320 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 4012500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 353000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 2097163000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 2753889500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 538500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 90000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 295133500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 895828000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 23354340820 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 4012500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 353000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 2097163000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 2753889500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 538500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 90000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 295133500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 895828000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of overall miss cycles
system.l2c.overall_miss_latency::total 23354340820 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 261222 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 261222 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 42097 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5042 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 47139 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 2811 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 2327 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 5138 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 15040 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 9814 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 24854 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 291 # number of ReadSharedReq accesses(hits+misses)
2016-10-14 00:21:40 +02:00
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 110 # number of ReadSharedReq accesses(hits+misses)
2016-12-05 22:48:34 +01:00
system.l2c.ReadSharedReq_accesses::cpu0.inst 70520 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 66635 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177769 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 55 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 19 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 23946 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 12538 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11694 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 363577 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 291 # number of demand (read+write) accesses
2016-10-14 00:21:40 +02:00
system.l2c.demand_accesses::cpu0.itb.walker 110 # number of demand (read+write) accesses
2016-12-05 22:48:34 +01:00
system.l2c.demand_accesses::cpu0.inst 70520 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 81675 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177769 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 55 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 19 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 23946 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 22352 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11694 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 388431 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 291 # number of overall (read+write) accesses
2016-10-14 00:21:40 +02:00
system.l2c.overall_accesses::cpu0.itb.walker 110 # number of overall (read+write) accesses
2016-12-05 22:48:34 +01:00
system.l2c.overall_accesses::cpu0.inst 70520 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 81675 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177769 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 55 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 19 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 23946 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 22352 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11694 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 388431 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012471 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.054145 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.016929 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018855 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.036957 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.027053 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.735638 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.838598 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.776294 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.036364 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.283196 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.141262 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.052632 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.114675 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.075371 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.470847 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.036364 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.283196 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.250713 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.052632 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.114675 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.410478 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.490391 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.036364 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.283196 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.250713 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.052632 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.114675 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.410478 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.490391 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19224.761905 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1901.098901 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 13298.245614 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13386.792453 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4244.186047 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 7730.215827 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 148870.074114 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 94763.304982 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 125790.427076 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88250 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 105010.415102 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 117581.111229 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89750 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 90000 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 107477.603787 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 122673.015873 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 122246.992038 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88250 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 105010.415102 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 134486.960981 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89750 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 90000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 107477.603787 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 97637.929155 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 122605.906144 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 105010.415102 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 134486.960981 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 90000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 107477.603787 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 97637.929155 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 122605.906144 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2016-12-05 22:48:34 +01:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-12-05 22:48:34 +01:00
system.l2c.writebacks::writebacks 100899 # number of writebacks
system.l2c.writebacks::total 100899 # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 11 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 4091 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 4091 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 525 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 273 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 798 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 53 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 86 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 139 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 11064 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 8230 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 19294 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 26 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 4 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19969 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9413 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 6 # number of ReadSharedReq MSHR misses
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
2016-12-05 22:48:34 +01:00
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2738 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 944 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 171178 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 26 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 19969 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 20477 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 6 # number of demand (read+write) MSHR misses
2016-08-12 15:12:59 +02:00
system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
2016-12-05 22:48:34 +01:00
system.l2c.demand_mshr_misses::cpu1.inst 2738 # number of demand (read+write) MSHR misses
2016-10-14 00:21:40 +02:00
system.l2c.demand_mshr_misses::cpu1.data 9174 # number of demand (read+write) MSHR misses
2016-12-05 22:48:34 +01:00
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 190472 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 26 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 19969 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 20477 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 6 # number of overall MSHR misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
2016-12-05 22:48:34 +01:00
system.l2c.overall_mshr_misses::cpu1.inst 2738 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.l2c.overall_mshr_misses::cpu1.data 9174 # number of overall MSHR misses
2016-12-05 22:48:34 +01:00
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 190472 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable
2016-12-05 22:48:34 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable
2016-07-21 18:19:18 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
2016-12-05 22:48:34 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2877 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 37994 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 30912 # number of WriteReq MSHR uncacheable
2016-10-14 00:21:40 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses
2016-12-05 22:48:34 +01:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses
2016-07-21 18:19:18 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
2016-12-05 22:48:34 +01:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5107 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 68906 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 11977000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6297000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 18274000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1386000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1952500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 3338500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1536458500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 697602000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 2234060500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 313000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1897400002 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1012660501 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 478500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 267162500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 106122500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 19214528830 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 313000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 1897400002 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2549119001 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 478500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 80000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 267162500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 803724500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 21448589330 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 313000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 1897400002 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2549119001 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 478500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 80000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 267162500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 803724500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 21448589330 # number of overall MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 210941500 # number of ReadReq MSHR uncacheable cycles
2016-12-05 22:48:34 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5849372000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7087000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 311625000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6379025500 # number of ReadReq MSHR uncacheable cycles
2016-10-14 00:21:40 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 210941500 # number of overall MSHR uncacheable cycles
2016-12-05 22:48:34 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5849372000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7087000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 311625000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6379025500 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-12-05 22:48:34 +01:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012471 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.054145 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.016929 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018855 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.036957 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.027053 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.735638 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.838598 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.776294 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.141262 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.075291 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470816 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.250713 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.410433 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.490363 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.250713 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.410433 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.490363 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22813.333333 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23065.934066 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22899.749373 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26150.943396 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22703.488372 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24017.985612 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138870.074114 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84763.304982 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 115790.427076 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 107581.058217 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 112417.902542 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112248.821870 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124486.936612 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87608.949204 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 112607.571349 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124486.936612 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87608.949204 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 112607.571349 # average overall mshr miss latency
2016-10-14 00:21:40 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency
2016-12-05 22:48:34 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182747.188203 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108315.954119 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167895.601937 # average ReadReq mshr uncacheable latency
2016-10-14 00:21:40 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency
2016-12-05 22:48:34 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96381.150107 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 61019.189348 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92575.762633 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 504615 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 283930 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 621 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-05-31 12:07:18 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-12-05 22:48:34 +01:00
system.membus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 37994 # Transaction distribution
system.membus.trans_dist::ReadResp 209423 # Transaction distribution
system.membus.trans_dist::WriteReq 30912 # Transaction distribution
system.membus.trans_dist::WriteResp 30912 # Transaction distribution
system.membus.trans_dist::WritebackDirty 137105 # Transaction distribution
system.membus.trans_dist::CleanEvict 16916 # Transaction distribution
system.membus.trans_dist::UpgradeReq 65086 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 38844 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 38910 # Transaction distribution
system.membus.trans_dist::ReadExResp 19275 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 171430 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2016-12-05 22:48:34 +01:00
system.membus.trans_dist::InvalidateResp 4600 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 637823 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 759513 # Packet count per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_count::total 832462 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18694600 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18885164 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
2016-12-05 22:48:34 +01:00
system.membus.pkt_size::total 21203308 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 127782 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 36480 # Total snoop traffic (bytes)
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::samples 419404 # Request fanout histogram
system.membus.snoop_fanout::mean 0.012453 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.110898 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::0 414181 98.75% 98.75% # Request fanout histogram
system.membus.snoop_fanout::1 5223 1.25% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.membus.snoop_fanout::total 419404 # Request fanout histogram
system.membus.reqLayer0.occupancy 81639999 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.reqLayer2.occupancy 11433500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.reqLayer5.occupancy 984876925 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.respLayer2.occupancy 1099184232 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.respLayer3.occupancy 7225285 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-12-05 22:48:34 +01:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-12-05 22:48:34 +01:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-12-05 22:48:34 +01:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 1044885 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 541195 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 200373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 29262 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 27938 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 1324 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 37997 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 522881 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30912 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30912 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 362121 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 129726 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 111408 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 43843 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 155251 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 50410 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 50410 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 484889 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 4647 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 3467 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1304964 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 322117 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1627081 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36107224 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5745684 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 41852908 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 395541 # Total snoops (count)
system.toL2Bus.snoopTraffic 15858252 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 901455 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.406700 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.494199 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.toL2Bus.snoop_fanout::0 536157 59.48% 59.48% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 363974 40.38% 99.85% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 1324 0.15% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-12-05 22:48:34 +01:00
system.toL2Bus.snoop_fanout::total 901455 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 896599840 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.toL2Bus.snoopLayer0.occupancy 2176474 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.toL2Bus.respLayer0.occupancy 692364962 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-12-05 22:48:34 +01:00
system.toL2Bus.respLayer1.occupancy 244002323 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2011-08-19 22:08:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-12-05 22:48:34 +01:00
system.cpu0.kern.inst.quiesce 1835 # number of quiesce instructions executed
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-12-05 22:48:34 +01:00
system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
