2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
2016-08-12 15:12:59 +02:00
sim_seconds 2.826111 # Number of seconds simulated
sim_ticks 2826111083000 # Number of ticks simulated
final_tick 2826111083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-08-12 15:12:59 +02:00
host_inst_rate 93135 # Simulator instruction rate (inst/s)
host_op_rate 112984 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2190118612 # Simulator tick rate (ticks/s)
host_mem_usage 627176 # Number of bytes of host memory used
host_seconds 1290.39 # Real time elapsed on the host
sim_insts 120180681 # Number of instructions simulated
sim_ops 145794019 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 1920 # Number of bytes read from this memory
2016-05-31 12:07:18 +02:00
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_read::cpu0.inst 1301824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1315176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8404800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 186528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 599252 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 416192 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_read::total 12227420 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1301824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 186528 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1488352 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8794944 # Number of bytes written to this memory
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_written::total 8812508 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 30 # Number of read requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_reads::cpu0.inst 22588 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 21070 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 131325 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2982 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 6503 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_reads::total 193909 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 137421 # Number of write requests responded to by this memory
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_writes::total 141812 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 679 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_read::cpu0.inst 460641 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 465366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2973981 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 181 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 66002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 212041 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 147267 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_read::total 4326589 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 460641 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 66002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 526643 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3112031 # Write bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_write::total 3118245 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3112031 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 679 # Total bandwidth to/from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_total::cpu0.inst 460641 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 471567 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2973981 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 66002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 212055 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 147267 # Total bandwidth to/from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_total::total 7444834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 193910 # Number of read requests accepted
system.physmem.writeReqs 141812 # Number of write requests accepted
system.physmem.readBursts 193910 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 141812 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12399936 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue
system.physmem.bytesWritten 8824960 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12227484 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8812508 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue
2016-05-31 12:07:18 +02:00
system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::0 12140 # Per bank write bursts
system.physmem.perBankRdBursts::1 12135 # Per bank write bursts
system.physmem.perBankRdBursts::2 12398 # Per bank write bursts
system.physmem.perBankRdBursts::3 12886 # Per bank write bursts
system.physmem.perBankRdBursts::4 14558 # Per bank write bursts
system.physmem.perBankRdBursts::5 12353 # Per bank write bursts
system.physmem.perBankRdBursts::6 12494 # Per bank write bursts
system.physmem.perBankRdBursts::7 12590 # Per bank write bursts
system.physmem.perBankRdBursts::8 12207 # Per bank write bursts
system.physmem.perBankRdBursts::9 12490 # Per bank write bursts
system.physmem.perBankRdBursts::10 11644 # Per bank write bursts
system.physmem.perBankRdBursts::11 10772 # Per bank write bursts
system.physmem.perBankRdBursts::12 11273 # Per bank write bursts
system.physmem.perBankRdBursts::13 11534 # Per bank write bursts
system.physmem.perBankRdBursts::14 11359 # Per bank write bursts
system.physmem.perBankRdBursts::15 10916 # Per bank write bursts
system.physmem.perBankWrBursts::0 8885 # Per bank write bursts
system.physmem.perBankWrBursts::1 8987 # Per bank write bursts
system.physmem.perBankWrBursts::2 9257 # Per bank write bursts
system.physmem.perBankWrBursts::3 9509 # Per bank write bursts
system.physmem.perBankWrBursts::4 8433 # Per bank write bursts
system.physmem.perBankWrBursts::5 8902 # Per bank write bursts
system.physmem.perBankWrBursts::6 9078 # Per bank write bursts
system.physmem.perBankWrBursts::7 8908 # Per bank write bursts
system.physmem.perBankWrBursts::8 8674 # Per bank write bursts
system.physmem.perBankWrBursts::9 9007 # Per bank write bursts
system.physmem.perBankWrBursts::10 8474 # Per bank write bursts
system.physmem.perBankWrBursts::11 8031 # Per bank write bursts
system.physmem.perBankWrBursts::12 8318 # Per bank write bursts
system.physmem.perBankWrBursts::13 8000 # Per bank write bursts
system.physmem.perBankWrBursts::14 7983 # Per bank write bursts
system.physmem.perBankWrBursts::15 7444 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-08-12 15:12:59 +02:00
system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
system.physmem.totGap 2826110796000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::2 551 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 28 # Read request sizes (log2)
2016-07-21 18:19:18 +02:00
system.physmem.readPktSize::4 3086 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.readPktSize::6 190245 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.writePktSize::6 137421 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 59620 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 70390 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 15526 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12745 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8439 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7276 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 6358 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5209 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4584 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1421 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 930 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 679 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 302 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 262 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.wrQLenPdf::15 2582 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3484 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4772 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5590 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5845 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6981 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8598 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8675 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9940 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 10692 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9309 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 10995 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8918 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8250 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7922 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 642 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 501 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 228 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 84734 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 250.487785 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 142.325533 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 306.970890 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 42837 50.55% 50.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17738 20.93% 71.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6168 7.28% 78.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3519 4.15% 82.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2713 3.20% 86.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1549 1.83% 87.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 945 1.12% 89.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1056 1.25% 90.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8209 9.69% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 84734 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6846 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.300175 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 562.386287 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6844 99.97% 99.97% # Reads before turning the bus around for writes
2016-05-31 12:07:18 +02:00
system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
2016-05-31 17:55:47 +02:00
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
2016-08-12 15:12:59 +02:00
system.physmem.rdPerTurnAround::total 6846 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6846 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.141689 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.636499 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.164291 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5708 83.38% 83.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 378 5.52% 88.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 91 1.33% 90.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 47 0.69% 90.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 276 4.03% 94.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 33 0.48% 95.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 21 0.31% 95.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 23 0.34% 96.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 19 0.28% 96.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 10 0.15% 96.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 2 0.03% 96.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 9 0.13% 96.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 166 2.42% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 9 0.13% 99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 4 0.06% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 11 0.16% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 6 0.09% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.03% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 3 0.04% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 2 0.03% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 3 0.04% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 2 0.03% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 3 0.04% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 7 0.10% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 2 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 3 0.04% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6846 # Writes before turning the bus around for reads
system.physmem.totQLat 6600075879 # Total ticks spent queuing
system.physmem.totMemAccLat 10232869629 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 968745000 # Total ticks spent in databus transfers
system.physmem.avgQLat 34065.08 # Average queueing delay per DRAM burst
2016-03-16 21:03:49 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-08-12 15:12:59 +02:00
system.physmem.avgMemAccLat 52815.08 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.06 # Data bus utilization in percentage
2016-08-12 15:12:59 +02:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-11-06 09:26:50 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2016-08-12 15:12:59 +02:00
system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing
system.physmem.readRowHits 161373 # Number of row buffer hits during reads
system.physmem.writeRowHits 85531 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes
system.physmem.avgGap 8418008.94 # Average gap between requests
system.physmem.pageHitRate 74.44 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 338612400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 184758750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 792121200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 466294320 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 79311033765 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1626092117250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1891772383845 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.392029 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2705053539598 # Time in different power states
system.physmem_0.memoryStateTime::REF 94369860000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_0.memoryStateTime::ACT 26681946652 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.actEnergy 301976640 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 164769000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 719113200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 427232880 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 78534447525 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1626773333250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1891508318655 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.298592 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2706191706230 # Time in different power states
system.physmem_1.memoryStateTime::REF 94369860000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.memoryStateTime::ACT 25549496770 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2016-08-12 15:12:59 +02:00
system.cpu0.branchPred.lookups 23913557 # Number of BP lookups
system.cpu0.branchPred.condPredicted 15655751 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 926443 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 14584665 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 9536401 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-08-12 15:12:59 +02:00
system.cpu0.branchPred.BTBHitPct 65.386493 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 3854213 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 33180 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 1360238 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 1204672 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 155566 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 48773 # Number of mispredicted indirect branches.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 65918 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 65918 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25327 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18922 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 21669 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 44249 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 506.926710 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 3129.335275 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191 43005 97.19% 97.19% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383 929 2.10% 99.29% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.33% 99.62% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959 23 0.05% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 100.00% # Table walker wait (enqueue to first request) latency
2016-04-21 10:48:24 +02:00
system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkWaitTime::total 44249 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 16055 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 11307.848022 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 9898.999015 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 6813.334576 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 14595 90.91% 90.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1294 8.06% 98.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 134 0.83% 99.80% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535 9 0.06% 99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687 17 0.11% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkCompletionTime::total 16055 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 85920956152 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.541941 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.508329 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 85862493152 99.93% 99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 40323000 0.05% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 8212500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 5190500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 2626000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 886000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 336500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 44000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 85920956152 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5102 78.63% 78.63% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1387 21.37% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6489 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65918 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65918 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6489 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6489 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 72407 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.read_hits 17729387 # DTB read hits
system.cpu0.dtb.read_misses 55806 # DTB read misses
system.cpu0.dtb.write_hits 14606301 # DTB write hits
system.cpu0.dtb.write_misses 10112 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.flush_entries 3431 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 353 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2188 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.perms_faults 939 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 17785193 # DTB read accesses
system.cpu0.dtb.write_accesses 14616413 # DTB write accesses
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-08-12 15:12:59 +02:00
system.cpu0.dtb.hits 32335688 # DTB hits
system.cpu0.dtb.misses 65918 # DTB misses
system.cpu0.dtb.accesses 32401606 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 10845 # Table walker walks requested
system.cpu0.itb.walker.walksShort 10845 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3752 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6021 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 1072 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 438.606364 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 2276.348067 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095 9409 96.28% 96.28% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287 121 1.24% 99.16% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383 47 0.48% 99.64% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.71% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575 16 0.16% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671 6 0.06% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 3657 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12272.627837 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11484.483595 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 4878.254960 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 514 14.06% 14.06% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 2884 78.86% 92.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 170 4.65% 97.57% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 55 1.50% 99.07% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 31 0.85% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.walkCompletionTime::total 3657 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 21495635712 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.820169 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.384194 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 3866725500 17.99% 17.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 17627832712 82.01% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 1008500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 69000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 21495635712 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2254 87.20% 87.20% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 331 12.80% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2585 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10845 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10845 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2585 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2585 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 13430 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 37503849 # ITB inst hits
system.cpu0.itb.inst_misses 10845 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-08-12 15:12:59 +02:00
system.cpu0.itb.flush_entries 2291 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu0.itb.perms_faults 1944 # Number of TLB faults due to permissions restrictions
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-08-12 15:12:59 +02:00
system.cpu0.itb.inst_accesses 37514694 # ITB inst accesses
system.cpu0.itb.hits 37503849 # DTB hits
system.cpu0.itb.misses 10845 # DTB misses
system.cpu0.itb.accesses 37514694 # DTB accesses
system.cpu0.numPwrStateTransitions 3712 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 1856 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 1487215700.959052 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 23895599673.728432 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 1080 58.19% 58.19% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 769 41.43% 99.62% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu0.pwrStateClkGateDist::max_value 499971395296 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 1856 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 65838742020 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2760272340980 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 131678547 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-08-12 15:12:59 +02:00
system.cpu0.fetch.icacheStallCycles 19262499 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 112028029 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 23913557 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 14595286 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 106047706 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2739238 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 149116 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 57008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 423158 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 407524 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 94244 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 37503537 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 259263 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 5228 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 127810874 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.056272 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.258048 # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-08-12 15:12:59 +02:00
system.cpu0.fetch.rateDist::0 65678610 51.39% 51.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 21331326 16.69% 68.08% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 8731054 6.83% 74.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 32069884 25.09% 100.00% # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-08-12 15:12:59 +02:00
system.cpu0.fetch.rateDist::total 127810874 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.181606 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.850769 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 19867897 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 60850603 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 41086114 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 4967748 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1038512 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 3035925 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 335186 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 110135169 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 3776324 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1038512 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 25520251 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 12577304 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 37369361 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 40264186 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 11041260 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 105172145 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 1006076 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1476626 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 165177 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 58768 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 6832387 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 109365921 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 480109573 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 120259513 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 9447 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 98266494 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 11099416 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1228555 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 1085594 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 12372656 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 18663457 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 16076197 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1697816 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2228906 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 102290291 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1693186 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 100457201 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 451571 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 9045594 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 21384310 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 120136 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 127810874 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.785983 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.028831 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-08-12 15:12:59 +02:00
system.cpu0.iq.issued_per_cycle::0 71664386 56.07% 56.07% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 23315575 18.24% 74.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 22454220 17.57% 91.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 9273638 7.26% 99.14% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1103003 0.86% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 52 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-08-12 15:12:59 +02:00
system.cpu0.iq.issued_per_cycle::total 127810874 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-08-12 15:12:59 +02:00
system.cpu0.iq.fu_full::IntAlu 9324082 40.55% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 74 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5582954 24.28% 64.83% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 8086742 35.17% 100.00% # attempts to use FU when none available
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
2016-08-12 15:12:59 +02:00
system.cpu0.iq.FU_type_0::IntAlu 66279940 65.98% 65.98% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 93468 0.09% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 8018 0.01% 66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 18419781 18.34% 84.42% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 15653721 15.58% 100.00% # Type of FU issued
2011-08-19 22:08:09 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-08-12 15:12:59 +02:00
system.cpu0.iq.FU_type_0::total 100457201 # Type of FU issued
system.cpu0.iq.rate 0.762897 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 22993852 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.228892 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 352138149 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 113036952 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 98428366 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 32549 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 123427553 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 21227 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 365954 # Number of loads that had data forwarded from stores
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-08-12 15:12:59 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 1901526 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2478 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 19250 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 882682 # Number of stores squashed
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-08-12 15:12:59 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 110051 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 360569 # Number of times an access to memory failed due to the cache being blocked
2011-08-19 22:08:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-08-12 15:12:59 +02:00
system.cpu0.iew.iewSquashCycles 1038512 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1592668 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 210705 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 104136429 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-08-12 15:12:59 +02:00
system.cpu0.iew.iewDispLoadInsts 18663457 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 16076197 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 876152 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 28505 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 158159 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 19250 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 253073 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 398879 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 651952 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 99436169 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 17977378 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 955231 # Number of squashed instructions skipped in execute
2011-08-19 22:08:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
2016-08-12 15:12:59 +02:00
system.cpu0.iew.exec_nop 152952 # number of nop insts executed
system.cpu0.iew.exec_refs 33471315 # number of memory reference insts executed
system.cpu0.iew.exec_branches 16838084 # Number of branches executed
system.cpu0.iew.exec_stores 15493937 # Number of stores executed
system.cpu0.iew.exec_rate 0.755143 # Inst execution rate
system.cpu0.iew.wb_sent 98890175 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 98438082 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 51269761 # num instructions producing a value
system.cpu0.iew.wb_consumers 84681895 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.747564 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.605439 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 8044326 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1573050 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 595336 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 126126769 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.753686 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.472161 # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-08-12 15:12:59 +02:00
system.cpu0.commit.committed_per_cycle::0 81783872 64.84% 64.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 24707932 19.59% 84.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 8259395 6.55% 90.98% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3211630 2.55% 93.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 3438301 2.73% 96.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 1493917 1.18% 97.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1163537 0.92% 98.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 551177 0.44% 98.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1517008 1.20% 100.00% # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-08-12 15:12:59 +02:00
system.cpu0.commit.committed_per_cycle::total 126126769 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 79016795 # Number of instructions committed
system.cpu0.commit.committedOps 95059926 # Number of ops (including micro ops) committed
2011-08-19 22:08:09 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
2016-08-12 15:12:59 +02:00
system.cpu0.commit.refs 31955445 # Number of memory references committed
system.cpu0.commit.loads 16761930 # Number of loads committed
system.cpu0.commit.membars 647782 # Number of memory barriers committed
system.cpu0.commit.branches 16235143 # Number of branches committed
2016-05-31 12:07:18 +02:00
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
2016-08-12 15:12:59 +02:00
system.cpu0.commit.int_insts 81982870 # Number of committed integer instructions.
system.cpu0.commit.function_calls 1931434 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu0.commit.op_class_0::IntAlu 63005341 66.28% 66.28% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 91123 0.10% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 8017 0.01% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 16761930 17.63% 84.02% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 15193515 15.98% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu0.commit.op_class_0::total 95059926 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1517008 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 223519030 # The number of ROB reads
system.cpu0.rob.rob_writes 207883288 # The number of ROB writes
system.cpu0.timesIdled 136700 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 3867673 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5520543918 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 78894743 # Number of Instructions Simulated
system.cpu0.committedOps 94937874 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.669041 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.669041 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.599147 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.599147 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 110427579 # number of integer regfile reads
system.cpu0.int_regfile_writes 59611828 # number of integer regfile writes
2016-05-31 17:55:47 +02:00
system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads
2016-05-31 12:07:18 +02:00
system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes
2016-08-12 15:12:59 +02:00
system.cpu0.cc_regfile_reads 350340790 # number of cc regfile reads
system.cpu0.cc_regfile_writes 41062621 # number of cc regfile writes
system.cpu0.misc_regfile_reads 252371624 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1225237 # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 711089 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.347987 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 28802334 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 711601 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 40.475398 # Average number of references to valid blocks.
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.347987 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965523 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.965523 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.tags.tag_accesses 63463455 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63463455 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 15558905 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 15558905 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 12019658 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 12019658 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308619 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 308619 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363044 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 363044 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361281 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 361281 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 27578563 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 27578563 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 27887182 # number of overall hits
system.cpu0.dcache.overall_hits::total 27887182 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 648058 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 648058 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1895809 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1895809 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147818 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 147818 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25317 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 25317 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20174 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20174 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2543867 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2543867 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2691685 # number of overall misses
system.cpu0.dcache.overall_misses::total 2691685 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8928091500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 8928091500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29690163364 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 29690163364 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 404195500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 404195500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 475433000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 475433000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 570500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 570500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 38618254864 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 38618254864 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 38618254864 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 38618254864 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 16206963 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 16206963 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 13915467 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 13915467 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456437 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 456437 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388361 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 388361 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381455 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381455 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 30122430 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 30122430 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 30578867 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 30578867 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039986 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.039986 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136238 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.136238 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323852 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323852 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065189 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065189 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052887 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052887 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084451 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.084451 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088024 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.088024 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13776.685883 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13776.685883 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15660.946522 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15660.946522 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15965.378994 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15965.378994 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23566.620402 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23566.620402 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15180.925286 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15180.925286 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14347.241547 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14347.241547 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 1034 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 4271446 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 202383 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.541667 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 21.105755 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 711089 # number of writebacks
system.cpu0.dcache.writebacks::total 711089 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260039 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 260039 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570278 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1570278 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18696 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18696 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830317 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1830317 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830317 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1830317 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388019 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 388019 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325531 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 325531 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101607 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 101607 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6621 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6621 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20174 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20174 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 713550 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 713550 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 815157 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 815157 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20336 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20336 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19032 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19032 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39368 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39368 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4833813000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4833813000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5968230399 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5968230399 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1672759500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1672759500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104692000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104692000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 455274000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 455274000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 555500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 555500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10802043399 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 10802043399 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12474802899 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 12474802899 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534406000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534406000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534406000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534406000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023941 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023941 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023393 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023393 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222609 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222609 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017049 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017049 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052887 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052887 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023688 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023688 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026658 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026658 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12457.670887 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12457.670887 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18333.831184 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18333.831184 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16463.034043 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16463.034043 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15812.112974 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15812.112974 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22567.363934 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22567.363934 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15138.453366 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15138.453366 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15303.558577 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15303.558577 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222974.331235 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222974.331235 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115179.993904 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115179.993904 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1254577 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.762789 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 36189840 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1255088 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 28.834504 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6511134000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762789 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999537 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999537 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 76255085 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 76255085 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 36189843 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 36189843 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 36189843 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 36189843 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 36189843 # number of overall hits
system.cpu0.icache.overall_hits::total 36189843 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1310126 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1310126 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1310126 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1310126 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1310126 # number of overall misses
system.cpu0.icache.overall_misses::total 1310126 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13674177457 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 13674177457 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 13674177457 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 13674177457 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 13674177457 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 13674177457 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 37499969 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 37499969 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 37499969 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 37499969 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 37499969 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 37499969 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034937 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.034937 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034937 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.034937 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034937 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.034937 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10437.299509 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10437.299509 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10437.299509 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10437.299509 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1615389 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 855 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 113956 # number of cycles access was blocked
2016-05-31 17:55:47 +02:00
system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.175550 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 85.500000 # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 1254577 # number of writebacks
system.cpu0.icache.writebacks::total 1254577 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54978 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 54978 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 54978 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 54978 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 54978 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 54978 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1255148 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1255148 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1255148 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1255148 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1255148 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1255148 # number of overall MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12423139434 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 12423139434 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12423139434 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 12423139434 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12423139434 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 12423139434 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033471 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.033471 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.033471 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9897.748659 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9897.748659 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9897.748659 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846782 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1849282 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 2270 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.prefetcher.pfSpanPage 236718 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 273792 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15633.615902 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 1886952 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 289401 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 6.520199 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.tags.occ_blocks::writebacks 14449.190897 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.342760 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.746834 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1171.335411 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.881909 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000753 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071493 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.954200 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 271 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15328 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 120 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 81 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 311 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1438 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7629 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4500 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1450 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.935547 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 67735071 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 67735071 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55557 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13221 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 68778 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 483131 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 483131 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 1451301 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 1451301 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221119 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 221119 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1183848 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1183848 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 387908 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 387908 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55557 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13221 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1183848 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 609027 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1861653 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55557 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13221 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1183848 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 609027 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1861653 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 499 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 185 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 684 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55776 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 55776 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20170 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 20170 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48817 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 48817 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 71252 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 71252 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 108229 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 108229 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 499 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 185 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 71252 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 157046 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 228982 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 499 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 185 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 71252 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 157046 # number of overall misses
system.cpu0.l2cache.overall_misses::total 228982 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14052000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4306000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 18358000 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 37654000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 37654000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9570500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9570500 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 531998 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 531998 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2721932500 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 2721932500 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3344074000 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3344074000 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3294040496 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3294040496 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 14052000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4306000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3344074000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 6015972996 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 9378404996 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 14052000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4306000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3344074000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 6015972996 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 9378404996 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 56056 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13406 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 69462 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 483131 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 483131 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 1451301 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 1451301 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55780 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 55780 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20170 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20170 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269936 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 269936 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1255100 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 1255100 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 496137 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 496137 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 56056 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13406 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1255100 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 766073 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2090635 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 56056 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13406 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1255100 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 766073 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2090635 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008902 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013800 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.009847 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999928 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999928 # miss rate for UpgradeReq accesses
2016-03-16 21:03:49 +01:00
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-05-31 17:55:47 +02:00
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180847 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180847 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056770 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056770 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.218143 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.218143 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008902 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013800 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056770 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.205001 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.109527 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008902 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013800 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056770 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.205001 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.109527 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28160.320641 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23275.675676 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26839.181287 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 675.093230 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 675.093230 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 474.491820 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 474.491820 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 132999.500000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 132999.500000 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55757.881476 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55757.881476 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 46933.054511 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 46933.054511 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30435.839710 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30435.839710 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28160.320641 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23275.675676 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46933.054511 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38307.075608 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 40956.952931 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28160.320641 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23275.675676 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46933.054511 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38307.075608 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 40956.952931 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 33.500000 # average number of cycles each access was blocked
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.unused_prefetches 10619 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 231332 # number of writebacks
system.cpu0.l2cache.writebacks::total 231332 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 4 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5717 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 5717 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 36 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 36 # number of ReadCleanReq MSHR hits
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system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 739 # number of ReadSharedReq MSHR hits
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system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 4 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 36 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6456 # number of demand (read+write) MSHR hits
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system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 36 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6456 # number of overall MSHR hits
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system.cpu0.l2cache.ReadReq_mshr_misses::total 679 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 265620 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 265620 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55776 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55776 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20170 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20170 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43100 # number of ReadExReq MSHR misses
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system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 71216 # number of ReadCleanReq MSHR misses
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system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 71216 # number of demand (read+write) MSHR misses
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system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 71216 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 150590 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 265620 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 488105 # number of overall MSHR misses
2016-04-09 18:13:40 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20336 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23339 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19032 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19032 # number of WriteReq MSHR uncacheable
2016-04-09 18:13:40 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39368 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42371 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11046000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3157500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 14203500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15282370178 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15282370178 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 964881000 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 964881000 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 302897000 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 302897000 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 441998 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 441998 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1759055000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1759055000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2915623000 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2915623000 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2607419996 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2607419996 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 11046000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3157500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2915623000 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4366474996 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 7296301496 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 11046000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3157500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2915623000 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4366474996 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15282370178 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 22578671674 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 246621000 # number of ReadReq MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4371369500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4617990500 # number of ReadReq MSHR uncacheable cycles
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4371369500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4617990500 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009775 # mshr miss rate for ReadReq accesses
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999928 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999928 # mshr miss rate for UpgradeReq accesses
2016-03-16 21:03:49 +01:00
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2016-05-31 17:55:47 +02:00
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159667 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159667 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056741 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216654 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216654 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.106420 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.233472 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20918.262150 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 57534.711912 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17299.214716 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17299.214716 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15017.203768 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15017.203768 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 110499.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 110499.500000 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40813.341067 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40813.341067 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 40940.561110 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24257.326226 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24257.326226 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32794.577145 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46257.816810 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214957.194138 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197865.825442 # average ReadReq mshr uncacheable latency
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111038.648141 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108989.414930 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 4083931 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2062737 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 216422 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 214567 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 102316 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1901889 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 19032 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 19032 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 714747 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 1482534 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 90142 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 335134 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 87548 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42677 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 113494 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 288350 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 285091 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1255148 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586492 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 3253 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3770830 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2574893 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29200 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119227 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 6494150 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160667312 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98708808 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53624 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 224224 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 259653968 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 933771 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 18925704 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 3041721 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.089004 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.286883 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.snoop_fanout::0 2772852 91.16% 91.16% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 267014 8.78% 99.94% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 1855 0.06% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.snoop_fanout::total 3041721 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 4067278494 # Layer occupancy (ticks)
2016-05-31 12:07:18 +02:00
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.snoopLayer0.occupancy 114026414 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer0.occupancy 1886176090 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer1.occupancy 1218391120 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer2.occupancy 15802982 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu0.toL2Bus.respLayer3.occupancy 63205426 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.branchPred.lookups 33853439 # Number of BP lookups
system.cpu1.branchPred.condPredicted 11509465 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 280542 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 18730917 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 5987349 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-08-12 15:12:59 +02:00
system.cpu1.branchPred.BTBHitPct 31.965061 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 12496464 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 7318 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 9007806 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 8970953 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 36853 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 10907 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 21636 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 21636 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8665 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5933 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 7038 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 14598 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 649.780792 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 3376.631612 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 13908 95.27% 95.27% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191 186 1.27% 96.55% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287 234 1.60% 98.15% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383 108 0.74% 98.89% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479 46 0.32% 99.21% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.21% 99.41% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671 8 0.05% 99.47% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 4 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 14598 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 5531 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11435.002712 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10101.039860 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 6336.393968 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 1833 33.14% 33.14% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3041 54.98% 88.12% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 457 8.26% 96.38% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 138 2.50% 98.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 31 0.56% 99.44% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 23 0.42% 99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.walkCompletionTime::total 5531 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 68460974968 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.179525 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.388721 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 68438733968 99.97% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3 17027000 0.02% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5 2383000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7 1817500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9 437500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11 205000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13 153500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15 216500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 68460974968 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1927 75.51% 75.51% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 625 24.49% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2552 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21636 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21636 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2552 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2552 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 24188 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.read_hits 10130487 # DTB read hits
system.cpu1.dtb.read_misses 18672 # DTB read misses
system.cpu1.dtb.write_hits 6476473 # DTB write hits
system.cpu1.dtb.write_misses 2964 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.flush_entries 1961 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 63 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 385 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.perms_faults 370 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 10149159 # DTB read accesses
system.cpu1.dtb.write_accesses 6479437 # DTB write accesses
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-08-12 15:12:59 +02:00
system.cpu1.dtb.hits 16606960 # DTB hits
system.cpu1.dtb.misses 21636 # DTB misses
system.cpu1.dtb.accesses 16628596 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 6064 # Table walker walks requested
system.cpu1.itb.walker.walksShort 6064 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2840 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2623 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 601 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 5463 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 343.950211 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 2166.504505 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-4095 5312 97.24% 97.24% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.04% 98.28% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-12287 43 0.79% 99.07% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-16383 29 0.53% 99.60% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-20479 6 0.11% 99.71% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.09% 99.80% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-32767 5 0.09% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 5463 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1764 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12147.108844 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11115.999882 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5636.944380 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191 277 15.70% 15.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383 1298 73.58% 89.29% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575 111 6.29% 95.58% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767 59 3.34% 98.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.51% 99.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.40% 99.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.11% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1764 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 16901758916 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.861276 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.345783 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 2345411264 13.88% 13.88% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 14555617152 86.12% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 730500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 16901758916 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 989 85.04% 85.04% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 174 14.96% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1163 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6064 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6064 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1163 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1163 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 7227 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 43493383 # ITB inst hits
system.cpu1.itb.inst_misses 6064 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-08-12 15:12:59 +02:00
system.cpu1.itb.flush_entries 1129 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu1.itb.perms_faults 581 # Number of TLB faults due to permissions restrictions
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-08-12 15:12:59 +02:00
system.cpu1.itb.inst_accesses 43499447 # ITB inst accesses
system.cpu1.itb.hits 43493383 # DTB hits
system.cpu1.itb.misses 6064 # DTB misses
system.cpu1.itb.accesses 43499447 # DTB accesses
system.cpu1.numPwrStateTransitions 5513 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 2757 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 1005805033.413856 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 25768715425.209221 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 1955 70.91% 70.91% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.94% 99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 959983620244 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 2757 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 53106605878 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773004477122 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 106214002 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-08-12 15:12:59 +02:00
system.cpu1.fetch.icacheStallCycles 10283907 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 108683336 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 33853439 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 27454766 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 92513470 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3739662 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 81877 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 30058 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 180666 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 303073 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 23077 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 43492215 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 108878 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2205 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 105285959 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.278787 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.339334 # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-08-12 15:12:59 +02:00
system.cpu1.fetch.rateDist::0 48617714 46.18% 46.18% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 13927599 13.23% 59.41% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 7511266 7.13% 66.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 35229380 33.46% 100.00% # Number of instructions fetched each cycle (Total)
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-08-12 15:12:59 +02:00
system.cpu1.fetch.rateDist::total 105285959 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.318729 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.023249 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 13161149 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 62754723 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 26539387 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1087783 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1742917 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 736717 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 129511 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 67619846 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 1094387 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1742917 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 17542611 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2352209 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 57806856 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 23225004 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 2616362 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 54744976 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 213737 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 258070 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 37169 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 15433 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1611507 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 54654605 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 258629758 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 58168286 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 1683 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 52142746 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 2511859 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1875660 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1802517 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 13071586 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 10382439 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6812181 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 622946 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 790955 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 53883918 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 580977 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 53654093 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 93763 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 3608749 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 5111945 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 44050 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 105285959 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.509603 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.847754 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-08-12 15:12:59 +02:00
system.cpu1.iq.issued_per_cycle::0 72150462 68.53% 68.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 16497460 15.67% 84.20% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 13036209 12.38% 96.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3323109 3.16% 99.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 278707 0.26% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-08-12 15:12:59 +02:00
system.cpu1.iq.issued_per_cycle::total 105285959 # Number of insts issued each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-08-12 15:12:59 +02:00
system.cpu1.iq.fu_full::IntAlu 2901953 45.47% 45.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 671 0.01% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.48% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1666030 26.11% 71.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 1813313 28.41% 100.00% # attempts to use FU when none available
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
2016-08-12 15:12:59 +02:00
system.cpu1.iq.FU_type_0::IntAlu 36596131 68.21% 68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 45838 0.09% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 3311 0.01% 68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 10338451 19.27% 87.57% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6670296 12.43% 100.00% # Type of FU issued
2011-08-19 22:08:09 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-08-12 15:12:59 +02:00
system.cpu1.iq.FU_type_0::total 53654093 # Type of FU issued
system.cpu1.iq.rate 0.505151 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 6381967 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.118947 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 219063644 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 58081406 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 51689844 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 6231 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2072 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1788 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 60031897 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 4097 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 89933 # Number of loads that had data forwarded from stores
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-08-12 15:12:59 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 434041 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 639 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 9872 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 275866 # Number of stores squashed
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-08-12 15:12:59 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 52151 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 77961 # Number of times an access to memory failed due to the cache being blocked
2011-08-19 22:08:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-08-12 15:12:59 +02:00
system.cpu1.iew.iewSquashCycles 1742917 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 520776 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 103336 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 54505946 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-08-12 15:12:59 +02:00
system.cpu1.iew.iewDispLoadInsts 10382439 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6812181 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 296650 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 7746 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 89089 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 9872 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 44543 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 120099 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 164642 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 53411917 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 10242028 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 220561 # Number of squashed instructions skipped in execute
2011-08-19 22:08:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
2016-08-12 15:12:59 +02:00
system.cpu1.iew.exec_nop 41051 # number of nop insts executed
system.cpu1.iew.exec_refs 16861277 # number of memory reference insts executed
system.cpu1.iew.exec_branches 11793508 # Number of branches executed
system.cpu1.iew.exec_stores 6619249 # Number of stores executed
system.cpu1.iew.exec_rate 0.502871 # Inst execution rate
system.cpu1.iew.wb_sent 53270244 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 51691632 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 25129407 # num instructions producing a value
system.cpu1.iew.wb_consumers 38339279 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.486674 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.655448 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 3369485 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 536927 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 153628 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 103395222 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.492179 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.152090 # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-08-12 15:12:59 +02:00
system.cpu1.commit.committed_per_cycle::0 77830115 75.27% 75.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 14293086 13.82% 89.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6071280 5.87% 94.97% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 693599 0.67% 95.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1980010 1.91% 97.56% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 1625143 1.57% 99.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 382099 0.37% 99.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 124911 0.12% 99.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 394979 0.38% 100.00% # Number of insts commited each cycle
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-08-12 15:12:59 +02:00
system.cpu1.commit.committed_per_cycle::total 103395222 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 41318794 # Number of instructions committed
system.cpu1.commit.committedOps 50889001 # Number of ops (including micro ops) committed
2011-08-19 22:08:09 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2016-08-12 15:12:59 +02:00
system.cpu1.commit.refs 16484713 # Number of memory references committed
system.cpu1.commit.loads 9948398 # Number of loads committed
system.cpu1.commit.membars 208127 # Number of memory barriers committed
system.cpu1.commit.branches 11637916 # Number of branches committed
2016-05-31 12:07:18 +02:00
system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
2016-08-12 15:12:59 +02:00
system.cpu1.commit.int_insts 45745086 # Number of committed integer instructions.
system.cpu1.commit.function_calls 3368055 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu1.commit.op_class_0::IntAlu 34356210 67.51% 67.51% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 44767 0.09% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 3311 0.01% 67.61% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.61% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.61% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.61% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 9948398 19.55% 87.16% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 6536315 12.84% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu1.commit.op_class_0::total 50889001 # Class of committed instruction
system.cpu1.commit.bw_lim_events 394979 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 137189075 # The number of ROB reads
system.cpu1.rob.rob_writes 110398979 # The number of ROB writes
system.cpu1.timesIdled 58975 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 928043 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5545446856 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 41285938 # Number of Instructions Simulated
system.cpu1.committedOps 50856145 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.572644 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.572644 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.388705 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.388705 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 55995090 # number of integer regfile reads
system.cpu1.int_regfile_writes 35603094 # number of integer regfile writes
2016-05-31 17:55:47 +02:00
system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads
2016-05-31 12:07:18 +02:00
system.cpu1.fp_regfile_writes 516 # number of floating regfile writes
2016-08-12 15:12:59 +02:00
system.cpu1.cc_regfile_reads 190376100 # number of cc regfile reads
system.cpu1.cc_regfile_writes 15518701 # number of cc regfile writes
system.cpu1.misc_regfile_reads 209095836 # number of misc regfile reads
system.cpu1.misc_regfile_writes 386203 # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 187149 # number of replacements
system.cpu1.dcache.tags.tagsinuse 469.748213 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 15687000 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 187502 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 83.663108 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 93899473000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.748213 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917477 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.917477 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 32860265 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 32860265 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 9540081 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 9540081 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 5893568 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 5893568 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48959 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 48959 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77987 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 77987 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70168 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 70168 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 15433649 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 15433649 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 15482608 # number of overall hits
system.cpu1.dcache.overall_hits::total 15482608 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 215586 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 215586 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 396166 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 396166 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30156 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30156 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18335 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 18335 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23429 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23429 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 611752 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 611752 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 641908 # number of overall misses
system.cpu1.dcache.overall_misses::total 641908 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3514528500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3514528500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9742278459 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 9742278459 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360181500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 360181500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551095500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 551095500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 166500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 166500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 13256806959 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 13256806959 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 13256806959 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 13256806959 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755667 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 9755667 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 6289734 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 6289734 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79115 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 79115 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96322 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 96322 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93597 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 93597 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 16045401 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 16045401 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 16124516 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 16124516 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022099 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.022099 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062986 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.062986 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381167 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381167 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190351 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190351 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250318 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250318 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038126 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.038126 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039809 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.039809 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16302.211183 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 16302.211183 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24591.404762 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24591.404762 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19644.477775 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19644.477775 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23521.938623 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23521.938623 # average StoreCondReq miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21670.230680 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 21670.230680 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20652.191527 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20652.191527 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1431753 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 39808 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.210526 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 35.966464 # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 187150 # number of writebacks
system.cpu1.dcache.writebacks::total 187150 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79090 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 79090 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306284 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 306284 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13036 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13036 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 385374 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 385374 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 385374 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 385374 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136496 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 136496 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89882 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 89882 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28741 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 28741 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5299 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5299 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23429 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23429 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 226378 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 226378 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 255119 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 255119 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14517 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14517 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11855 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11855 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26372 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26372 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1963325500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1963325500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2363104967 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2363104967 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488593500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488593500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93065000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93065000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527670500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527670500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 162500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 162500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326430467 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4326430467 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4815023967 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4815023967 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2528366000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2528366000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2528366000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2528366000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013991 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013991 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014290 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014290 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.363281 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.363281 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055013 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055013 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250318 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250318 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014109 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.014109 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015822 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.015822 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14383.758498 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14383.758498 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26291.192530 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26291.192530 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16999.878223 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16999.878223 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17562.747688 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17562.747688 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22522.109352 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22522.109352 # average StoreCondReq mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19111.532335 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19111.532335 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18873.639231 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18873.639231 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174165.874492 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174165.874492 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95873.123009 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95873.123009 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 589510 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.449637 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 42880129 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 590022 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 72.675475 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 79021423000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.449637 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975488 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975488 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu1.icache.tags.tag_accesses 87573930 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 87573930 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 42880129 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 42880129 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 42880129 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 42880129 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 42880129 # number of overall hits
system.cpu1.icache.overall_hits::total 42880129 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 611823 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 611823 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 611823 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 611823 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 611823 # number of overall misses
system.cpu1.icache.overall_misses::total 611823 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5700309356 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5700309356 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5700309356 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5700309356 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5700309356 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5700309356 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 43491952 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 43491952 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 43491952 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 43491952 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 43491952 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 43491952 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014067 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.014067 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014067 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.014067 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014067 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.014067 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9316.925575 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 9316.925575 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 9316.925575 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 9316.925575 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 502398 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 42118 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.928344 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 589510 # number of writebacks
system.cpu1.icache.writebacks::total 589510 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21797 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 21797 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 21797 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 21797 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 21797 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 21797 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 590026 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 590026 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 590026 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 590026 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 590026 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 590026 # number of overall MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5243631193 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5243631193 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5243631193 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5243631193 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5243631193 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5243631193 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8747999 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8747999 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8747999 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 8747999 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013566 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.013566 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.013566 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8887.118861 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86613.851485 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86613.851485 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 195371 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 196016 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 576 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.prefetcher.pfSpanPage 57640 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 44567 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 14592.313259 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 696647 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 58721 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 11.863677 # Average number of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.tags.occ_blocks::writebacks 14188.463877 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.825483 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.061403 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 390.962497 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.865995 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000661 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023862 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.890644 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 294 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13830 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 105 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8625 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3420 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017944 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001831 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.844116 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 27388422 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 27388422 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17107 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6359 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 23466 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 113848 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 113848 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 650456 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 650456 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 26908 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 26908 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 565476 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 565476 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99207 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 99207 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17107 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6359 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 565476 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 126115 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 715057 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17107 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6359 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 565476 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 126115 # number of overall hits
system.cpu1.l2cache.overall_hits::total 715057 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 487 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 295 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 782 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29684 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 29684 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23429 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 23429 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33964 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 33964 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 24548 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 24548 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71313 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 71313 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 487 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 295 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 24548 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 105277 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 130607 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 487 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 295 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 24548 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 105277 # number of overall misses
system.cpu1.l2cache.overall_misses::total 130607 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10682500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6004000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 16686500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13705500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 13705500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 20860500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 20860500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 156500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 156500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1388167997 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1388167997 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 916991000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 916991000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1624894996 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1624894996 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10682500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6004000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 916991000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 3013062993 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 3946740493 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10682500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6004000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 916991000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 3013062993 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 3946740493 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17594 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6654 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 24248 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113848 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 113848 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 650456 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 650456 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29684 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 29684 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23429 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23429 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60872 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 60872 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 590024 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 590024 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 170520 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 170520 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17594 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6654 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 590024 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 231392 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 845664 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17594 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6654 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 590024 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 231392 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 845664 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.027680 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.044334 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.032250 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.557958 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.557958 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.041605 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.041605 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.418209 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.418209 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.027680 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.044334 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.041605 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.454973 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.154443 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.027680 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.044334 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.041605 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.454973 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.154443 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21935.318275 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20352.542373 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21338.235294 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 461.713381 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 461.713381 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 890.370908 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 890.370908 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40871.746467 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40871.746467 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37355.018739 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37355.018739 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22785.396716 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22785.396716 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21935.318275 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20352.542373 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37355.018739 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28620.334859 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30218.445359 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21935.318275 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20352.542373 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37355.018739 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28620.334859 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30218.445359 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 266 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.unused_prefetches 797 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 31759 # number of writebacks
system.cpu1.l2cache.writebacks::total 31759 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 426 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 426 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 74 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 74 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 500 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 500 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 511 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 487 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 293 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 780 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24893 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 24893 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29684 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29684 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23429 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23429 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33538 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 33538 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 24539 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 24539 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71239 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71239 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 487 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 293 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 24539 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104777 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 130096 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 487 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 293 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 24539 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104777 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24893 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 154989 # number of overall MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14517 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14618 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11855 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11855 # number of WriteReq MSHR uncacheable
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26372 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26473 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7760500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4210000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11970500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1022179654 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1022179654 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 459449500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 459449500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 351583000 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 351583000 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 132500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 132500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1131738499 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1131738499 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 769613500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 769613500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1195688496 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1195688496 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7760500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4210000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 769613500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2327426995 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 3109010995 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7760500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4210000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 769613500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2327426995 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1022179654 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 4131190649 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7990000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2412179500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2420169500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7990000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2412179500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2420169500 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032168 # mshr miss rate for ReadReq accesses
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2015-11-06 09:26:50 +01:00
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.550959 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.550959 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041590 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.417775 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.417775 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153839 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for overall accesses
2014-09-20 23:18:53 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183275 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15346.794872 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41062.935524 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15478.018461 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15478.018461 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15006.316958 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15006.316958 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33744.960910 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33744.960910 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31362.871348 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16784.184169 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16784.184169 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23897.821570 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26654.734523 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166162.395812 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165560.918046 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91467.446534 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91420.296151 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 1661462 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 840058 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12360 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 115637 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106952 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8685 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 43235 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 842502 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 11855 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 11855 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 146735 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 662812 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 29649 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 30154 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 72596 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41626 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 86297 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 68185 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 65527 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 590026 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 275295 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 251 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1769762 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885483 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14740 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38125 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2708110 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75491792 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29665722 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26616 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70376 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 105254506 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 347103 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 4899396 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 1195777 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.122893 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.349738 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.snoop_fanout::0 1057509 88.44% 88.44% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 129583 10.84% 99.27% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 8685 0.73% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.snoop_fanout::total 1195777 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 1635737987 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.snoopLayer0.occupancy 81718473 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer0.occupancy 885241795 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer1.occupancy 395391898 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer2.occupancy 8093984 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu1.toL2Bus.respLayer3.occupancy 20543974 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
system.iobus.trans_dist::WriteResp 59421 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer0.occupancy 40381000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer8.occupancy 575500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer23.occupancy 6080500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer24.occupancy 33803000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer25.occupancy 187681355 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.iocache.tags.replacements 36458 # number of replacements
2016-08-12 15:12:59 +02:00
system.iocache.tags.tagsinuse 14.555440 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2016-05-31 17:55:47 +02:00
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.iocache.tags.warmup_cycle 255145986000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.555440 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.909715 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.909715 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-05-31 17:55:47 +02:00
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
2016-08-12 15:12:59 +02:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2016-05-31 17:55:47 +02:00
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-05-31 17:55:47 +02:00
system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36476 # number of overall misses
system.iocache.overall_misses::total 36476 # number of overall misses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_miss_latency::realview.ide 32543877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 32543877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4303510478 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4303510478 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4336054355 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4336054355 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4336054355 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4336054355 # number of overall miss cycles
2016-05-31 17:55:47 +02:00
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 129142.369048 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129142.369048 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118802.740669 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118802.740669 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118874.173566 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118874.173566 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-07-21 18:19:18 +02:00
system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
2016-05-31 17:55:47 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2016-05-31 17:55:47 +02:00
system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 19943877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 19943877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489987873 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2489987873 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2509931750 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2509931750 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2509931750 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2509931750 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79142.369048 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 79142.369048 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68738.622819 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68738.622819 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 136926 # number of replacements
system.l2c.tags.tagsinuse 65153.135165 # Cycle average of tags in use
system.l2c.tags.total_refs 554455 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 202299 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.740770 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 87124800000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 6156.009081 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.876446 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 1.073086 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 8059.392106 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 7027.702710 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37061.403814 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.474451 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906071 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1853.985065 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2995.751440 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1972.560896 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.093933 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000273 # Average percentage of cache occupancy
2016-05-31 12:07:18 +02:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.l2c.tags.occ_percent::cpu0.inst 0.122977 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.107234 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.565512 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000099 # Average percentage of cache occupancy
2016-03-16 21:03:49 +01:00
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.l2c.tags.occ_percent::cpu1.inst 0.028290 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.045712 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030099 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.994158 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 33193 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 32156 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 172 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 5974 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 27047 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4634 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 27347 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.506485 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.490662 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 6339538 # Number of tag accesses
system.l2c.tags.data_accesses 6339538 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 263091 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 263091 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 41407 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4842 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 46249 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2692 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 2122 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 4814 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 3983 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1501 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5484 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 230 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 51619 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 58109 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47216 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 63 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 17 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 21642 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 11731 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5163 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 195876 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 230 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 51619 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 62092 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 47216 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 63 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 17 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 21642 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 13232 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 5163 # number of demand (read+write) hits
system.l2c.demand_hits::total 201360 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 230 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits
system.l2c.overall_hits::cpu0.inst 51619 # number of overall hits
system.l2c.overall_hits::cpu0.data 62092 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 47216 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 63 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 17 # number of overall hits
system.l2c.overall_hits::cpu1.inst 21642 # number of overall hits
system.l2c.overall_hits::cpu1.data 13232 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 5163 # number of overall hits
system.l2c.overall_hits::total 201360 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 609 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 555 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1164 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 50 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 135 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 185 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 11314 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8283 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 19597 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 30 # number of ReadSharedReq misses
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_misses::cpu0.inst 19597 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 9392 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131482 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 8 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 2894 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 1084 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6503 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 170994 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 30 # number of demand (read+write) misses
2016-05-31 12:07:18 +02:00
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
2016-08-12 15:12:59 +02:00
system.l2c.demand_misses::cpu0.inst 19597 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 20706 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 131482 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2894 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 9367 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 6503 # number of demand (read+write) misses
system.l2c.demand_misses::total 190591 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 30 # number of overall misses
2016-05-31 12:07:18 +02:00
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_misses::cpu0.inst 19597 # number of overall misses
system.l2c.overall_misses::cpu0.data 20706 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 131482 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2894 # number of overall misses
system.l2c.overall_misses::cpu1.data 9367 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 6503 # number of overall misses
system.l2c.overall_misses::total 190591 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 8863500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 1613000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 10476500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 750000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 250000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 1000000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1173434500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 698306000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1871740500 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2901000 # number of ReadSharedReq miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 241000 # number of ReadSharedReq miss cycles
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1645029500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 865429500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14426700203 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 699000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 83500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 247656000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 98290000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 907627854 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 18194657557 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 2901000 # number of demand (read+write) miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.demand_miss_latency::cpu0.itb.walker 241000 # number of demand (read+write) miss cycles
2016-08-12 15:12:59 +02:00
system.l2c.demand_miss_latency::cpu0.inst 1645029500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 2038864000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14426700203 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 699000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 247656000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 796596000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 907627854 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 20066398057 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 2901000 # number of overall miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.overall_miss_latency::cpu0.itb.walker 241000 # number of overall miss cycles
2016-08-12 15:12:59 +02:00
system.l2c.overall_miss_latency::cpu0.inst 1645029500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 2038864000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14426700203 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 699000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 247656000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 796596000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 907627854 # number of overall miss cycles
system.l2c.overall_miss_latency::total 20066398057 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 263091 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 263091 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 42016 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5397 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 47413 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 2742 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 2257 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 4999 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 15297 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 9784 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 25081 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 260 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 89 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 71216 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 67501 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 178698 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 71 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 24536 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 12815 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11666 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 366870 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 260 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 89 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 71216 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 82798 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 178698 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 71 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 24536 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 22599 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11666 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 391951 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 260 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 89 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 71216 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 82798 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 178698 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 71 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 24536 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 22599 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11666 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 391951 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.014494 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.102835 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.024550 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018235 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.059814 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.037007 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.739622 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.846586 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.781348 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.033708 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.275177 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.139139 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.735778 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.112676 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.055556 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.117949 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.084588 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.557432 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.466089 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.033708 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.275177 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.250079 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.735778 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.112676 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.055556 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.117949 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.414487 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.557432 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.486262 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.115385 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.033708 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.275177 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.250079 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.735778 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.112676 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.055556 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.117949 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.414487 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.557432 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.486262 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14554.187192 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2906.306306 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 9000.429553 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15000 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1851.851852 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 5405.405405 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103715.264274 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84305.927804 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 95511.583406 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 96700 # average ReadSharedReq miss latency
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333 # average ReadSharedReq miss latency
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83942.924937 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 92145.389693 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 87375 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 83500 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85575.673808 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90673.431734 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 106405.239698 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96700 # average overall miss latency
2016-05-31 12:07:18 +02:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency
2016-08-12 15:12:59 +02:00
system.l2c.demand_avg_miss_latency::cpu0.inst 83942.924937 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 98467.304163 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87375 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 85575.673808 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 85042.809864 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 105285.129188 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96700 # average overall miss latency
2016-05-31 12:07:18 +02:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency
2016-08-12 15:12:59 +02:00
system.l2c.overall_avg_miss_latency::cpu0.inst 83942.924937 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 98467.304163 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109723.766014 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87375 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 85575.673808 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 85042.809864 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 139570.637244 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 105285.129188 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 188 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 37.600000 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.l2c.writebacks::writebacks 101215 # number of writebacks
system.l2c.writebacks::total 101215 # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 2 # number of ReadSharedReq MSHR hits
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system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 4 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 4022 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 4022 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 609 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 555 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 1164 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 50 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 135 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 185 # number of SCUpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses::cpu1.data 8283 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 19597 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 30 # number of ReadSharedReq MSHR misses
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19595 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9392 # number of ReadSharedReq MSHR misses
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system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2892 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1084 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6503 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 170990 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 30 # number of demand (read+write) MSHR misses
2016-05-31 12:07:18 +02:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses
2016-08-12 15:12:59 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 19595 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 20706 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131482 # number of demand (read+write) MSHR misses
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system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2892 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 9367 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6503 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 190587 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 30 # number of overall MSHR misses
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 19595 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 20706 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu1.inst 2892 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 9367 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::total 190587 # number of overall MSHR misses
2016-04-09 18:13:40 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20336 # number of ReadReq MSHR uncacheable
2016-07-21 18:19:18 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14514 # number of ReadReq MSHR uncacheable
2016-07-21 18:19:18 +02:00
system.l2c.ReadReq_mshr_uncacheable::total 37954 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19032 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11855 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 30887 # number of WriteReq MSHR uncacheable
2016-04-09 18:13:40 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39368 # number of overall MSHR uncacheable misses
2016-07-21 18:19:18 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26369 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 68841 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14170000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 12236500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 26406500 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1349500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3214500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 4564000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1060294500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 615476000 # number of ReadExReq MSHR miss cycles
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system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2601000 # number of ReadSharedReq MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 211000 # number of ReadSharedReq MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1448949504 # number of ReadSharedReq MSHR miss cycles
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system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13111874714 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 619000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 73500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 218669000 # number of ReadSharedReq MSHR miss cycles
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system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 842596357 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 16484553076 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2601000 # number of demand (read+write) MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 211000 # number of demand (read+write) MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 1448949504 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13111874714 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 619000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 218669000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 702926000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 842596357 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 18160323576 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2601000 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 211000 # number of overall MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 1448949504 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 1831803501 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 619000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 218669000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 702926000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 842596357 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 18160323576 # number of overall MSHR miss cycles
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 192566500 # number of ReadReq MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4005299000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6171000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2150864000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6354900500 # number of ReadReq MSHR uncacheable cycles
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 192566500 # number of overall MSHR uncacheable cycles
2016-08-12 15:12:59 +02:00
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system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6171000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2150864000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6354900500 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-08-12 15:12:59 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014494 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.102835 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.024550 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018235 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.059814 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.037007 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739622 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.846586 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.781348 # mshr miss rate for ReadExReq accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.139139 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.084588 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.466078 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.250079 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.414487 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.486252 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.250079 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.414487 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.486252 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23267.651888 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22047.747748 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22685.996564 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26990 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23811.111111 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24670.270270 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93715.264274 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74305.927804 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 85511.583406 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average ReadSharedReq mshr miss latency
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82145.336563 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80673.431734 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96406.532990 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency
2016-08-12 15:12:59 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency
2016-08-12 15:12:59 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196956.087726 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148192.365991 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167436.910471 # average ReadReq mshr uncacheable latency
2016-05-31 12:07:18 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency
2016-08-12 15:12:59 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101739.966470 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81567.901703 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92312.727880 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 505464 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 284514 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2016-05-31 17:55:47 +02:00
system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-05-31 12:07:18 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::ReadReq 37954 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::ReadResp 209195 # Transaction distribution
system.membus.trans_dist::WriteReq 30887 # Transaction distribution
system.membus.trans_dist::WriteResp 30887 # Transaction distribution
system.membus.trans_dist::WritebackDirty 137421 # Transaction distribution
system.membus.trans_dist::CleanEvict 16935 # Transaction distribution
system.membus.trans_dist::UpgradeReq 65286 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 38770 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 39566 # Transaction distribution
system.membus.trans_dist::ReadExResp 19573 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 171242 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13620 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638853 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 760423 # Packet count per connected master and slave (bytes)
2016-05-31 17:55:47 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_count::total 833372 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
2016-04-09 18:13:40 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18721784 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18912106 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_size::total 21230250 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 123250 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 36480 # Total snoop traffic (bytes)
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::samples 419934 # Request fanout histogram
system.membus.snoop_fanout::mean 0.012350 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.110440 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::0 414748 98.77% 98.77% # Request fanout histogram
system.membus.snoop_fanout::1 5186 1.23% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::total 419934 # Request fanout histogram
system.membus.reqLayer0.occupancy 81570000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer2.occupancy 11357000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer5.occupancy 987545766 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer2.occupancy 1099710840 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer3.occupancy 1385881 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-08-12 15:12:59 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 1051858 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 557134 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 188416 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 28173 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 27109 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 1064 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states
2016-07-21 18:19:18 +02:00
system.toL2Bus.trans_dist::ReadReq 37957 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.toL2Bus.trans_dist::ReadResp 525508 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30887 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30887 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 364306 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 131438 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 111511 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 43584 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 155095 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 50612 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 50612 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 487554 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1267106 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 367019 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1634125 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36291756 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5905726 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 42197482 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 390713 # Total snoops (count)
system.toL2Bus.snoopTraffic 15836620 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 903686 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.404217 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.493133 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.toL2Bus.snoop_fanout::0 539465 59.70% 59.70% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 363157 40.19% 99.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 1064 0.12% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.toL2Bus.snoop_fanout::total 903686 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 901600874 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 17:55:47 +02:00
system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.toL2Bus.respLayer0.occupancy 679704118 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.toL2Bus.respLayer1.occupancy 260937433 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2011-08-19 22:08:09 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-08-12 15:12:59 +02:00
system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-08-12 15:12:59 +02:00
system.cpu1.kern.inst.quiesce 2757 # number of quiesce instructions executed
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
