Commit graph

5062 commits

Author SHA1 Message Date
Ali Saidi
649c239cee LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-13 12:58:08 -04:00
Deyuan Guo
bb921b1459 MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote
debugging.

Testing:

Build gem5 for MIPS_SE and make gem5 wait at beginning:
modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc;
scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU
----
Build GDB-7.3 mips-cross:
./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/
make
make install
----
Run:
./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches
./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello
(gdb) target remote :7000
(gdb) info registers
(gdb) disassemble
(gdb) si
(gdb) break main
(gdb) c
(gdb) quit
Testing done.
2011-09-10 03:45:25 -07:00
Gabe Black
6a2b223112 PseudoInst: Add compiler guards to pseudo_inst.hh. 2011-09-10 02:31:15 -07:00
Gabe Black
49a7ed0397 StaticInst: Merge StaticInst and StaticInstBase.
Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
2011-09-09 02:40:11 -07:00
Gabe Black
b7b545bc38 Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
2011-09-09 02:30:01 -07:00
Gabe Black
a1ad9e652a Stack: Tidy up some comments, a warning, and make stack extension consistent.
Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
2011-09-09 01:01:43 -07:00
Gabe Black
f370ac5c18 ISA parser: Don't look for operands in strings. 2011-09-08 03:21:14 -07:00
Gabe Black
f4dc64655f ISA parser: Match /* */ and // style comments.
Comments should not be scanned for operands, and we should look for both /* */
style and // style.
2011-09-08 03:20:05 -07:00
Gabe Black
87d687e242 X86: Make sure instruction flags are set properly even on 32 bit machines.
The way flag bits were being set for microops in x86 ended up implicitly
calling the bitset constructor which was truncating flags beyond the width of
an unsigned long. This change sets the bits in chunks which are always small
enough to avoid being truncated. On 64 bit machines this should reduce to be
the same as before, and on 32 bit machines it should work properly and not be
unreasonably inefficient.
2011-09-05 18:36:26 -07:00
Gabe Black
3bd0b9654c X86,TLB: Make sure the "delayedResponse" variable is always set.
When an instruction is translated in the x86 TLB, a variable called
delayedResponse is passed back and forth which tracks whether a translation
could be completed immediately, or if there's going to be callback that will
finish things up. If a read was to the internal memory space, memory mapped
registers used to implement things like MSRs, the function hadn't yet gotten
to where delayedResponse was set to false, it's default. That meant that the
value was never set, and the TLB could start waiting for a callback that would
never come. This change simply moves the assignment to above where control
can divert to translateInt().
2011-09-05 02:48:57 -07:00
Lisa Hsu
365966304e TLB: comments and a helpful warning.
Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why.  Add a little warn() to explain it a bit.  Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage().
2011-09-02 17:04:00 -07:00
Lisa Hsu
f6a2ef22ff Fix build for gcc-4.2 opt/fast
Even though the code is safe, compiler flags a warning here, which are treated as errors for fast/opt. I know it's redundant but it has no side effects and fixes the compile.
2011-09-01 15:25:54 -07:00
Lisa Hsu
ae12ae3023 Functional Accesses: Update states to support Broadcast/Snooping protocols.
In the current implementation of Functional Accesses, it's very hard to
implement broadcast or snooping protocols where the memory has no idea if it
has exclusive access to a cache block or not. Without this knowledge, making
sure the RW vs. RO permissions are right are next to impossible. So we add a
new state called Backing_Store to enable the conveyance that this is the backup
storage for a block, so that it can be written if it is the only possibly RW
block in the system, or written even if there is another RW block in the
system, without causing problems.

Also, a small change to actually set the m_name field for each Controller so
that debugging can be easier. Now you can access a controller's name just by
controller->getName().
2011-09-01 11:41:44 -07:00
Nilay Vaish
ebda5c14a5 SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.
2011-08-29 06:34:40 -05:00
Nilay Vaish
1bbca50491 Ruby: Remove some unused code 2011-08-29 05:10:23 -05:00
Nilay Vaish
a08cc94936 Ruby: Eliminate modulo op for computing set size. 2011-08-26 12:27:58 -05:00
Ali Saidi
c9d5985b82 ARM: Mark some variables uncacheable until boot all CPUs are enabled.
There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).
2011-08-19 15:08:08 -05:00
Ali Saidi
c9c2d979b8 Mem: Put prefetcher notify call before packet is deleted. 2011-08-19 15:08:08 -05:00
Ali Saidi
2fd2b44b86 ARM: Add VExpress_E support with PCIe to gem5 2011-08-19 15:08:08 -05:00
Ali Saidi
d2a0a2ec22 ARM: Add support for Versatile Express boards 2011-08-19 15:08:08 -05:00
Ali Saidi
23755eb434 ARM: Make GIC function that should only be called by GIC protected. 2011-08-19 15:08:08 -05:00
Ali Saidi
243223ae63 IDE: Fix issues with new PIIX kernel driver and our model.
The driver can read the IDE config register as a 32 bit register since
some adapters use bit 18 as a disable channel bit. If the size isn't
set in a PRD it should be 64K according to the SPEC (and driver) not
128K.
2011-08-19 15:08:08 -05:00
Ali Saidi
b94f841969 ARM: Add support for DIV/SDIV instructions. 2011-08-19 15:08:07 -05:00
Ali Saidi
b6203360ef LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
This patch improves performance by as much as 10% on some spec benchmarks.
2011-08-19 15:08:07 -05:00
Geoffrey Blake
5f425b8bd1 Fix bugs due to interaction between SEV instructions and O3 pipeline
SEV instructions were originally implemented to cause asynchronous squashes
via the generateTCSquash() function in the O3 pipeline when updating the
SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system
that would lead to a pipeline either going inactive indefinitely or not being
able to commit squashed instructions. Fixed SEV instructions to behave like
interrupts and cause synchronous sqaushes inside the pipeline, eliminating
the race conditions. Also fixed up the semantics of the WFE instruction to
behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1
or unmasked interrupts are pending.
2011-08-19 15:08:07 -05:00
Mrinmoy Ghosh
d0e0485902 LSQ: Add some better dprintfs for storeset predictor. 2011-08-19 15:08:05 -05:00
Mrinmoy Ghosh
0db95030fc LSQ: Fix a few issues with the storeset predictor.
Two issues are fixed in this patch:
1. The load and store pc passed to the predictor are passed in reverse order.
2. The flag indicating that a barrier is inflight was never cleared when
   the barrier was squashed instead of committed. This made all load insts
   dependent on a non-existent barrier in-flight.
2011-08-19 15:08:05 -05:00
Thomas Grass
3f1ae35c6d Stats: Add a sparse histogram stat object. 2011-08-19 15:08:05 -05:00
Giacomo Gabrielli
676a530b77 O3: Squash the violator and younger instructions instead not all insts.
Change the way instructions are squashed on memory ordering violations
to squash the violator and younger instructions, not all instructions
that are younger than the instruction they violated (no reason to throw
away valid work).
2011-08-19 15:08:05 -05:00
Geoffrey Blake
f778c46b5e ARM: Add per-cpu local timers for ARM.
Cortex-A9 processors can have a local timer and watchdog counter. It
is enabled by default in Linux and up to this point we've had to disable
them since a model wasn't available. This change allows a default
MP ARM Linux configuration to boot.
2011-08-19 15:08:05 -05:00
Prakash Ramrakhani
efd91d2237 ARM: Add per-processor interrupt support to GIC. 2011-08-19 15:08:05 -05:00
Ali Saidi
9b356adf54 ARM: Fix a memory leak with the table walker. 2011-08-19 15:08:05 -05:00
Ali Saidi
6779bd3e5d Prefetcher: Fix some memory leaks with the prefetcher. 2011-08-19 15:08:05 -05:00
Ali Saidi
b3a058f220 ARM: quiet what can be a very noise CLCD controller. 2011-08-19 15:08:05 -05:00
Gabe Black
f2c89a01d1 InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively. 2011-08-16 02:47:15 -07:00
Gabe Black
78a4636a13 O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively. 2011-08-16 02:46:57 -07:00
Nilay Vaish
769c1844f0 Ruby: Initialize some variables. 2011-08-15 12:56:47 -05:00
Gabe Black
0e6dc00497 O3: When squashing, restore the macroop that should be used for fetching. 2011-08-14 17:41:34 -07:00
Gabe Black
ec204f003c O3: Add a pointer to the macroop for a microop in the dyninst. 2011-08-14 04:08:14 -07:00
Gabe Black
1b9de61a71 X86: Use IsSquashAfter if an instruction could affect fetch translation.
Control register operands are set up so that writing to them is serialize
after, serialize before, and non-speculative. These are probably overboard,
but they should usually be safe. Unfortunately there are times when even these
aren't enough. If an instruction modifies state that affects fetch, later
serialized instructions which come after it might have already gone through
fetch and decode by the time it commits. These instructions may have been
translated incorrectly or interpretted incorrectly and need to be destroyed.
This change modifies instructions which will or may have this behavior so that
they use the IsSquashAfter flag when necessary.
2011-08-13 23:03:11 -07:00
Gabe Black
e0043f8dbe O3: At the end of an instruction, force fetchAddr to something sensible.
It's possible (though until now very unlikely) for fetchAddr to get out of
sync with the actual PC of the current instruction. This change forcefull
resets fetchAddr at the end of every instruction.
2011-08-13 13:36:37 -07:00
Gabe Black
96df6bedb7 O3: Stop using the current macroop no matter why you're leaving it.
Until now, the only reason a macroop would be left was because it ended at a
microop marked as the last microop. In O3 with branch prediction, it's
possible for the branch predictor to have entries which originally came from
different instructions which happened to have the same RIP. This could
theoretically happen in many ways, but it was encountered specifically when
different programs in different address spaces ran one after the other in
X86_FS.

What would happen in that case was that the macroop would continue to be
looped over and microops fetched from it until it reached the last microop
even though the macropc had moved out from under it. If things lined up
properly, this could mean that the end bytes of an instruction actually fell
into the instruction sized block of memory after the one in the predecoder.
The fetch loop implicitly assumes that the last instruction sized chunk of
memory processed was the last one needed for the instruction it just finished
executing. It would then tell the predecoder to move to an offset within the
bytes it was given that is larger than those bytes, and that would trip an
assert in the x86 predecoder.

This change fixes this problem by making fetch stop processing the current
macroop if the address it should be fetching from changed when the PC is
updated. That happens when the last microop was reached because the instruction
handled it properly, and it also catches the case where the branch predictor
makes fetch do a macro level branch when it shouldn't.

The check of isLastMicroop is retained because otherwise, a macroop that
branches back to itself would act like a single, long macroop instead of
multiple instances of the same microop. There may be situations (which may
turn out to be purely hypothetical) where that matters.

This also fixes a relatively minor issue where the curMacroop variable would
be set to NULL immediately after seeing that a microop was the last one before
curMacroop was used to build the dyninst. The traceData structure would have a
NULL pointer to the macroop for that microop.
2011-08-09 11:30:43 -07:00
Gabe Black
3989f41261 O3: When waiting to handle an interrupt, let everything drain out.
Before this change, the commit stage would wait until the ROB and store queue
were empty before recognizing an interrupt. The fetch stage would stop
generating instructions at an appropriate point, so commit would then wait
until a valid time to interrupt the instruction stream. Instructions might be
in flight after fetch but not the in the ROB or store queue (in rename, for
instance), so this change makes commit wait until all in flight instructions
are finished.
2011-08-09 03:37:43 -07:00
Nilay Vaish
821dfc1289 BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
2011-08-08 10:50:13 -05:00
Gabe Black
5c0e6e6092 O3: Get rid of the unused addToRemoveList function. 2011-08-07 15:41:10 -07:00
Gabe Black
a9b7931156 O3: Let squashed and deferred instructions issue.
Let squahsed and deferred instructions issue so they don't accumulate and clog
up the CPU.
2011-08-07 15:41:07 -07:00
Ali Saidi
4d83b8a799 O3: Fix uninitialized variable in the tournament branch predictor. 2011-08-07 09:21:49 -07:00
Gabe Black
16882b0483 Translation: Use a pointer type as the template argument.
This allows regular pointers and reference counted pointers without having to
use any shim structures or other tricks.
2011-08-07 09:21:48 -07:00
Nilay Vaish
720c0be620 Ruby: Remove files and includes not in use 2011-08-03 18:25:30 -05:00
Gabe Black
6230668f5e O3: Get rid of the raw ExtMachInst constructor on DynInsts.
This constructor assumes that the ExtMachInst can be decoded directly into a
StaticInst that's useful to execute. With the advent of microcoded
instructions that's no longer true.
2011-08-02 11:51:16 -07:00
Gabe Black
1c68c32cc9 Scons: Make some Action objects fit the abreviated output format. 2011-08-02 03:22:11 -07:00
Nilay Vaish
1b49c56679 Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
2011-08-02 00:10:08 -05:00
Gabe Black
206c2e9a0e O3: Implement memory mapped IPRs for O3. 2011-07-31 19:21:17 -07:00
Gabe Black
a42c6ae48d O3: Fix corner case squashing into the microcode ROM.
When fetching from the microcode ROM, if the PC is set so that it isn't in the
cache block that's been fetched the CPU will get stuck. The fetch stage
notices that it's in the ROM so it doesn't try to fetch from the current PC.
It then later notices that it's outside of the current cache block so it skips
generating instructions expecting to continue once the right bytes have been
fetched. This change lets the fetch stage attempt to generate instructions,
and only checks if the bytes it's going to use are valid if it's really going
to use them.
2011-07-30 23:22:53 -07:00
Nilay Vaish
b4152e250d SLICC: Put functions of a controller in its .cc file
Currently, functions associated with a controller go into separate files.
This patch puts all the functions in the controller's .cc file. This should
hopefully take away some time from compilation.
2011-07-27 20:20:53 -05:00
Ali Saidi
147095cb08 Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
Prefetch requests issued from the L2 or below wouldn't check if valid data is
present higher in the system. If a prefetch into the L2 occured at the same
time as writeback from a higher-level cache the dirty data could be replaced
in by unmodified data in memory.
2011-07-15 11:53:35 -05:00
Giacomo Gabrielli
69ef57fd0f O3: Create a pipeline activity viewer for the O3 CPU model.
Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
2011-07-15 11:53:35 -05:00
Wade Walker
8870a5820a ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
2011-07-15 11:53:34 -05:00
Wade Walker
e6672d1f29 ARM: Add two unimplemented miscellaneous registers.
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
2011-07-15 11:53:34 -05:00
Nilay Vaish
dbde1502cd X86: implements copyRegs() function
This patch implements the copyRegs() function for the x86 architecture.
The patch assumes that no side effects other than TLB invalidation need
to be considered while copying the registers. This may not hold true in
future.
2011-07-11 16:52:52 -05:00
Gabe Black
a7dcd19fa0 ISA: Get rid of the unused mem_acc_type template parameter. 2011-07-11 04:47:06 -07:00
Mrinmoy Ghosh
3396fd9e84 Branch predictor: Fixes the tournament branch predictor.
Branch predictor could not predict a branch in a nested loop because:
 1. The global history was not updated after a mispredict squash.
 2. The global history was updated in the fetch stage. The choice predictors
    that were updated  used the changed global history. This is incorrect, as
    it incorporates the state of global history after the branch in
    encountered. Fixed update to choice predictor using the global history
    state before the branch happened.
 3. The global predictor table was also updated using the global history state
    before the branch happened as above.

Additionally, parameters to initialize ctr and history size were reversed.
2011-07-10 12:56:08 -05:00
Geoffrey Blake
c7e7b89058 O3: Fix up pipelining icache accesses in fetch stage to function properly
Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to
icache to work with recent changes to main repository.
Also added in ability for fetch stage to delay issuing the fault carrying
nop when a pipeline fetch causes a fault and no fetch bandwidth is available
until the next cycle.
2011-07-10 12:56:08 -05:00
Ali Saidi
f8538f7456 IO: Handle case where ISA Fake device is being used as a fake memory. 2011-07-10 12:56:08 -05:00
Ali Saidi
60579e8d74 O3: Make sure fetch doesn't go off into the weeds during speculation. 2011-07-10 12:56:08 -05:00
Ali Saidi
9751a1d3e7 Config: Add support for a Self.all proxy object 2011-07-10 12:56:08 -05:00
Daniel Johnson
83f91db2cc ARM: Fix mp interrupt bug in GIC.
Missing "!" made multiprocessor interrupts operate incorrectly.
2011-07-10 12:56:08 -05:00
Korey Sewell
678376f0ba alpha:hwrei:rollback for o3
change hwrei back to being a non-control instruction so O3-FS mode will work
add squash in inorder that will catch a hwrei (or any other genric instruction)
that isnt a control inst but changes the PC. Additional testing still needs to be done
for inorder-FS mode but this change will free O3 development back up in the interim
2011-07-07 21:32:49 -04:00
Brad Beckmann
255f82a783 ruby: added generic dma machine 2011-07-06 18:45:15 -07:00
Brad Beckmann
4f83390781 MOESI_hammer: Fixed uniprocessor DMA bug 2011-07-06 18:44:42 -07:00
Nathan Binkert
da1eaaca0e slicc: add a protocol statement and an include statement
All protocols must specify their name
The include statement allows any file to include another file.
2011-07-05 18:30:05 -07:00
Nathan Binkert
831e9b3b7a slicc: cleanup slicc code and make it less verbose 2011-07-05 18:30:05 -07:00
Nathan Binkert
3d252f8e5f grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently.  This makes implementing an include statement as part
of a grammar possible.
2011-07-05 18:30:04 -07:00
Gabe Black
87b657278d ISAs: Streamline some spots where Mem is used in the ISA descriptions. 2011-07-05 16:52:57 -07:00
Gabe Black
63a934d152 ISA parser: Define operand types with a ctype directly. 2011-07-05 16:52:15 -07:00
Gabe Black
f16179eb21 ISA parser: Simplify operand type handling.
This change simplifies the code surrounding operand type handling and makes it
depend only on the ctype that goes with each operand type. Future changes will
allow defining operand types by their ctypes directly, convert the ISAs over
to that style of definition, and then remove support for the old style. These
changes are to make it easier to use non-builtin types like classes or
structures as the type for operands.
2011-07-05 16:48:18 -07:00
Nilay Vaish
9b85b4b19a Merged with Gabe's recent changes. 2011-07-03 11:38:25 -05:00
Nilay Vaish
5e0851d554 Network_test: Conform it with functional access changes in Ruby
Addition of functional access support to Ruby necessitated some changes to
the way coherence protocols are written. I had forgotten to update the
Network_test protocol. This patch makes those updates.
2011-07-03 11:33:46 -05:00
Gabe Black
3a1428365a ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
2011-07-02 22:35:04 -07:00
Gabe Black
2e7426664a ExecContext: Get rid of the now unused read/write templated functions. 2011-07-02 22:34:58 -07:00
Gabe Black
aade13769f ISA: Use readBytes/writeBytes for all instruction level memory operations. 2011-07-02 22:34:29 -07:00
Gabe Black
2f72d6a1f4 X86: Fix store microops so they don't drop faults in timing mode.
If a fault was returned by the CPU when a store initiated it's write, the
store instruction would ignore the fault. This change fixes that.
2011-07-02 22:31:22 -07:00
Nilay Vaish
45b411fc5f Ruby: Commit files missing from previous commit
The previous commit on functional access support in Ruby did not have
some of the files required. This patch adds those files to the repository.
2011-07-01 16:29:33 -05:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
c86f849d5a Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
2011-06-30 19:49:26 -05:00
Nilay Vaish
f4cfd65d29 arch: print next upc correctly
The patch corrects the print statement which prints the current and
the next pc. Instead of the next upc, the next pc was being printed.
2011-06-28 18:27:38 -05:00
Joel Hestness
d50aec8d9a Ruby: remove unused functions in CacheMemory: get/setMemoryValue 2011-06-24 15:47:35 -05:00
Deyaun Guo
5aaddc129e mips: fix nmsub and nmadd definitions
the -/+ signs were flipped for nmsub_s, nmsub_d, and nmadd_d
2011-06-22 23:35:21 -04:00
Gabe Black
efb9f7c2ae X86: Eliminate an unused argument for building store microops. 2011-06-21 19:28:14 -07:00
Gabe Black
affad29932 InOder: Fix a compile error. 2011-06-20 02:29:14 -07:00
Korey Sewell
477e7039b3 inorder: clear reg. dep entry after removing from list
this will safeguard future code from trying to remove
from the list twice. That code wouldnt break but would
waste time.
2011-06-19 21:43:42 -04:00
Korey Sewell
b963b339b9 inorder: se: squash after syscalls 2011-06-19 21:43:42 -04:00
Korey Sewell
eedd04e894 inorder: cleanup dprintfs in cache unit 2011-06-19 21:43:42 -04:00
Korey Sewell
078f914e69 inorder: SE mode TLB faults
handle them like we do in FS mode, by blocking the TLB until the fault
is handled by the fault->invoke()
2011-06-19 21:43:42 -04:00
Korey Sewell
3cb23bd3a2 inorder:tracing: fix fault tracing bug 2011-06-19 21:43:42 -04:00
Korey Sewell
fe3a2aa4a3 inorder: se compile fixes 2011-06-19 21:43:42 -04:00
Korey Sewell
e572c01120 inorder: add necessary debug flag header files 2011-06-19 21:43:41 -04:00
Korey Sewell
59686795e3 mips: mark unaligned access flag as true 2011-06-19 21:43:41 -04:00
Korey Sewell
91a88ae8ce inorder: clear fetchbuffer on traps
implement clearfetchbufferfunction
extend predecoder to use multiple threads and clear those on trap
2011-06-19 21:43:41 -04:00
Korey Sewell
2dae0e8735 inorder: use separate float-reg bits function in dyninst
this will make sure we get the correct view of a FP register
2011-06-19 21:43:41 -04:00
Korey Sewell
8c0def8d03 inorder: use trapPending flag to manage traps 2011-06-19 21:43:41 -04:00
Korey Sewell
5ef0b7a9db inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
2011-06-19 21:43:41 -04:00
Korey Sewell
716e447da8 inorder: handle serializing instructions
including IPR accesses and store-conditionals. These class of instructions will not
execute correctly in a superscalar machine
2011-06-19 21:43:41 -04:00
Korey Sewell
83a0fd24f7 alpha: fix warn_once for prefetches 2011-06-19 21:43:40 -04:00
Korey Sewell
33a6020f2e alpha: naming for dtb faults
Just "dfault" gets confusing while debugging. Why not
differentiate whether it's an access violation or page
fault
2011-06-19 21:43:40 -04:00
Korey Sewell
561c33f082 inorder: dont handle multiple faults on same cycle
if a faulting instruction reaches an execution unit,
then ignore it and pass it through the pipeline.

Once we recognize the fault in the graduation unit,
dont allow a second fault to creep in on the same cycle.
2011-06-19 21:43:40 -04:00
Korey Sewell
c4deabfb97 inorder: register ports for FS mode
handle "snoop" port registration as well as functional
port setup for FS mode
2011-06-19 21:43:40 -04:00
Korey Sewell
f1c3691356 inorder: check for interrupts each tick
use a dummy instruction to facilitate the squash after
the interrupts trap
2011-06-19 21:43:40 -04:00
Korey Sewell
0bfdf342da inorder: explicit fault check
Before graduating an instruction, explicitly check fault
by making the fault check it's own separate command
that can be put on an instruction schedule.
2011-06-19 21:43:40 -04:00
Korey Sewell
5f608dd2e9 inorder: squash and trap behind a tlb fault 2011-06-19 21:43:39 -04:00
Korey Sewell
e0e387c2a9 inorder: stall stores on store conditionals & compare/swaps 2011-06-19 21:43:39 -04:00
Korey Sewell
f268d7d004 alpha: make hwrei a control inst
this always changes the PC and is basically an impromptu branch instruction. why
not speculate on this instead of always be forced to mispredict/squash after the
hwrei gets resolved?

The InOrder model needs this marked as "isControl" so it knows to update the PC
after the ALU executes it. If this isnt marked as control, then it's going to
force the model to check the PC of every instruction at commit (what O3 does?),
and that would be a wasteful check for a very high percentage of instructions.
2011-06-19 21:43:39 -04:00
Korey Sewell
e8b7df072b inorder: make InOrder CPU FS compilable/visible
make syscall a SE mode only functionality
copy over basic FS functions (hwrei) to make FS compile
2011-06-19 21:43:39 -04:00
Korey Sewell
d71b95d84d inorder: remove memdep tracking for default pipeline
speculative load/store pipelines can reenable this
2011-06-19 21:43:39 -04:00
Korey Sewell
b72bdcf4f8 inorder: fetchBuffer tracking
calculate blocks in use for the fetch buffer to figure out how many total blocks
are pending
2011-06-19 21:43:39 -04:00
Korey Sewell
4d4c7d79d0 inorder: redefine DynInst FP result type
Sharing the FP value w/the integer values was giving inconsistent results esp. when
their is a 32-bit integer register matched w/a 64-bit float value
2011-06-19 21:43:38 -04:00
Korey Sewell
db8b1e4b78 inorder: treat SE mode syscalls as a trapping instruction
define a syscallContext to schedule the syscall and then use syscall() to actually perform the action
2011-06-19 21:43:38 -04:00
Korey Sewell
c95fe261ab inorder: bug in mdu
segfault was caused by squashed multiply thats in the process of an event.
use isProcessing flag to handle this and cleanup the MDU code
2011-06-19 21:43:38 -04:00
Korey Sewell
4c979f9325 inorder: optionally track faulting instructions 2011-06-19 21:43:38 -04:00
Korey Sewell
22ba1718c4 inorder: cleanup events in resource pool
remove events in the resource pool that can be called from the CPU event, since the CPU
event is scheduled at the same time at the resource pool event.
----
Also, match the resPool event function names to the cpu event function names
----
2011-06-19 21:43:38 -04:00
Korey Sewell
e8082a28c8 inorder: don't stall after stores
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
2011-06-19 21:43:38 -04:00
Korey Sewell
379c23199e inorder: don't stall after stores
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
2011-06-19 21:43:37 -04:00
Korey Sewell
4c9ad53cc5 inorder: remove decode squash
also, cleanup comments for gem5.fast compilation
2011-06-19 21:43:37 -04:00
Korey Sewell
a444133e73 inorder: support for compare and swap insts
dont treat read() and write() fields as mut. exclusive
2011-06-19 21:43:37 -04:00
Korey Sewell
89d0f95bf0 inorder: branch predictor update
only update BTB on a taken branch and update branch predictor w/pcstate from instruction
---
only pay attention to branch predictor updates if the the inst. is in fact a branch
2011-06-19 21:43:37 -04:00
Korey Sewell
479195d4cf inorder: priority for grad/squash events
define separate priority resource pool squash and graduate events
2011-06-19 21:43:37 -04:00
Korey Sewell
71018f5e8b inorder: remove stalls on trap squash 2011-06-19 21:43:37 -04:00
Korey Sewell
34b2500f09 inorder: no dep. tracking for zero reg
this causes forwarding a bad value register value
2011-06-19 21:43:37 -04:00
Korey Sewell
d02fa0f6b6 imported patch recoverPCfromTrap 2011-06-19 21:43:37 -04:00
Korey Sewell
264e8178ff imported patch squash_from_next_stage 2011-06-19 21:43:36 -04:00
Korey Sewell
f0f33ae2b9 inorder: add flatDestReg member to dyninst
use it in reg. dep. tracking
2011-06-19 21:43:36 -04:00
Korey Sewell
555bd4d842 inorder: update event priorities
dont use offset to calculate this but rather an enum
that can be updated
2011-06-19 21:43:36 -04:00
Korey Sewell
7dea79535c inorder: implement trap handling 2011-06-19 21:43:36 -04:00
Korey Sewell
061b369d28 inorder: cleanup intercomm. structs/squash info 2011-06-19 21:43:35 -04:00
Korey Sewell
b195da9345 inorder: use setupSquash for misspeculation
implement a clean interface to handle branch misprediction and eventually all pipeline
flushing
2011-06-19 21:43:35 -04:00
Korey Sewell
d5d4e47f76 sparc: init. cache state in TLB
valgrind complains and its a potential source of instability, so go ahead
and set it to 0 to start
2011-06-19 21:43:35 -04:00
Korey Sewell
73cfab8b23 inorder: DynInst handling of stores for big-endian ISAs
The DynInst was not performing the host-to-guest translation
which ended up breaking stores for SPARC
2011-06-19 21:43:35 -04:00
Korey Sewell
4f34bc8b7b inorder: make marking of dest. regs an explicit request
formerly, this was implicit when you accessed the execution unit
or the use-def unit but it's better that this just be something
that a user can specify.
2011-06-19 21:43:35 -04:00
Korey Sewell
946b0ed4f4 inorder: simplify handling of split accesses 2011-06-19 21:43:35 -04:00
Korey Sewell
1a6d25dc47 inorder: addtl functionaly for inst. skeds
add find and end functions for inst. schedules
that can search by stage number
2011-06-19 21:43:35 -04:00
Korey Sewell
8b54858831 inorder: register file stats
keep stats for int/float reg file usage instead
of aggregating across reg file types
2011-06-19 21:43:34 -04:00
Korey Sewell
085f30ff9c inorder: scheduling for nonspec insts
make handling of speculative and nonspeculative insts
more explicit
2011-06-19 21:43:34 -04:00
Korey Sewell
3c417ea23a inorder: find register dependencies "lazily"
Architectures like SPARC need to read the window pointer
in order to figure out it's register dependence. However,
this may not get updated until after an instruction gets
executed, so now we lazily detect the register dependence
in the EXE stage (execution unit or use_def). This
makes sure we get the mapping after the most current change.
2011-06-19 21:43:34 -04:00
Korey Sewell
bd67ee9852 inorder: assert on macro-ops
provide a sanity check for someone coding
a new architecture
2011-06-19 21:43:34 -04:00
Korey Sewell
ee7062d94d inorder: handle faults at writeback stage
call trap function when a fault is received
2011-06-19 21:43:34 -04:00
Korey Sewell
17f5749dbb inorder: ISA-zero reg handling
ignore writes to the ISA zero register
2011-06-19 21:43:34 -04:00
Korey Sewell
2a59fcfbe9 inorder: update support for branch delay slots 2011-06-19 21:43:34 -04:00
Korey Sewell
d4b4ef1324 inorder: inst. iterator cleanup
get rid of accessing iterators (for instructions) by reference
2011-06-19 21:43:34 -04:00
Korey Sewell
b43eeaf2e2 cpus/isa: add a != operator for pcstate 2011-06-19 21:43:33 -04:00
Korey Sewell
e2f9266dbf inorder: update bpred code
clean up control flow to make it easier to understand
2011-06-19 21:43:33 -04:00
Korey Sewell
6df6365095 inorder: add types for dependency checks 2011-06-19 21:43:33 -04:00
Korey Sewell
19e3eb2915 inorder: use flattenIdx for reg indexing
- also use "threadId()" instead of readTid() everywhere
- this will help support more complex ISA indexing
2011-06-19 21:43:33 -04:00
Korey Sewell
b2e5152e16 simple-thread: give a name() function for debugging w/the SimpleThread object 2011-06-19 21:43:33 -04:00
Korey Sewell
76c60c5f93 inorder: use m5_hash_map for skedCache
since we dont care about if the cache of instruction schedules is sorted or not,
then the hash map should be faster
2011-06-19 21:43:33 -04:00
Gedare Bloom
3f1f16703d ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. 2011-06-17 12:20:10 -05:00
Ali Saidi
8b4307f8d8 ARM: Handle case where new TLB size is different from previous TLB size.
After a checkpoint we need to make sure that we restore the right
number of entries.
2011-06-16 15:08:12 -05:00
Chander Sudanthi
9fe3610b32 ARM: Fix memset on TLB flush and initialization
Instead of clearing the entire TLB on initialization and flush, the code was
clearing only one element.  This patch corrects the memsets in the init and
flush routines.
2011-06-16 15:08:11 -05:00
Nilay Vaish
8bf92329ee Ruby: Correct set LONG_BITS and INDEX_SHIFT in class Set.
The code for Set class was written under the assumption that
std::numeric_limits<long>::digits returns the number of bits used for
data type long, which was presumed to be either 32 or 64. But return value
is actually one less, that is, it is either 31 or 63. The value is now
being incremented by 1 so as to correctly set it.
2011-06-14 19:51:44 -05:00
Gabe Black
91622602c2 Loader: Handle bad section names when loading an ELF file.
If there's a problem when reading the section names from a supposed ELF file,
this change makes gem5 print an error message as returned by libelf and die.
Previously these sorts of errors would make gem5 segfault when it tried to
access the section name through a NULL pointer.
2011-06-12 23:52:21 -07:00
Korey Sewell
c8b43641fd o3: missing newlines on some dprintfs 2011-06-10 22:15:32 -04:00
Korey Sewell
4229bce89d sparc: don't use directcntrl branch flag
this flag is only used for early branch resolution in the O3 model (of pc-relative branches)
but this isnt cleanly working even when the branch target code is added for sparc. For now,
we'll ignore this optimization and add a todo in the SPARC ISA for future developers
2011-06-10 22:15:32 -04:00
Korey Sewell
1a451cd2c5 sparc: compilation fixes for inorder
Add a few constants and functions that the InOrder model wants for SPARC.
* * *
sparc: add eaComp function
InOrder separates the address generation from the actual access so give
Sparc that functionality
* * *
sparc: add control flags for branches
branch predictors and other cpu model functions need to know specific information
about branches, so add the necessary flags here
2011-06-09 01:34:06 -04:00
Nilay Vaish
67bb307003 Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set correctly.
This is because pointers are not used for handling directory entries.
function. get and set functions for access permissions have been added to the
Controller state machine. The changePermission() function provided by the
AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC
code once again. The set_permission() functionality has been removed.

NOTE: Each protocol will have to define these get and set functions in order
to compile successfully.
2011-06-08 11:58:09 -05:00
Gabe Black
1f7a627401 Mem: Use sysconf to get the page size instead of the PAGE_SIZE macro. 2011-06-08 00:57:50 -07:00
Gabe Black
ab3704170e ISA parser: Loosen the regular expressions matching filenames.
The regular expressions matching filenames in the ##include directives and the
internally generated ##newfile directives where only looking for filenames
composed of alpha numeric characters, periods, and dashes. In Unix/Linux, the
rules for what characters can be in a filename are much looser than that. This
change replaces those expressions with ones that look for anything other than
a quote character. Technically quote characters are allowed as well so we
should allow escaping them somehow, but the additional complexity probably
isn't worth it.
2011-06-07 00:46:54 -07:00
Gabe Black
a59a143a25 gcc 4.0: Add some virtual destructors to make gcc 4.0 happy. 2011-06-07 00:24:49 -07:00
Nilay Vaish
3a083edc30 SLICC: Remove machine name as prefix to functions
Currently, the machine name is appended before any of the functions
defined with in the sm files. This is not necessary and it also
means that these functions cannot be used outside the sm files.
This patch does away with the prefixes. Note that the generated
C++ files in which the code for these functions is present are
still named such that the machine name is the prefix.
2011-06-03 13:52:18 -05:00
Nathan Binkert
2b1aa35e20 scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00
Nathan Binkert
f49f384fe4 scons: rename some things from m5 to gem5
The default generated binary is now gem5.<type> instead of m5.<type>.
The latter does still work but gem5.<type> will be generated first and
then m5.<type> will be hard linked to it.
2011-06-02 17:36:18 -07:00
Nathan Binkert
0c424344fa copyright: Add code for finding all copyright blocks and create a COPYING file
The end of the COPYING file was generated with:
% python ./util/find_copyrights.py configs src system tests util

Update -C command line option to spit out COPYING file
2011-06-02 17:36:07 -07:00
Nathan Binkert
f656787edb copyright: clean up copyright blocks 2011-06-02 14:36:35 -07:00
Steve Reinhardt
6a1be32a72 SimObject: allow modules in subclass definitions
In particular, this avoids crashing when you do
an import (like "import pdb") inside a SimObject
subclass definition.
2011-06-01 21:43:13 -07:00
Tushar Krishna
07e5b15953 orion: bug fix in link power, and some reorg 2011-05-31 02:56:22 -04:00
Tushar Krishna
36899dc197 garnet: added network ptr to links to be used by orion 2011-05-31 02:55:14 -04:00
Gabe Black
8dcbe8adb5 Misc: Remove the URL from warnings, fatals, panics, etc. 2011-05-29 21:48:58 -07:00
Gabe Black
96138a79cd Name: Replace M5 with gem5 in a few places it's printed on startup. 2011-05-25 01:32:07 -07:00
Steve Reinhardt
0cbbedcc33 sim: style fixes in sim/process.hh 2011-05-23 14:29:23 -07:00
Steve Reinhardt
8d29bda742 syscall emul: fix Power Linux mmap constant, plus other cleanup
We were getting a spurious warning in the regressions that turned
out to be due to having the wrong value for TGT_MAP_ANONYMOUS for
Power Linux, but in the process of tracking it down I ended up
doing some cleanup of the mmap handling in general.
2011-05-23 14:29:23 -07:00
Steve Reinhardt
19bb896bfe config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams()
is the practice of appending to SimObjectVectors which have
already been assigned as children.  This practice sidesteps the
assignment operation for those appended SimObjects, which is
where parent/child relationships are typically established.

This patch reworks the config scripts that use append() on
SimObjectVectors, which all happen to be in the x86 system
configuration.  At some point in the future, I hope to make
SimObjectVectors immutable (by deriving from tuple rather than
list), at which time this patch will be necessary for correct
operation.  For now, it just avoids some of the warning
messages that get printed in adoptOrphanParams().
2011-05-23 14:29:23 -07:00
Steve Reinhardt
8a652f9871 config: tweak ruby configs to clean up hierarchy
Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings.  This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
   caches children of the sequencer rather than the controller; these
   config ciles are rewritten to assign the L1 caches to the
   controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
   causes the sequencers to be children of system.ruby, generating
   warnings because they are already parented to their respective
   controllers.  Changing this attribute to _cpu_ruby_ports fixes this
   because the leading underscore means this is now treated as a plain
   Python attribute rather than a child assignment. As a result, the
   configuration hierarchy changes such that, e.g.,
   system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
   internal link node rather than direct children of the topology.
   The topology classes are rewritten to assign the routers to the
   topology object first.
2011-05-23 14:29:23 -07:00
Steve Reinhardt
41fc9bbab5 config: reinstate implicit parenting on parameter assignment
Last summer's big rewrite of the initialization code (in
particular cset 6efc3672733b) got rid of the implicit parenting
that used to occur when an unparented SimObject was assigned as
a parameter value to another SimObject.  The idea was that the
new adoptOrphanParams() step would catch these anyway so it was
unnecessary.

Unfortunately it turns out that adoptOrphanParams() has some
inherent instability in that the parent that does the adoption
depends on the config tree traversal order.  Even making this
order deterministic (e.g., by traversing children in
alphabetical order) can introduce unwanted and unexpected
hierarchy changes between similar configs (e.g., when adding a
switch_cpu in place of a cpu), causing problems when trying to
restore checkpoints across similar configs.  The hierarchy
created by implicit parenting is more stable and more
controllable, so this patch turns that behavior back on.

This patch also cleans up some long-standing holes regarding
parenting of SimObjects that are created in class definitions
(either in the body of the class, or as default parameters).

To avoid breaking some existing config files, this necessitated
changing the error on reparenting children to a warning.  This
change fixes another bug where attempting to print the prior
error message would fail on reparenting SimObjectVectors
because they lack a _parent attribute.  Some further issues
with SimObjectVectors were cleaned up by getting rid of the
get_parent() call (which could cause errors with some
SimObjectVectors where there was no single parent to return)
with has_parent() (since all the uses of get_parent() were just
boolean tests anyway).

Finally, since the adoptOrphanParam() step turned out to be so
problematic, we now issue a warning when it actually has to do
an adoption.  Future cleanup of config files will get rid of
current warnings.
2011-05-23 14:29:08 -07:00
Steve Reinhardt
ccbecb9e8f sim: add some DPRINTFs for debugging unserialization
Also got rid of unused C++ unserializeAll() method
(this is now handled in Python)
2011-05-23 14:27:20 -07:00
Geoffrey Blake
d0b0a55515 O3: Fix offset calculation into storeQueue buffer for store->load forwarding
Calculation of offset to copy from storeQueue[idx].data structure for load to
store forwarding fixed to be difference in bytes between store and load virtual
addresses.  Previous method would induce bug where a load would index into
buffer at the wrong location.
2011-05-23 10:40:21 -05:00
Geoffrey Blake
c223b887fe O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.
If a split load fails on a blocked cache wbOutstanding can be decremented
twice if the first part of the split load succeeds and the second part fails.
Condition the decrementing on not having completed the first part of the load.
2011-05-23 10:40:19 -05:00
Geoffrey Blake
6dd996aabb O3: Fix issue with interrupts/faults occuring in the middle of a macro-op
This patch fixes two problems with the O3 cpu model. The first is an issue
with an instruction fetch causing a fault on the next address while the
current macro-op is being issued. This happens when the micro-ops exceed
the fetch bandwdith and then on the next cycle the fetch stage attempts
to issue a request to the next line while it still has micro-ops to issue
if the next line faults a fault is attached to a micro-op in the currently
executing macro-op rather than a "nop" from the next instruction block.
This leads to an instruction incorrectly faulting when on fetch when
it had no reason to fault.

A similar problem occurs with interrupts. When an interrupt occurs the
fetch stage nominally stops issuing instructions immediately. This is incorrect
in the case of a macro-op as the current location might not be interruptable.
2011-05-23 10:40:18 -05:00
Tushar Krishna
fc1d2d9679 garnet: use vnet_type from protocol to decide buffer depths
The virtual channels within "response" vnets are made buffers_per_data_vc
deep (default=4), while virtual channels within other vnets are made
buffers_per_ctrl_vc deep (default = 1). This is for accurate power estimates.
2011-05-21 00:40:57 -04:00
Tushar Krishna
3d06ffa7d5 slicc: added vnet_type to MI_example
Forgot to add this to MI_example in my previous patch.
2011-05-20 05:06:43 -04:00
Nathan Binkert
22263f5091 gcc: fix an uninitialized variable warning from G++ 4.5 2011-05-18 11:06:23 -07:00
Tushar Krishna
3ed048e4f5 slicc: added vnet_type field to identify response vnets from others
Identifying response vnets versus other vnets will allow garnet to
determine which vnets will carry data packets, and which will carry
ctrl packets, and use appropriate buffer sizes (since data packets are larger
than ctrl packets). This in turn allows the orion power model to accurately
estimate buffer power.
2011-05-18 03:06:07 -04:00
Tushar Krishna
26eaba4cb5 garnet: rename and rearrange config parameters.
Renamed (message) class to vnet for consistency with rest of ruby.
Moved some parameters specific to fixed/flexible garnet networks into their
corresponding py files.
2011-05-18 03:04:14 -04:00
Ali Saidi
b5160ba2c3 ARM: Generate condition code setting code based on which codes are set.
This change further eliminates cases where condition codes were being read
just so they could be written without change because the instruction in
question was supposed to preserve them. This is done by creating the condition
code code based on the input rather than just doing a simple substitution.
2011-05-13 17:27:02 -05:00
Ali Saidi
05866c82f9 ARM: Construct the predicate test register for more instruction programatically.
If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.
2011-05-13 17:27:02 -05:00
Ali Saidi
401165c778 ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
2011-05-13 17:27:01 -05:00
Ali Saidi
e097c4fb18 ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
2011-05-13 17:27:01 -05:00
Ali Saidi
2178859b76 ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
2011-05-13 17:27:01 -05:00
Chander Sudanthi
4bf48a11ef Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.
Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
ExecKernel are set by default when Exec is specified.  Use minus
sign with ExecUser or ExecKernel to remove user or kernel tracing
respectively.
2011-05-13 17:27:00 -05:00
Chander Sudanthi
5299c75e62 ARM: Better RealView/Versatile EB platform support.
Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
2011-05-13 17:27:00 -05:00
Geoffrey Blake
b79650ceaa O3: Fix an issue with a load & branch instruction and mem dep squashing
Instructions that load an address and are control instructions can
execute down the wrong path if they were predicted correctly and then
instructions following them are squashed. If an instruction is a
memory and control op use the predicted address for the next PC instead
of just advancing the PC. Without this change NPC is used for the next
instruction, but predPC is used to verify that the branch was successful
so the wrong path is silently executed.
2011-05-13 17:27:00 -05:00
Nathan Binkert
f7b3900c13 stats: delete mysql support
we can add it back within python in some future changeset
2011-05-12 11:19:35 -07:00
Nathan Binkert
1177e7a3c8 stats: move code that loops over all stats into python 2011-05-12 11:19:35 -07:00
Nathan Binkert
35b0c1d391 stats: better expose statistics to python.
Build a python list and dict of all stats and expose flags properly.

--HG--
rename : src/python/m5/stats.py => src/python/m5/stats/__init__.py
2011-05-12 11:19:32 -07:00