Commit graph

539 commits

Author SHA1 Message Date
Brad Beckmann
17b4ef52bb ruby: x86 fs config support 2011-02-06 22:14:18 -08:00
Brad Beckmann
1b54344aeb MOESI_hammer: Added full-bit directory support 2011-02-06 22:14:18 -08:00
Gabe Black
fd26707731 Mem,X86: Make the IO bridge pass APIC messages back towards the CPU. 2011-02-03 20:56:27 -08:00
Gabe Black
00f24ae92c Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
2011-02-03 20:23:00 -08:00
Gabe Black
c4b81d311e X86: Change how the default disk image gets set up.
The disk image to use was always being forced to a particular value. This
change changes what disk image is selected as the default based on the
architecture being built. In the future, a more sophisticated system might be
used that selected a path based on certain rules instead of relying on one off
file names.
2011-02-02 18:03:58 -08:00
Gabe Black
119f5f8e94 X86: Add L1 caches for the TLB walkers.
Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
2011-02-01 18:28:41 -08:00
Gabe Black
a368fba7d4 Time: Add a mechanism to prevent M5 from running faster than real time.
M5 skips over any simulated time where it doesn't have any work to do. When
the simulation is active, the time skipped is short and the work done at any
point in time is relatively substantial. If the time between events is long
and/or the work to do at each event is small, it's possible for simulated time
to pass faster than real time. When running a benchmark that can be good
because it means the simulation will finish sooner in real time. When
interacting with the real world through, for instance, a serial terminal or
bridge to a real network, this can be a problem. Human or network response time
could be greatly exagerated from the perspective of the simulation and make
simulated events happen "too soon" from an external perspective.

This change adds the capability to force the simulation to run no faster than
real time. It does so by scheduling a periodic event that checks to see if
its simulated period is shorter than its real period. If it is, it stalls the
simulation until they're equal. This is called time syncing.

A future change could add pseudo instructions which turn time syncing on and
off from within the simulation. That would allow time syncing to be used for
the interactive parts of a session but then turned off when running a
benchmark using the m5 utility program inside a script. Time syncing would
probably not happen anyway while running a benchmark because there would be
plenty of work for M5 to do, but the event overhead could be avoided.
2011-01-19 11:48:00 -08:00
Nathan Binkert
bd18ac8287 ruby: get rid of ruby's Debug.hh
Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace
2011-01-10 11:11:20 -08:00
Nilay Vaish
5e25f31712 Ruby: Add option for random seed to Ruby.py
This patch adds an option to the script Ruby.py for setting the parameter
m_random_seed used for randomizing delays in the memory system. The option
can be specified as "--random_seed <seed value>".
2011-01-03 12:40:31 -06:00
Ali Saidi
18555c1b56 Configs: Automatically choose the correct hello world binary. 2010-12-07 16:19:57 -08:00
Gabe Black
4876e0c92b Config: Change misleading "cycle" message to say "tick".
Most of the messages in the config scripts that report a time value already
print "@ tick" followed by the current tick value, but a few were printing
"@ cycle". Since this is a distinction that's frequently confusing to new
users, this changes those message to the more accurate and consistent "@ tick".
2010-11-17 23:16:19 -05:00
Ali Saidi
d7b8efa0df ARM: Add support for a dumb IDE controller 2010-11-15 14:04:03 -06:00
Ali Saidi
c779af4e12 Mem: Finish half-baked support for mmaping file in physmem.
Physmem has a parameter to be able to mem map a file, however
it isn't actually used. This changeset utilizes the parameter
so a file can be mmapped.
2010-11-08 13:58:24 -06:00
Gabe Black
df3fd79d1f Configs: Stop setting the "mem" parameter in splash2 config files.
This parameter is no longer used, and trying to set it like these scripts were
gives a simobject two parents and causes the simulation to die.
2010-10-22 20:59:22 -07:00
Brad Beckmann
8f1f83d13d config: fixed numa high bit setting bug 2010-08-30 15:26:51 -07:00
Brad Beckmann
08b360e0e0 config: minor fix to probe filter index setting 2010-08-30 12:07:21 -07:00
Nathan Binkert
6d207bf40d ruby: None, not none 2010-08-29 07:02:42 -07:00
Steve Reinhardt
6d9fc4175e memtest: scale associativity and mshrs according to config
Use the actual fanouts in the tree specification to scale
cache associativity and mshrs instead of dumb constants.
2010-08-25 21:55:42 -07:00
Brad Beckmann
d4318457d1 config: changed ruby config file names to be consistent 2010-08-24 14:08:23 -07:00
Brad Beckmann
0e610290d0 config: remove ruby's requirement on the timing cmd line param
Since ruby only works in timing mode, explicitly requiring the timing cmd line
param to be specified is not necessary.
2010-08-24 13:20:32 -07:00
Brad Beckmann
8572d8fd91 config: fixed ruby dma device connections 2010-08-24 13:20:31 -07:00
Brad Beckmann
e983ef9e8c testers: move testers to a new directory
This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.

--HG--
rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py
rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc
rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh
rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc
rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh
rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc
rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh
rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py
rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript
rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc
rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh
rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py
rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript
rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc
rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh
rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc
rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh
rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc
rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh
rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc
rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh
rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py
rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-24 12:07:22 -07:00
Ali Saidi
330fada1aa ARM: Add configuration for Linux/Full System 2010-08-23 11:18:40 -05:00
Brad Beckmann
af6b97e3ee ruby: Recycle latency fix for hammer
Patch allows each individual message buffer to have different recycle latencies
and allows the overall recycle latency to be specified at the cmd line. The
patch also adds profiling info to make sure no one processor's requests are
recycled too much.
2010-08-20 11:46:14 -07:00
Brad Beckmann
8b28848321 ruby: added probe filter support to hammer 2010-08-20 11:46:14 -07:00
Brad Beckmann
593ae7457e ruby: fixed DirectoryMemory's numa_high_bit configuration
This fix includes the off-by-one bit selection bug for numa mapping.
2010-08-20 11:46:13 -07:00
Brad Beckmann
72044e3f5a ruby: Disable migratory sharing for token and hammer
This patch allows one to disable migratory sharing for those cache blocks that
are accessed by atomic requests.  While the implementations are different
between the token and hammer protocols, the motivation is the same.  For
Alpha, LLSC semantics expect that normal loads do not unlock cache blocks that
have been locked by LL accesses.  Therefore, locked blocks should not transfer
write permissions when responding to these load requests.  Instead, only they
only transfer read permissions so that the subsequent SC access can possibly
succeed.
2010-08-20 11:46:13 -07:00
Brad Beckmann
9b130c153b ruby: Improved try except blocks in ruby creation
Replaced the sys.exit in the try-except blocks with raise so that the python
call stack will be printed
2010-08-20 11:46:13 -07:00
Brad Beckmann
a2dcbde165 config: added cmd options to control ruby debug 2010-08-20 11:46:13 -07:00
Brad Beckmann
6a4f99899b ruby: Resurrected Ruby's deterministic tests
Added the request series and invalidate deterministic tests as new cpu models
and removed the no longer needed ruby tests

--HG--
rename : configs/example/rubytest.py => configs/example/determ_test.py
rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/DirectedGenerator.cc
rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/DirectedGenerator.hh
rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/InvalidateGenerator.cc
rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/InvalidateGenerator.hh
rename : src/cpu/rubytest/RubyTester.cc => src/cpu/directedtest/RubyDirectedTester.cc
rename : src/cpu/rubytest/RubyTester.hh => src/cpu/directedtest/RubyDirectedTester.hh
rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/SeriesRequestGenerator.cc
rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/SeriesRequestGenerator.hh
2010-08-20 11:46:13 -07:00
Brad Beckmann
29c45ccd23 ruby: Reduced ruby latencies
The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system.  Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks.  The result was many cpus were idle for large periods of time.

These changes fix the latency mismatch.
2010-08-20 11:46:12 -07:00
Brad Beckmann
808701a10c memtest: Memtester support for DMA
This patch adds DMA testing to the Memtester and is inherits many changes from
Polina's old tester_dma_extension patch.  Since Ruby does not work in atomic
mode, the atomic mode options are removed.
2010-08-20 11:46:12 -07:00
Brad Beckmann
10e25cb1d0 config: Improve ruby simobject names
This patch attaches ruby objects to the system before the topology is
created so that their simobject names read their meaningful variable
names instead of their topology name.
2010-08-20 11:46:11 -07:00
Brad Beckmann
c7bd896448 ruby: added token broadcast config params to cmd options 2010-08-20 11:46:11 -07:00
Brad Beckmann
5c801090a3 config: reorganized how ruby specifies command-line options 2010-08-20 11:44:09 -07:00
Brad Beckmann
7816d0d12b config: moved python protocol config files
Moved the python protocol config files back to their original location to avoid
addToPath calls.

--HG--
rename : configs/ruby/protocols/MESI_CMP_directory.py => configs/ruby/MESI_CMP_directory.py
rename : configs/ruby/protocols/MI_example.py => configs/ruby/MI_example.py
rename : configs/ruby/protocols/MOESI_CMP_directory.py => configs/ruby/MOESI_CMP_directory.py
rename : configs/ruby/protocols/MOESI_CMP_token.py => configs/ruby/MOESI_CMP_token.py
rename : configs/ruby/protocols/MOESI_hammer.py => configs/ruby/MOESI_hammer.py
2010-08-20 11:41:35 -07:00
Steve Reinhardt
e0754c0f6c misc: add some AMD copyright notices
Meant to add these with the previous batch of csets.
2010-08-17 05:49:05 -07:00
Steve Reinhardt
2519d116c9 sim: fold checkpoint restore code into instantiate()
The separate restoreCheckpoint() call is gone; just pass
the checkpoint dir as an optional arg to instantiate().
This change is a precursor to some more extensive
reworking of the startup code.
2010-08-17 05:17:06 -07:00
Steve Reinhardt
cfaddd5fd3 configs: clean up checkpoint code in Simulation.py
Small change to clean up some redundant code.
Should not have any functional impact.
2010-08-17 05:17:06 -07:00
Steve Reinhardt
1fbe466345 sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once.  The C++ Root object already panics if more than one is
created.  This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists).  It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone.  Users who use
configs/common/Simulate.py should not notice.
2010-08-17 05:06:22 -07:00
Nathan Binkert
2e9e75447a None, not none 2010-08-08 22:57:16 -07:00
Steve Reinhardt
cbd65e95db util: add a script for testing checkpointing
See comments in util/checkpoint-tester.py for details.
2010-07-05 21:39:38 -07:00
Ali Saidi
3dc6a8070e ARM: fix sizes of structs for ARM Linux 2010-06-02 12:58:17 -05:00
Nathan Binkert
90820ddf02 config: fix assertion for x86 in FSConfig.py 2010-04-18 21:33:59 -07:00
Brad Beckmann
898f1fc4a4 ruby: Reorganized Ruby topology and protocol files
--HG--
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/protocols/MESI_CMP_directory.py
rename : configs/ruby/MI_example.py => configs/ruby/protocols/MI_example.py
rename : configs/ruby/MOESI_CMP_directory.py => configs/ruby/protocols/MOESI_CMP_directory.py
rename : configs/ruby/MOESI_CMP_token.py => configs/ruby/protocols/MOESI_CMP_token.py
rename : configs/ruby/MOESI_hammer.py => configs/ruby/protocols/MOESI_hammer.py
rename : configs/ruby/networks/MeshDirCorners.py => src/mem/ruby/network/topologies/MeshDirCorners.py
2010-03-21 21:22:22 -07:00
Brad Beckmann
61e6b9e701 added sparse memory support to hammer 2010-03-21 21:22:21 -07:00
Brad Beckmann
4f044605e8 ruby: Adds configurable bit selection for numa mapping 2010-03-21 21:22:21 -07:00
Brad Beckmann
92cfd1cac7 ruby: Ruby support for sparse memory
The patch includes direct support for the MI example protocol.
2010-03-21 21:22:21 -07:00
Brad Beckmann
c67bddc84a ruby: removed ruby.config from configs/example 2010-03-21 21:22:20 -07:00
Brad Beckmann
91b0c5487b ruby: Python config files now sets a unique id for each sequencer 2010-03-21 21:22:20 -07:00
Brad Beckmann
d8e1e5abd0 ruby: fixed how ruby_fs creates phsyical memory
Now ruby_fs creates physical memory of the right size.
2010-03-21 21:22:20 -07:00
Brad Beckmann
1765badda2 ruby: Added a mesh network with directories at the corners
The patch creates a specific mesh network where directories are at the corners.
The patch is a good example of how to create an arbitrary network, similar to
the old file specified network, while leveraging scripts and loops when
possible.
2010-03-21 21:22:20 -07:00
Gabe Black
b1cbd7841a Config: Fix fs.py's call to CacheConfig.config_cache. 2010-02-27 18:52:57 -08:00
Lisa Hsu
a70f70ccbf configs: pull out cache configuration code from se.py and fs.py.
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.
2010-02-25 10:13:40 -08:00
Lisa Hsu
1d3228481f cache: Make caches sharing aware and add occupancy stats.
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).
2010-02-23 09:34:22 -08:00
Brad Beckmann
057f5898ca ruby: ruby_se.py updated to new config system 2010-01-29 20:29:33 -08:00
Brad Beckmann
c441590b15 ruby: Removed if else statement in create_system
Based on Steve's suggestion, the ugly if-elif statement and multiple protocol
module import calls are removed and replaced with exec statements using the
protocol string.
2010-01-29 20:29:33 -08:00
Brad Beckmann
26cce73e97 ruby: memtest-ruby updated to the new config system 2010-01-29 20:29:33 -08:00
Brad Beckmann
8dd45674ae ruby: Converted Garnet to M5 configuration 2010-01-29 20:29:32 -08:00
Brad Beckmann
6c867f8263 ruby: Added a mesh topology 2010-01-29 20:29:27 -08:00
Brad Beckmann
faa76fc248 ruby: MESI_CMP_directory updated to the new config system 2010-01-29 20:29:27 -08:00
Brad Beckmann
31fcf09a68 ruby: MOESI_CMP_directory updated to the new config system 2010-01-29 20:29:26 -08:00
Brad Beckmann
d77a9df3c1 ruby: MOESI_CMP_token updates to use the new config system 2010-01-29 20:29:25 -08:00
Brad Beckmann
b3d195153e ruby: MI_example updates to use the new config system 2010-01-29 20:29:24 -08:00
Brad Beckmann
502b8bd8a4 ruby: Memory size consistency check
Ruby's memory is now sized according to the size of M5 physical memory.
2010-01-29 20:29:24 -08:00
Brad Beckmann
134cc3d48d ruby: convert to M5 MemorySize
Converted both ruby caches and directory memory to use the M5 MemorySize python
type.
2010-01-29 20:29:23 -08:00
Brad Beckmann
45230a4f6b ruby: added the GEMS ruby tester 2010-01-29 20:29:23 -08:00
Brad Beckmann
f88faa6c11 ruby: cleaned up ruby profilers
Cleaned up the ruby profilers by moving the memory controller profiling code
out of the main profiler object and into a separate object similar to the
current CacheProfiler.  Both the CacheProfiler and MemCntrlProfiler are
specific to a particular Ruby object, CacheMemory and MemoryControl
respectively.  Therefore, these profilers should not be SimObjects and
created by the python configuration system, but instead private objects.  This
simplifies the creation of these profilers.
2010-01-29 20:29:22 -08:00
Brad Beckmann
cfe41d0a1b ruby: Removed RubySystem::getNumberOfSequencers
removed the static function RubySystem::getNumberOfSequencers and replaced
it with a python config variable
2010-01-29 20:29:21 -08:00
Brad Beckmann
ce2d13195b ruby: FS support using the new configuration system 2010-01-29 20:29:21 -08:00
Brad Beckmann
dc758641c9 ruby: reorganized ruby python configuration
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester).  This
code works for memory tester, but have not tested fs mode.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2c9ca672df ruby: Memory Controller Profiler with new config system
This patch includes a rather substantial change to the memory controller
profiler in order to work with the new configuration system.  Most
noteably, the mem_cntrl_profiler no longer uses a string map, but instead
a vector.  Eventually this support should be removed from the main
profiler and go into a separate object.  Each memory controller should have
a pointer to that new mem_cntrl profile object.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2a0555470c ruby: Converted MOESI_hammer dma cntrl to new config system 2010-01-29 20:29:19 -08:00
Brad Beckmann
3b290a35ac ruby: Added the cache profiler to the new config system 2010-01-29 20:29:19 -08:00
Brad Beckmann
12daaed84a ruby: Added clock to ruby system
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
ed81489954 ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system.  Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects.  This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
42bebab779 ruby: connects sm queues to the network 2010-01-29 20:29:18 -08:00
Steve Reinhardt
a8ea70dac6 ruby: Calculate system total memory capacity in Python
rather than in RubySystem object.
2010-01-29 20:29:18 -08:00
Steve Reinhardt
0b54f1db8e ruby: Add support for generating topologies in Python. 2010-01-29 20:29:17 -08:00
Steve Reinhardt
98c94cfe3c ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
2010-01-29 20:29:17 -08:00
Gabe Black
93d89b288f X86: Record the memory mode when building an X86 system. 2009-12-19 01:49:34 -08:00
Brad Beckmann
c6182199c5 m5: improvements to the ruby_fs.py file 2009-11-18 16:34:32 -08:00
Brad Beckmann
70a261c0ae m5: Added option to take a checkpoint at the end of simulation 2009-11-18 13:55:58 -08:00
Brad Beckmann
b8c413e993 m5: Moved profile option since Simulation depends on it. 2009-11-18 13:55:58 -08:00
Brad Beckmann
90d6e2652f ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of ports
per core.  CPUs have two ports: icache + dcache.  MemTester has one port.
2009-11-18 13:55:58 -08:00
Brad Beckmann
3cf24f9716 ruby: Support for merging ALPHA_FS and ruby
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers.  Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
2009-11-18 13:55:58 -08:00
Brad Beckmann
c3204421d8 ruby: Ruby memtest python script. 2009-11-18 13:55:57 -08:00
Brad Beckmann
912f3d7074 removed libruby file reference from ruby_se.py 2009-10-16 08:15:53 -07:00
Nathan Binkert
9a8cb7db7e python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.

--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00
Korey Sewell
6499174115 inorder-configs: update se.py
fix bug with  'numThreads=len(workloads)' which was counting characters of command-line not counting threads as intended.
Update numThreads for inorder/o3 cases and default to 1 for all other cases.
2009-09-16 09:46:26 -04:00
Korey Sewell
7858a8e68f configs: add maxinsts option on command line
-option to allow threads to run to a max_inst_any_thread which is more useful/quicker in a lot of
cases then always having to figure out what tick to run your simulation to.
2009-09-16 09:45:30 -04:00
Steve Reinhardt
15bb248013 Add an I/O cache to FS config even if there's just an "L2" cache. 2009-09-14 21:19:40 -07:00
Korey Sewell
6c46313556 se-configs: edit se.py to account for non-O3CPU workloads 2009-07-26 00:13:35 -04:00
Korey Sewell
44f80e7ca5 o3-smt: enforce numThreads parameter for SMT SE mode 2009-07-25 00:50:27 -04:00
Daniel Sanchez
93f2f69657 ruby: Working M5 interface and updated Ruby interface.
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5.  Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
  tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
2009-05-11 10:38:46 -07:00
Korey Sewell
c70241810d cpus: fix cpu progress event
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
2009-05-05 02:51:31 -04:00
Gabe Black
8d84f81e70 X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment. 2009-04-26 02:04:32 -07:00
Steve Reinhardt
6629d9b2bc mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond.  Now there is just one on
the main memory bus.  The default bus responder on all other buses
is now the downstream cache's cpu_side port.  Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
2008-07-16 11:10:33 -07:00
Steve Reinhardt
97b6947eb7 Minor tweaks for future Ruby compatibility. 2009-04-21 08:17:36 -07:00
Gabe Black
b8333a5155 X86: Actually put the PCI INTA entry into the MP tables. 2009-04-19 04:15:18 -07:00
Gabe Black
25e223c30f X86: Make E820 report nice, round (and correct) numbers. 2009-04-19 04:14:48 -07:00
Gabe Black
06d25dcd26 X86: Automatically make the IO APIC in an N CPU system have id N+1. 2009-04-19 02:39:19 -07:00
Steve Reinhardt
9b66e82897 configs: Allow M5_CPU2000 env var to set CPU2K binary path.
It would be nice to have a more comprehensive mechanism
but this is a big improvement over manually editing the script.
2009-04-15 12:52:31 -07:00
Gabe Black
eafdf00eb3 X86: Add IRQ4 to the Intel MP tables. 2009-02-25 10:19:06 -08:00
Korey Sewell
cf4a00ca41 Configs: Add support for the InOrder CPU model 2009-02-10 15:49:29 -08:00
Gabe Black
1c5b9773bd X86: Find the natural lpj for this configuration. 2009-02-01 00:29:07 -08:00
Gabe Black
a5ed1590bd X86: Add a root device to the kernel command line. 2009-02-01 00:27:49 -08:00
Gabe Black
70cd5bfce5 X86: Configure the first PCI interrupt. 2009-02-01 00:26:10 -08:00
Gabe Black
18f6c18323 X86: Hook in a hard drive image. 2009-02-01 00:24:26 -08:00
Gabe Black
01679bb416 X86: Take out the IDE noprobe kernel arguments. 2009-02-01 00:20:44 -08:00
Gabe Black
bb7ad80bbe X86: Plug in an IDE controller. 2009-02-01 00:00:03 -08:00
Gabe Black
d08b8e2b82 X86: Add some interrupt info to the intel MP tables. 2009-01-31 23:43:09 -08:00
Ali Saidi
f4291aac25 Errors: Print a URL with a hash of the format string to find more information about an error. 2009-01-30 20:04:15 -05:00
Gabe Black
7b7a92d3f4 X86: Prevent Linux for probing for non-existant IDE controllers. 2009-01-25 20:36:24 -08:00
Gabe Black
ff29e00112 X86: Add entries for the IO APIC to the MP table. 2008-10-11 16:12:34 -07:00
Gabe Black
526933e5d0 X86: Add an Intel MP table to the simulation. 2008-10-11 15:14:37 -07:00
Gabe Black
3af428606a X86: Rename the PC device to Pc.
--HG--
rename : src/dev/x86/PC.py => src/dev/x86/Pc.py
2008-10-11 02:23:40 -07:00
Gabe Black
ec0fb05d64 X86: Turn SMBios structures into simobjects. 2008-10-10 03:50:51 -07:00
Gabe Black
b4dab225fd X86: Split makeLinuxX86System into makeLinuxX86System and makeX86System. 2008-10-10 03:50:30 -07:00
Ali Saidi
3a3e356f4e style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
Michael Adler
5f42bfcd56 process: separate stderr from stdout
- Add the option of redirecting stderr to a file. With the old
behaviour, stderr would follow stdout if stdout was to a file, but
stderr went to the host stderr if stdout went to the host stdout.  The
new default maintains stdout and stderr going to the host.  Now the
two can specify different files, but they will share a file descriptor
if the name of the files is the same.
- Add --output and --errout options to se.py to go with --input.
2008-07-23 14:41:34 -07:00
Nathan Binkert
00df9016fe Rename SimConsole to Terminal since it makes more sense
--HG--
rename : src/dev/SimConsole.py => src/dev/Terminal.py
rename : src/dev/simconsole.cc => src/dev/terminal.cc
rename : src/dev/simconsole.hh => src/dev/terminal.hh
2008-06-17 20:29:06 -07:00
Ali Saidi
7e6728450f Scripts: Check for the appropriate build type as soon as possible. 2008-06-13 01:09:06 -04:00
Gabe Black
bceaa257a3 X86: Make the e820 table manually or automatically configurable from python. 2008-06-12 00:58:36 -04:00
Gabe Black
561a541797 X86: Force the kernel to use a certain loops per jiffy instead of calculating it. 2008-06-12 00:46:16 -04:00
Gabe Black
f6a97752b0 X86: Make the amount of system memory match the hardcoded e820 info. 2008-06-12 00:45:11 -04:00
Gabe Black
633c585bfa X86: Make the regular console use the serial port as well. 2008-06-12 00:45:01 -04:00
Gabe Black
b0c52885ce X86: Change the Opteron platform to be the PC platform.
--HG--
extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
2008-03-25 02:06:53 -04:00
Ali Saidi
969688154d Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't exist
--HG--
extra : convert_revision : c156c49668815755c4c788f807e8eba32151aa24
2008-03-15 22:20:09 -04:00
Lisa Hsu
02a56d8d01 Error out if -s is used without --caches (instead of saying you must specify a
CPU).

--HG--
extra : convert_revision : a3b2bfbe7e037146ac08dd08834bf255da692506
2008-02-29 01:49:36 -05:00
Ali Saidi
0273533adb Configs: Make sure options don't conflict
--HG--
extra : convert_revision : dc9b91cf1d8e33c5e68d7faeb45dbe3e7038d14c
2008-02-29 01:23:18 -05:00
Ali Saidi
3cb7df428c Configs: Fix some bugs we introduced in the simpoints code
--HG--
extra : convert_revision : ef22c11cb3242903a484fc05dc0f96d3e5f9af72
2008-02-28 20:39:01 -05:00
Rick Strong
fcfc8b8c4f Configs: Make using Simpoints easier with some config files that support them easily
--HG--
extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd
2008-02-27 00:35:09 -05:00
Gabe Black
7bde0285e5 X86: Get PCI config space to work, and adjust address space prefix numbering scheme.
--HG--
extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
2008-02-26 23:38:01 -05:00
Vilas Sridharan
2e079ce038 add instruction count fast forwaing and max instruction options
--HG--
extra : convert_revision : 8fe45e512229cdc3e0dcd23e3e5c54516c445d0f
2008-02-22 17:48:10 -05:00
Ali Saidi
fc38e9c630 Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency.
--HG--
extra : convert_revision : f972207c616590a60a6e103daa5de469cf124b44
2008-02-14 16:13:50 -05:00
Gabe Black
657b52fea1 X86: Use the existing boot_osflags instead of duplicating it.
--HG--
extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a
2008-01-21 04:32:34 -05:00
Gabe Black
223e48e6ae X86: Make the IO ports work using extra physical address lines. Add a serial port.
--HG--
extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
2008-01-12 06:39:15 -05:00
Ali Saidi
45ea1549c9 Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something.
--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
2007-12-18 01:52:57 -05:00
Gabe Black
42ae409746 X86: Move startup code to the system object to initialize a Linux system.
--HG--
extra : convert_revision : a4796c79f41aa8b8f38bf2f628bee8f1b3af64be
2007-12-01 23:09:56 -08:00
Korey Sewell
10e0ae5407 Accidently kept hardcoded memory value in merge. Remove that and now ALPHA_FS quick regressions pass
--HG--
extra : convert_revision : 12582bef9317cd102cafdea9001f45651d34851f
2007-11-16 19:37:21 -05:00
Korey Sewell
3ee0433f7c compile-time fix for setMipsOptions function
--HG--
extra : convert_revision : e008f6d314d4891cb6ddc9cbf96fbcc6eee53b35
2007-11-16 19:15:20 -05:00
Korey Sewell
3fd291bc4e merge Ali's config change...
--HG--
extra : convert_revision : ada34ebc392d84f1225b4ff3e25f353396aa102f
2007-11-15 14:21:42 -05:00
Korey Sewell
3110b157e6 fix MIPS headers
--HG--
extra : convert_revision : 2870a146a1be0e8c80878090f39c0eaa15d2eb13
2007-11-15 14:21:01 -05:00
Korey Sewell
9cff176bbc add setMipsOptions function for MIPS usage
--HG--
extra : convert_revision : 42909d66a46201757cbdb14f75cccbd6b27d1f18
2007-11-15 14:20:41 -05:00
Ali Saidi
0896b5b897 Configs: Fix for benchmarks that don't use getopt.
--HG--
extra : convert_revision : 6cbc7bb360c282821dd9da7814e0ac8b689f5d01
2007-11-15 12:58:06 -05:00
Ali Saidi
185f0eb134 Config: Fix some errors in the splash2 config file.
--HG--
extra : convert_revision : 7bcb0f039e0609f95a081ef3aba2edb1ffa742f2
2007-11-15 03:51:28 -05:00
Korey Sewell
2692590049 Add in files from merge-bare-iron, get them compiling in FS and SE mode
--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-11-13 16:58:16 -05:00
Ali Saidi
5a4fc93fca Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if that isn't set use cwd.
--HG--
extra : convert_revision : 6548dd6de376dd59285a37a03bcf2525f8fc3845
2007-11-03 14:41:00 -04:00
Ali Saidi
51345d7324 Checkpoints: Change Simulation.py to not go crazy if the simulation ends before the number of checkpoints requested are created.
--HG--
extra : convert_revision : 865179134a219b34dbbba698e1fa0da7c452e074
2007-10-25 22:20:00 -04:00
Ali Saidi
a630d77ec5 Configuration: Move iocache outside of processors loop so it works for MP systems
--HG--
extra : convert_revision : 0ba563555a94eb22a6d4e402388e75e70d3556c2
2007-10-08 15:19:58 -04:00
Gabe Black
847a18ad48 X86: Adjust the config scripts for x86 fs.
--HG--
extra : convert_revision : 36ed22b50066f54be0e51c3419babc07dd218e10
2007-10-07 17:52:36 -07:00
Ali Saidi
136cb057d4 Checkpointing: Fix directory regex
--HG--
extra : convert_revision : 4d3958eda66209373249e54e7deadd1a7442e828
2007-09-12 15:27:15 -04:00
Ali Saidi
6f9ad931cc Checkpointing: Force drain/resume when switching a CPU
--HG--
extra : convert_revision : 7d9c3f4c8c357e3a9214deba5df3581beeaf7cb6
2007-09-12 15:24:24 -04:00
Ali Saidi
dd6a21190e Configuration: Fix example script to only create one L2 if --l2cache and -nX are given as parameters.
Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de]

--HG--
extra : convert_revision : 1dfc548d2bc33d622d829bbf385f4bf9700711cd
2007-09-05 14:57:50 -04:00
Ali Saidi
bba265ccd8 PCI: Move PCI Configuration data into devices now that we can inherit parameters.
--HG--
extra : convert_revision : bd2214b28fb46a9a9e9e204e0539be33acb548ad
2007-08-16 16:49:05 -04:00
Ali Saidi
773cb77656 Devices: Make EtherInts connect in the same way memory ports currently do.
--HG--
extra : convert_revision : 765b096785a77df9adc4791c9101b90696bd7be2
2007-08-16 16:49:02 -04:00
Ali Saidi
e9ddc7fbca Regression: fix configuration for SPARC_FS
--HG--
extra : convert_revision : 88aa9649cc1b4d8165616e98880d3d6cd2a75762
2007-08-12 19:44:04 -04:00
Vincentius Robby
ec4000e0e2 Added fastmem option.
Lets CPU accesses to physical memory bypass Bus.

--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
2007-08-08 18:43:12 -04:00
Ali Saidi
06a9f58c68 DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-08-10 16:14:01 -04:00
Steve Reinhardt
3afc625975 merge from head
--HG--
extra : convert_revision : 21f7afe2719c00744c0981212c1ee6e442238e01
2007-08-03 03:51:30 -04:00
Ali Saidi
31a9114a3d merge, no manual changes
--HG--
extra : convert_revision : 8504bddf1f73a4186cebc03c3e52e42ea38361fc
2007-08-02 15:38:06 -04:00
Gabe Black
e719a3e4c0 Fix how the "cmd" parameter is set in se.py and remove hack in x86 process initialization code.
--HG--
extra : convert_revision : 1fc741eea956ebfa4cef488eef4333d1f50617a6
2007-08-01 18:19:23 -07:00
Ali Saidi
456a4570c1 Configuration: Update the drive systems kernel as well as the testsys kernel with cmd line option.
--HG--
extra : convert_revision : 5dfb0db65452c0b7aa3e2dc2a0209e3f8e23811f
2007-08-01 17:39:16 -04:00
Steve Reinhardt
884807a68a Fix up a bunch of multilevel coherence issues.
Atomic mode seems to work.  Timing is closer but not there yet.

--HG--
extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
2007-07-15 20:11:06 -07:00
Steve Reinhardt
9172876dd7 Fix problem with unset max_loads in memtest.
Also make default 0, and make that mean run forever.

--HG--
extra : convert_revision : 3e60a52b1c5e334a9ef3d744cf7ee1d851ba4aa9
2007-07-15 14:32:55 -07:00
Steve Reinhardt
b1bdc3b3d9 Punt on old -n/-c memtest args.
Also added comments to document treespec format.

--HG--
extra : convert_revision : fa9e8f66b68b96a4efca8a7fe6e7c37367382d9d
2007-07-15 14:07:31 -07:00
Steve Reinhardt
ad560a6642 Add --force-bus option to memtest.py.
--HG--
extra : convert_revision : 101735cca426903704ff2edaff051fa7c5bfc46c
2007-07-15 13:22:49 -07:00
Steve Reinhardt
4bcfa916f1 New tree-based algorithm for creating more complex cache hierarchies.
--HG--
extra : convert_revision : de8dd4ef5dae0f3e084461e8ef7c549653e61d3f
2007-07-14 23:49:24 -07:00
Steve Reinhardt
07f091d6ed Get rid of remaining traces of obsolete CoherenceProtocol object.
--HG--
extra : convert_revision : c5555b00bef1b304a84886188ad2c0dcb4d7c5b9
2007-06-30 17:59:45 -07:00
Steve Reinhardt
9117c94f9c Get rid of coherence protocol object.
--HG--
extra : convert_revision : 4ff144342dca23af9a12a2169ca318a002654b42
2007-06-27 20:54:13 -07:00
Steve Reinhardt
83af0fdcf5 Getting closer...
configs/example/memtest.py:
    Add progress interval option.
src/base/traceflags.py:
    Add MemTest flag.
src/cpu/memtest/memtest.cc:
    Clean up tracing.
src/cpu/memtest/memtest.hh:
    Get rid of unused code.

--HG--
extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-21 11:59:17 -07:00
Steve Reinhardt
d69a763833 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

configs/example/memtest.py:
    Hand merge redundant changes.

--HG--
extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
2007-06-17 17:30:24 -07:00
Steve Reinhardt
35cf19d441 More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.

configs/example/memtest.py:
    Revamp options.
src/cpu/memtest/memtest.cc:
    No need for memory initialization.
    No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
    MemTest really doesn't want to snoop.
src/mem/bridge.cc:
    checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
    More major reorg.  Seems to work for atomic mode now,
    timing mode still broken.

--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-06-17 17:27:53 -07:00
Nathan Binkert
d14256f9ba the cmd argument is supposed to be an array of parameters, not one string
--HG--
extra : convert_revision : dffdaa94a1f28f3709515a9eeed420552d8c7b22
2007-06-10 13:57:48 -07:00
Nathan Binkert
e9936a6250 More realistic parameters
--HG--
extra : convert_revision : aaa4ea2b7c97df3d6b731e9252984b45715e9d6f
2007-06-09 22:43:08 -07:00
Ali Saidi
48133a0f04 fix SPARC....
configs/common/FSConfig.py:
    fix SPARC

--HG--
extra : convert_revision : 34a36c0f626f3fb8a1526ec194a9b0cdae32fed4
2007-06-04 12:03:38 -04:00
Nathan Binkert
35147170f9 Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-27 19:21:17 -07:00
Steve Reinhardt
9f1c104ccd memtest.py:
Make clocks more reasonable.
Fix bug in sense of options.timing flag.

configs/example/memtest.py:
    Fix bug in sense of options.timing flag.
configs/example/memtest.py:
    Make clocks more reasonable.

--HG--
extra : convert_revision : 3715697988c56e92a4da129b42026d0623f5e85e
2007-05-22 06:22:27 -07:00
Steve Reinhardt
0305159abf PhysicalMemory has vector of uniform ports instead of one special one.
configs/example/memtest.py:
    PhysicalMemory has vector of uniform ports instead of one special one.
    Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
    Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
    Add comment.

--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
2007-05-19 00:24:34 -04:00
Ali Saidi
0934f259d6 add an l2 cache option to se example config
configs/common/Options.py:
configs/example/fs.py:
    move l2 cache option to Options.py

--HG--
extra : convert_revision : 5c0071c2827f7db6d56229d5276326364b50f0c8
2007-05-15 18:06:35 -04:00
Ali Saidi
f317227b4e hopefully the final hacky change to make the bus bridge work ok
cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here

src/mem/bridge.cc:
src/mem/bridge.hh:
    hopefully the final hacky change to make the bus bridge work ok

--HG--
extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c
2007-05-15 17:39:50 -04:00
Ali Saidi
57104ea5f9 couple more bug fixes for intel nic
src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
    couple more bug fixes

--HG--
extra : convert_revision : ae5b806528c1ec06f0091e1f6e50fc0721057ddb
2007-05-14 16:37:00 -04:00
Ali Saidi
634d2e9d83 remove hit_latency and make latency do the right thing
set the latency parameter in terms of a latency
add caches to tsunami-simple configs

configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
    set the latency parameter in terms of a latency
configs/common/FSConfig.py:
    give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
    remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    add caches to tsunami-simple configs

--HG--
extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
2007-05-10 18:24:48 -04:00
Ali Saidi
0dfc29a023 fix partial writes with a functional memory hack
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached

configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
    fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
    fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
    by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier

--HG--
extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
2007-05-07 14:42:03 -04:00
Ali Saidi
6e60d5c12f add a udp stream benchmark and a udp loopback benchmark
--HG--
extra : convert_revision : 9300c67a1258e57436eba6cbdbed8fdf93fb6e59
2007-04-30 13:08:21 -04:00
Ali Saidi
e77aa3d212 make ping actually end
--HG--
extra : convert_revision : 6932d050a821abc7871bc73051688a986dcea364
2007-04-30 13:07:05 -04:00
Kevin Lim
522e59840f Fix mutex test script for latest disk image.
--HG--
extra : convert_revision : 1b0a251046674db1be8c9a2c026ff8c17f9cea06
2007-04-26 00:10:06 -04:00
Ron Dreslinski
c47804002a Fix the splash2 run script
--HG--
extra : convert_revision : 2b5f6718ac93d3d1b9b1d1b290f1ff5fa10cd0d8
2007-04-23 16:03:53 -04:00
Lisa Hsu
25e92383c8 spec-surge-client.rcS:
fix script to reflect new benchmark directory sturcture

configs/boot/spec-surge-client.rcS:
    fix script to reflect new benchmark directory sturcture

--HG--
extra : convert_revision : 45f9d8aebabd1f3f8d1e826e07840e2365511a35
2007-04-20 20:21:59 -04:00
Gabe Black
39c4ea3473 Fix mcf benchmark object so it gets the arguments it expects.
--HG--
extra : convert_revision : 47087be1f89699e9f8e0dc023abbf593bc0f6618
2007-03-22 00:10:47 -04:00
Nathan Binkert
d55b25cde6 Move all of the parameters of the Root SimObject so they are
directly configured by python.  Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.

--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-03-06 11:13:43 -08:00
Ali Saidi
82874eefca Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
2007-03-03 19:03:22 -05:00
Ali Saidi
1694c65ba1 Add Iob and remove the fake device
configs/common/FSConfig.py:
    add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy

--HG--
extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
2007-03-03 19:02:31 -05:00
Ali Saidi
36f43ff6a5 Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-03-03 17:22:47 -05:00
Gabe Black
4b4b46ea90 Keep around which input set was used for a benchmark, and make vortex work with SPARC.
--HG--
extra : convert_revision : c891435a31e81fb8294484aedf340c0c96c8afa2
2007-03-03 03:34:53 +00:00
Nathan Binkert
fa4c3d74fe Get rid of the ConsoleListener SimObject and just fold the
relevant code directly into the SimConsole object.  Now,
you can easily turn off the listen port by just specifying
0 as the port.

--HG--
extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
2007-02-21 22:14:11 -08:00
Ali Saidi
3fa5816dcf fix some checkpointing annoyances
-m works as you think it should
Ctrl-C actually ends the simulation now

--HG--
extra : convert_revision : f2269dc90d165c716459ec61f5f7b1ea3c1d4ae2
2007-01-30 18:21:42 -05:00
Gabe Black
1352e55ceb Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmemo3

src/sim/byteswap.hh:
    Hand Merge

--HG--
extra : convert_revision : 640d33ad0c416934e8a5107768e7f1dce6709ca8
2007-01-22 22:31:48 -08:00
Ali Saidi
7933aade85 add memory mapped disk device
configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
    add configuration for memory mapped disk
src/dev/sparc/SConscript:
    add memory mapped disk to sconscript

--HG--
extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
2007-01-09 22:16:49 -05:00