New tree-based algorithm for creating more complex cache hierarchies.
--HG-- extra : convert_revision : de8dd4ef5dae0f3e084461e8ef7c549653e61d3f
This commit is contained in:
Steve Reinhardt
parent
15a51d0cae
commit
4bcfa916f1
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@ -49,6 +49,10 @@ parser.add_option("-n", "--numtesters", type="int", default=8,
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metavar="N",
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help="Number of tester pseudo-CPUs [default: %default]")
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parser.add_option("-t", "--treespec", type="string",
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help="Colon-separated multilevel tree specification")
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parser.add_option("-f", "--functional", type="int", default=0,
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metavar="PCT",
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help="Target percentage of functional accesses "
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@ -69,84 +73,83 @@ if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# Should generalize this someday... would be cool to have a loop that
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# just iterates, adding a level of caching each time.
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#if options.cache_levels != 2 and options.cache_levels != 0:
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# print "Error: number of cache levels must be 0 or 2"
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# sys.exit(1)
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if options.blocking:
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num_l1_mshrs = 1
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num_l2_mshrs = 1
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else:
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num_l1_mshrs = 12
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num_l2_mshrs = 92
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block_size = 64
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# --------------------
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# Base L1 Cache
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# ====================
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if not options.treespec:
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# convert simple cache_levels option to treespec
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treespec = [options.numtesters, 1]
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numtesters = options.numtesters
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else:
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try:
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treespec = [int(x) for x in options.treespec.split(':')]
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numtesters = reduce(lambda x,y: x*y, treespec)
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except:
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print "Error parsing treespec option"
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sys.exit(1)
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class L1(BaseCache):
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latency = '1ns'
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block_size = block_size
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mshrs = num_l1_mshrs
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tgts_per_mshr = 8
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# ----------------------
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# Base L2 Cache
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# ----------------------
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class L2(BaseCache):
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block_size = block_size
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latency = '10ns'
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mshrs = num_l2_mshrs
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tgts_per_mshr = 16
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write_buffers = 8
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if options.numtesters > block_size:
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if numtesters > block_size:
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print "Error: Number of testers limited to %s because of false sharing" \
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% (block_size)
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sys.exit(1)
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cpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
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percent_functional=options.functional,
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percent_uncacheable=options.uncacheable,
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progress_interval=options.progress)
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for i in xrange(options.numtesters) ]
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if len(treespec) < 1:
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print "Error parsing treespec"
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sys.exit(1)
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# define prototype L1 cache
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proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
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latency = '1ns', tgts_per_mshr = 8)
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if options.blocking:
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proto_l1.mshrs = 1
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else:
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proto_l1.mshrs = 8
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# build a list of prototypes, one for each cache level (L1 is at end,
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# followed by the tester pseudo-cpu objects)
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prototypes = [ proto_l1,
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MemTest(atomic=options.atomic, max_loads=options.maxloads,
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percent_functional=options.functional,
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percent_uncacheable=options.uncacheable,
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progress_interval=options.progress) ]
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while len(prototypes) < len(treespec):
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# clone previous level and update params
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prev = prototypes[0]
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next = prev()
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next.size = prev.size * 4
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next.latency = prev.latency * 10
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next.assoc = prev.assoc * 2
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prototypes.insert(0, next)
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# system simulated
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system = System(cpu = cpus, funcmem = PhysicalMemory(),
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physmem = PhysicalMemory(latency = "100ns"),
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membus = Bus(clock="500MHz", width=16))
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system = System(funcmem = PhysicalMemory(),
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physmem = PhysicalMemory(latency = "100ns"))
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# l2cache & bus
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if options.cache_levels == 2:
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system.toL2Bus = Bus(clock="500MHz", width=16)
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system.l2c = L2(size='64kB', assoc=8)
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system.l2c.cpu_side = system.toL2Bus.port
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# connect l2c to membus
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system.l2c.mem_side = system.membus.port
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# add L1 caches
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for cpu in cpus:
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if options.cache_levels == 2:
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cpu.l1c = L1(size = '32kB', assoc = 4)
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cpu.test = cpu.l1c.cpu_side
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cpu.l1c.mem_side = system.toL2Bus.port
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elif options.cache_levels == 1:
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cpu.l1c = L1(size = '32kB', assoc = 4)
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cpu.test = cpu.l1c.cpu_side
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cpu.l1c.mem_side = system.membus.port
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else:
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cpu.test = system.membus.port
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system.funcmem.port = cpu.functional
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# connect memory to membus
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system.physmem.port = system.membus.port
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def make_level(spec, prototypes, attach_obj, attach_port):
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fanout = spec[0]
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parent = attach_obj # use attach obj as config parent too
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if fanout > 1:
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new_bus = Bus(clock="500MHz", width=16)
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new_bus.port = getattr(attach_obj, attach_port)
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parent.cpu_side_bus = new_bus
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attach_obj = new_bus
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attach_port = "port"
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objs = [prototypes[0]() for i in xrange(fanout)]
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if len(spec) > 1:
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# we just built caches, more levels to go
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parent.cache = objs
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for cache in objs:
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cache.mem_side = getattr(attach_obj, attach_port)
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make_level(spec[1:], prototypes[1:], cache, "cpu_side")
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else:
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# we just built the MemTest objects
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parent.cpu = objs
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for t in objs:
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t.test = getattr(attach_obj, attach_port)
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t.functional = system.funcmem.port
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make_level(treespec, prototypes, system.physmem, "port")
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# -----------------------
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# run simulation
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