29c45ccd23
The previous slower ruby latencies created a mismatch between the faster M5 cpu models and the much slower ruby memory system. Specifically smp interrupts were much slower and infrequent, as well as cpus moving in and out of spin locks. The result was many cpus were idle for large periods of time. These changes fix the latency mismatch. |
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| boot | ||
| common | ||
| example | ||
| ruby | ||
| splash2 | ||