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testers: move testers to a new directory

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This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.

--HG--
rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py
rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc
rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh
rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc
rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh
rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc
rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh
rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py
rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript
rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc
rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh
rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py
rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript
rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc
rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh
rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc
rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh
rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc
rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh
rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc
rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh
rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py
rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
This commit is contained in:
Brad Beckmann 2010-08-24 12:07:22 -07:00
parent 20b2f0ce9f
commit e983ef9e8c
28 changed files with 46 additions and 43 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
configs/example/memtest-ruby.py
View file

@ -104,17 +104,21 @@ system = System(cpu = cpus,
funcmem = PhysicalMemory(),
physmem = PhysicalMemory())
system.dmas = [ MemTest(atomic = False, \
max_loads = options.maxloads, \
issue_dmas = True, \
percent_functional = 0, \
percent_uncacheable = 0, \
progress_interval = options.progress) \
for i in xrange(options.num_dmas) ]
if options.num_dmas > 0:
dmas = [ MemTest(atomic = False, \
max_loads = options.maxloads, \
issue_dmas = True, \
percent_functional = 0, \
percent_uncacheable = 0, \
progress_interval = options.progress) \
for i in xrange(options.num_dmas) ]
system.dma_devices = dmas
else:
dmas = []
system.ruby = Ruby.create_system(options, \
system.physmem, \
dma_devices = system.dmas)
system, \
dma_devices = dmas)
#
# The tester is most effective when randomization is turned on and
@ -131,7 +135,7 @@ for (i, cpu) in enumerate(cpus):
cpu.test = system.ruby.cpu_ruby_ports[i].port
cpu.functional = system.funcmem.port
for (i, dma) in enumerate(system.dmas):
for (i, dma) in enumerate(dmas):
#
# Tie the dma memtester ports to the correct functional port
# Note that the test port has already been connected to the dma_sequencer

6
configs/example/determ_test.py → configs/example/ruby_direct_test.py
View file

@ -69,7 +69,7 @@ if args:
sys.exit(1)
#
# Select the directed generator
# Select the direct test generator
#
if options.test_type == "SeriesGetx":
generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
@ -80,7 +80,7 @@ elif options.test_type == "SeriesGets":
elif options.test_type == "Invalidate":
generator = InvalidateGenerator(num_cpus = options.num_cpus)
else:
print "Error: unknown directed generator"
print "Error: unknown direct test generator"
sys.exit(1)
#
@ -95,7 +95,7 @@ system = System(physmem = PhysicalMemory())
#
system.tester = RubyDirectedTester(requests_to_complete = \
options.requests,
generator = generator)
generator = generator)
system.ruby = Ruby.create_system(options, system)

2
configs/example/rubytest.py
View file

@ -90,7 +90,7 @@ tester = RubyTester(checks_to_complete = options.checks,
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
system = System(physmem = PhysicalMemory())
system = System(tester = tester, physmem = PhysicalMemory())
system.ruby = Ruby.create_system(options, system)

5
configs/ruby/MOESI_hammer.py
View file

@ -186,10 +186,9 @@ def create_system(options, system, piobus, dma_devices):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
system.dma_cntrl.dma_sequencer.port = dma_device.test
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
else:
system.dma_cntrl.dma_sequencer.port = dma_device.dma
dma_cntrl.dma_sequencer.port = dma_device.dma
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
if options.recycle_latency:

2
src/cpu/directedtest/DirectedGenerator.cc → src/cpu/testers/directedtest/DirectedGenerator.cc
View file

@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
DirectedGenerator::DirectedGenerator(const Params *p)
: SimObject(p)

4
src/cpu/directedtest/DirectedGenerator.hh → src/cpu/testers/directedtest/DirectedGenerator.hh
View file

@ -29,8 +29,8 @@
#ifndef __CPU_DIRECTEDTEST_DIRECTEDGENERATOR_HH__
#define __CPU_DIRECTEDTEST_DIRECTEDGENERATOR_HH__
#include "cpu/directedtest/DirectedGenerator.hh"
#include "cpu/directedtest/RubyDirectedTester.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "params/DirectedGenerator.hh"
#include "sim/sim_object.hh"

6
src/cpu/directedtest/InvalidateGenerator.cc → src/cpu/testers/directedtest/InvalidateGenerator.cc
View file

@ -27,9 +27,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/directedtest/RubyDirectedTester.hh"
#include "cpu/directedtest/DirectedGenerator.hh"
#include "cpu/directedtest/InvalidateGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/InvalidateGenerator.hh"
InvalidateGenerator::InvalidateGenerator(const Params *p)
: DirectedGenerator(p)

4
src/cpu/directedtest/InvalidateGenerator.hh → src/cpu/testers/directedtest/InvalidateGenerator.hh
View file

@ -35,8 +35,8 @@
#ifndef __CPU_DIRECTEDTEST_INVALIDATEGENERATOR_HH__
#define __CPU_DIRECTEDTEST_INVALIDATEGENERATOR_HH__
#include "cpu/directedtest/RubyDirectedTester.hh"
#include "cpu/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "mem/protocol/InvalidateGeneratorStatus.hh"
#include "params/InvalidateGenerator.hh"

4
src/cpu/directedtest/RubyDirectedTester.cc → src/cpu/testers/directedtest/RubyDirectedTester.cc
View file

@ -27,8 +27,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/directedtest/RubyDirectedTester.hh"
#include "cpu/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "mem/ruby/eventqueue/RubyEventQueue.hh"
#include "sim/sim_exit.hh"

0
src/cpu/directedtest/RubyDirectedTester.hh → src/cpu/testers/directedtest/RubyDirectedTester.hh
View file

0
src/cpu/directedtest/RubyDirectedTester.py → src/cpu/testers/directedtest/RubyDirectedTester.py
View file

0
src/cpu/directedtest/SConscript → src/cpu/testers/directedtest/SConscript
View file

6
src/cpu/directedtest/SeriesRequestGenerator.cc → src/cpu/testers/directedtest/SeriesRequestGenerator.cc
View file

@ -27,9 +27,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/directedtest/RubyDirectedTester.hh"
#include "cpu/directedtest/DirectedGenerator.hh"
#include "cpu/directedtest/SeriesRequestGenerator.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
: DirectedGenerator(p)

4
src/cpu/directedtest/SeriesRequestGenerator.hh → src/cpu/testers/directedtest/SeriesRequestGenerator.hh
View file

@ -35,8 +35,8 @@
#ifndef __CPU_DIRECTEDTEST_SERIESREQUESTGENERATOR_HH__
#define __CPU_DIRECTEDTEST_SERIESREQUESTGENERATOR_HH__
#include "cpu/directedtest/RubyDirectedTester.hh"
#include "cpu/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "mem/protocol/SeriesRequestGeneratorStatus.hh"
#include "params/SeriesRequestGenerator.hh"

0
src/cpu/memtest/MemTest.py → src/cpu/testers/memtest/MemTest.py
View file

0
src/cpu/memtest/SConscript → src/cpu/testers/memtest/SConscript
View file

2
src/cpu/memtest/memtest.cc → src/cpu/testers/memtest/memtest.cc
View file

@ -38,7 +38,7 @@
#include "base/misc.hh"
#include "base/statistics.hh"
#include "cpu/memtest/memtest.hh"
#include "cpu/testers/memtest/memtest.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/packet.hh"

0
src/cpu/memtest/memtest.hh → src/cpu/testers/memtest/memtest.hh
View file

2
src/cpu/rubytest/Check.cc → src/cpu/testers/rubytest/Check.cc
View file

@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/rubytest/Check.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/system/System.hh"

2
src/cpu/rubytest/Check.hh → src/cpu/testers/rubytest/Check.hh
View file

@ -32,7 +32,7 @@
#include <iostream>
#include "cpu/rubytest/RubyTester.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
#include "mem/protocol/AccessModeType.hh"
#include "mem/protocol/TesterStatus.hh"
#include "mem/ruby/common/Address.hh"

6
src/cpu/rubytest/CheckTable.cc → src/cpu/testers/rubytest/CheckTable.cc
View file

@ -28,9 +28,9 @@
*/
#include "base/intmath.hh"
#include "cpu/rubytest/Check.hh"
#include "cpu/rubytest/CheckTable.hh"
#include "cpu/rubytest/CheckTable.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "cpu/testers/rubytest/CheckTable.hh"
#include "cpu/testers/rubytest/CheckTable.hh"
CheckTable::CheckTable(int _num_cpu_sequencers, RubyTester* _tester)
: m_num_cpu_sequencers(_num_cpu_sequencers), m_tester_ptr(_tester)

0
src/cpu/rubytest/CheckTable.hh → src/cpu/testers/rubytest/CheckTable.hh
View file

4
src/cpu/rubytest/RubyTester.cc → src/cpu/testers/rubytest/RubyTester.cc
View file

@ -27,8 +27,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/rubytest/Check.hh"
#include "cpu/rubytest/RubyTester.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/eventqueue/RubyEventQueue.hh"

2
src/cpu/rubytest/RubyTester.hh → src/cpu/testers/rubytest/RubyTester.hh
View file

@ -34,7 +34,7 @@
#include <vector>
#include <string>
#include "cpu/rubytest/CheckTable.hh"
#include "cpu/testers/rubytest/CheckTable.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/ruby/common/DataBlock.hh"

0
src/cpu/rubytest/RubyTester.py → src/cpu/testers/rubytest/RubyTester.py
View file

0
src/cpu/rubytest/SConscript → src/cpu/testers/rubytest/SConscript
View file

2
src/mem/ruby/system/RubyPort.cc
View file

@ -26,7 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/rubytest/RubyTester.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
#include "mem/physical.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/RubyPort.hh"

2
src/mem/ruby/system/Sequencer.cc
View file

@ -27,7 +27,7 @@
*/
#include "base/str.hh"
#include "cpu/rubytest/RubyTester.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
#include "mem/protocol/CacheMsg.hh"
#include "mem/protocol/Protocol.hh"
#include "mem/protocol/Protocol.hh"