MOESI_hammer: fixed bug for dma reads in single cpu systems
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c13640a89c
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20b2f0ce9f
1 changed files with 29 additions and 14 deletions
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@ -97,6 +97,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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Other_GETS, desc="A GetS from another processor";
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Merged_GETS, desc="A Merged GetS from another processor";
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Other_GETS_No_Mig, desc="A GetS from another processor";
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NC_DMA_GETS, desc="special GetS when only DMA exists";
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Invalidate, desc="Invalidate block";
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// Responses
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@ -291,14 +292,18 @@ machine(L1Cache, "AMD Hammer-like protocol")
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} else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) {
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trigger(Event:Merged_GETS, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:GETS) {
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if (isCacheTagPresent(in_msg.Address)) {
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if (getCacheEntry(in_msg.Address).AtomicAccessed && no_mig_atomic) {
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trigger(Event:Other_GETS_No_Mig, in_msg.Address);
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if (machineCount(MachineType:L1Cache) > 1) {
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if (isCacheTagPresent(in_msg.Address)) {
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if (getCacheEntry(in_msg.Address).AtomicAccessed && no_mig_atomic) {
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trigger(Event:Other_GETS_No_Mig, in_msg.Address);
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} else {
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trigger(Event:Other_GETS, in_msg.Address);
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}
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} else {
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trigger(Event:Other_GETS, in_msg.Address);
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}
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} else {
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trigger(Event:Other_GETS, in_msg.Address);
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trigger(Event:NC_DMA_GETS, in_msg.Address);
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}
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} else if (in_msg.Type == CoherenceRequestType:INV) {
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trigger(Event:Invalidate, in_msg.Address);
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@ -945,7 +950,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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zz_recycleMandatoryQueue;
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}
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transition({IT, ST, OT, MT, MMT}, {Other_GETX, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) {
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transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) {
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// stall
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}
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@ -1095,7 +1100,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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rr_deallocateL2CacheBlock;
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}
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transition(I, {Other_GETX, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
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transition(I, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
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f_sendAck;
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l_popForwardQueue;
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}
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@ -1122,7 +1127,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(S, {Other_GETS, Other_GETS_No_Mig}) {
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transition(S, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
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ff_sendAckShared;
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l_popForwardQueue;
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}
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@ -1152,7 +1157,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(O, {Other_GETS, Other_GETS_No_Mig}) {
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transition(O, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
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ee_sendDataShared;
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l_popForwardQueue;
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}
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@ -1189,6 +1194,11 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(MM, NC_DMA_GETS) {
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c_sendExclusiveData;
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l_popForwardQueue;
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}
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transition(MM, Other_GETS_No_Mig, O) {
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ee_sendDataShared;
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l_popForwardQueue;
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@ -1226,6 +1236,11 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(M, NC_DMA_GETS) {
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ee_sendDataShared;
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l_popForwardQueue;
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}
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transition(M, Merged_GETS, O) {
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em_sendDataSharedMultiple;
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l_popForwardQueue;
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@ -1233,7 +1248,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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// Transitions from IM
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transition(IM, {Other_GETX, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
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transition(IM, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
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f_sendAck;
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l_popForwardQueue;
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}
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@ -1260,7 +1275,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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}
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// Transitions from SM
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transition(SM, {Other_GETS, Other_GETS_No_Mig}) {
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transition(SM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
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ff_sendAckShared;
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l_popForwardQueue;
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}
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@ -1305,7 +1320,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(OM, {Other_GETS, Other_GETS_No_Mig}) {
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transition(OM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) {
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ee_sendDataShared;
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l_popForwardQueue;
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}
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@ -1330,7 +1345,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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// Transitions from IS
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transition(IS, {Other_GETX, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
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transition(IS, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
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f_sendAck;
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l_popForwardQueue;
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}
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@ -1448,7 +1463,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition({OI, MI}, {Other_GETS, Other_GETS_No_Mig}, OI) {
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transition({OI, MI}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}, OI) {
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q_sendDataFromTBEToCache;
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l_popForwardQueue;
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}
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@ -1471,7 +1486,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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}
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// Transitions from II
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transition(II, {Other_GETS, Other_GETS_No_Mig, Other_GETX, Invalidate}, II) {
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transition(II, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Other_GETX, Invalidate}, II) {
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f_sendAck;
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l_popForwardQueue;
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}
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