PCI: Move PCI Configuration data into devices now that we can inherit parameters.
--HG-- extra : convert_revision : bd2214b28fb46a9a9e9e204e0539be33acb548ad
This commit is contained in:
Ali Saidi
parent
773cb77656
commit
bba265ccd8
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@ -40,8 +40,7 @@ class CowIdeDisk(IdeDisk):
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def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(configdata=NSGigEPciData(),
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pci_bus=0, pci_dev=1, pci_func=0)
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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@ -29,7 +29,7 @@
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from Pci import PciDevice, PciConfigData
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from Pci import PciDevice
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class EtherObject(SimObject):
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type = 'EtherObject'
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@ -79,8 +79,6 @@ class IGbE(EtherDevice):
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tx_desc_cache_size = Param.Int(64,
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"Number of enteries in the rx descriptor cache")
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clock = Param.Clock('500MHz', "Clock speed of the device")
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class IGbEPciData(PciConfigData):
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VendorID = 0x8086
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DeviceID = 0x1075
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SubsystemID = 0x1008
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@ -125,7 +123,13 @@ class EtherDevBase(EtherDevice):
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tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
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rss = Param.Bool(False, "Receive Side Scaling")
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class NSGigEPciData(PciConfigData):
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class NSGigE(EtherDevBase):
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type = 'NSGigE'
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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VendorID = 0x100B
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DeviceID = 0x0022
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Status = 0x0290
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@ -145,34 +149,7 @@ class NSGigEPciData(PciConfigData):
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BAR0Size = '256B'
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BAR1Size = '4kB'
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class NSGigE(EtherDevBase):
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type = 'NSGigE'
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dma_data_free = Param.Bool(False, "DMA of Data is free")
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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configdata = NSGigEPciData()
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class SinicPciData(PciConfigData):
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VendorID = 0x1291
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DeviceID = 0x1293
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000000
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '64kB'
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class Sinic(EtherDevBase):
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type = 'Sinic'
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@ -191,5 +168,22 @@ class Sinic(EtherDevBase):
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delay_copy = Param.Bool(False, "Delayed copy transmit")
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virtual_addr = Param.Bool(False, "Virtual addressing")
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configdata = SinicPciData()
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VendorID = 0x1291
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DeviceID = 0x1293
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000000
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '64kB'
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@ -28,11 +28,20 @@
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from m5.SimObject import SimObject
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from m5.params import *
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from Pci import PciDevice, PciConfigData
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from Pci import PciDevice
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class IdeID(Enum): vals = ['master', 'slave']
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class IdeControllerPciData(PciConfigData):
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class IdeDisk(SimObject):
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type = 'IdeDisk'
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delay = Param.Latency('1us', "Fixed disk delay in microseconds")
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driveID = Param.IdeID('master', "Drive ID")
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image = Param.DiskImage("Disk image")
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class IdeController(PciDevice):
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type = 'IdeController'
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disks = VectorParam.IdeDisk("IDE disks attached to this controller")
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VendorID = 0x8086
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DeviceID = 0x7111
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Command = 0x0
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@ -55,14 +64,3 @@ class IdeControllerPciData(PciConfigData):
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BAR3Size = '4B'
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BAR4Size = '16B'
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class IdeDisk(SimObject):
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type = 'IdeDisk'
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delay = Param.Latency('1us', "Fixed disk delay in microseconds")
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driveID = Param.IdeID('master', "Drive ID")
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image = Param.DiskImage("Disk image")
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class IdeController(PciDevice):
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type = 'IdeController'
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disks = VectorParam.IdeDisk("IDE disks attached to this controller")
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configdata =IdeControllerPciData()
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@ -31,8 +31,23 @@ from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice, DmaDevice, PioDevice
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class PciConfigData(SimObject):
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type = 'PciConfigData'
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class PciConfigAll(PioDevice):
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type = 'PciConfigAll'
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pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
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bus = Param.UInt8(0x00, "PCI bus to act as config space for")
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size = Param.MemorySize32('16MB', "Size of config space")
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class PciDevice(DmaDevice):
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type = 'PciDevice'
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abstract = True
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config = Port(Self.pio.peerObj.port, "PCI configuration space port")
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pci_bus = Param.Int("PCI bus")
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pci_dev = Param.Int("PCI device number")
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pci_func = Param.Int("PCI function code")
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pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
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config_latency = Param.Latency('20ns', "Config read or write latency")
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VendorID = Param.UInt16("Vendor ID")
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DeviceID = Param.UInt16("Device ID")
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Command = Param.UInt16(0, "Command")
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@ -68,20 +83,4 @@ class PciConfigData(SimObject):
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MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
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MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
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class PciConfigAll(PioDevice):
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type = 'PciConfigAll'
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pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
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bus = Param.UInt8(0x00, "PCI bus to act as config space for")
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size = Param.MemorySize32('16MB', "Size of config space")
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class PciDevice(DmaDevice):
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type = 'PciDevice'
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abstract = True
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config = Port(Self.pio.peerObj.port, "PCI configuration space port")
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pci_bus = Param.Int("PCI bus")
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pci_dev = Param.Int("PCI device number")
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pci_func = Param.Int("PCI function code")
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pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
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configdata = Param.PciConfigData(Parent.any, "PCI Config data")
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config_latency = Param.Latency('20ns', "Config read or write latency")
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@ -48,7 +48,6 @@
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#include "dev/alpha/tsunamireg.h"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "params/PciConfigData.hh"
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#include "sim/byteswap.hh"
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#include "sim/core.hh"
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@ -82,21 +81,57 @@ PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp,
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PciDev::PciDev(const Params *p)
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: DmaDevice(p), plat(p->platform), configData(p->configdata),
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pioDelay(p->pio_latency), configDelay(p->config_latency),
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configPort(NULL)
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: DmaDevice(p), plat(p->platform), pioDelay(p->pio_latency),
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configDelay(p->config_latency), configPort(NULL)
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{
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// copy the config data from the PciConfigData object
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if (configData) {
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memcpy(config.data, configData->config.data, sizeof(config.data));
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memcpy(BARSize, configData->BARSize, sizeof(BARSize));
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} else
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panic("NULL pointer to configuration data");
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config.vendor = htole(p->VendorID);
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config.device = htole(p->DeviceID);
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config.command = htole(p->Command);
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config.status = htole(p->Status);
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config.revision = htole(p->Revision);
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config.progIF = htole(p->ProgIF);
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config.subClassCode = htole(p->SubClassCode);
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config.classCode = htole(p->ClassCode);
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config.cacheLineSize = htole(p->CacheLineSize);
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config.latencyTimer = htole(p->LatencyTimer);
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config.headerType = htole(p->HeaderType);
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config.bist = htole(p->BIST);
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config.baseAddr[0] = htole(p->BAR0);
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config.baseAddr[1] = htole(p->BAR1);
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config.baseAddr[2] = htole(p->BAR2);
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config.baseAddr[3] = htole(p->BAR3);
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config.baseAddr[4] = htole(p->BAR4);
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config.baseAddr[5] = htole(p->BAR5);
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config.cardbusCIS = htole(p->CardbusCIS);
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config.subsystemVendorID = htole(p->SubsystemVendorID);
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config.subsystemID = htole(p->SubsystemID);
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config.expansionROM = htole(p->ExpansionROM);
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config.reserved0 = 0;
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config.reserved1 = 0;
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config.interruptLine = htole(p->InterruptLine);
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config.interruptPin = htole(p->InterruptPin);
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config.minimumGrant = htole(p->MinimumGrant);
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config.maximumLatency = htole(p->MaximumLatency);
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BARSize[0] = p->BAR0Size;
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BARSize[1] = p->BAR1Size;
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BARSize[2] = p->BAR2Size;
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BARSize[3] = p->BAR3Size;
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BARSize[4] = p->BAR4Size;
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BARSize[5] = p->BAR5Size;
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for (int i = 0; i < 6; ++i) {
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uint32_t barsize = BARSize[i];
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if (barsize != 0 && !isPowerOf2(barsize)) {
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fatal("BAR %d size %d is not a power of 2\n", i, BARSize[i]);
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}
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}
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memset(BARAddrs, 0, sizeof(BARAddrs));
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plat->registerPciDevice(0, p->pci_dev, p->pci_func,
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letoh(configData->config.interruptLine));
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letoh(config.interruptLine));
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}
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void
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@ -304,53 +339,3 @@ PciDev::unserialize(Checkpoint *cp, const std::string §ion)
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}
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PciConfigData *
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PciConfigDataParams::create()
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{
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PciConfigData *data = new PciConfigData(name);
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data->config.vendor = htole(VendorID);
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data->config.device = htole(DeviceID);
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data->config.command = htole(Command);
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data->config.status = htole(Status);
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data->config.revision = htole(Revision);
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data->config.progIF = htole(ProgIF);
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data->config.subClassCode = htole(SubClassCode);
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data->config.classCode = htole(ClassCode);
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data->config.cacheLineSize = htole(CacheLineSize);
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data->config.latencyTimer = htole(LatencyTimer);
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data->config.headerType = htole(HeaderType);
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data->config.bist = htole(BIST);
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data->config.baseAddr[0] = htole(BAR0);
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data->config.baseAddr[1] = htole(BAR1);
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data->config.baseAddr[2] = htole(BAR2);
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data->config.baseAddr[3] = htole(BAR3);
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data->config.baseAddr[4] = htole(BAR4);
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data->config.baseAddr[5] = htole(BAR5);
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data->config.cardbusCIS = htole(CardbusCIS);
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data->config.subsystemVendorID = htole(SubsystemVendorID);
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data->config.subsystemID = htole(SubsystemID);
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data->config.expansionROM = htole(ExpansionROM);
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data->config.interruptLine = htole(InterruptLine);
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data->config.interruptPin = htole(InterruptPin);
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data->config.minimumGrant = htole(MinimumGrant);
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data->config.maximumLatency = htole(MaximumLatency);
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data->BARSize[0] = BAR0Size;
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data->BARSize[1] = BAR1Size;
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data->BARSize[2] = BAR2Size;
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data->BARSize[3] = BAR3Size;
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data->BARSize[4] = BAR4Size;
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data->BARSize[5] = BAR5Size;
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for (int i = 0; i < 6; ++i) {
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uint32_t barsize = data->BARSize[i];
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if (barsize != 0 && !isPowerOf2(barsize)) {
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fatal("%s: BAR %d size %d is not a power of 2\n",
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name, i, data->BARSize[i]);
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}
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}
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return data;
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}
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@ -52,30 +52,6 @@
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#define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
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/**
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* This class encapulates the first 64 bytes of a singles PCI
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* devices config space that in configured by the configuration file.
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*/
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class PciConfigData : public SimObject
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{
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public:
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/**
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* Constructor to initialize the devices config space to 0.
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*/
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PciConfigData(const std::string &name)
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: SimObject(name)
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{
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std::memset(config.data, 0, sizeof(config.data));
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std::memset(BARSize, 0, sizeof(BARSize));
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}
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/** The first 64 bytes */
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PCIConfig config;
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/** The size of the BARs */
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uint32_t BARSize[6];
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};
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/**
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* PCI device, base implementation is only config space.
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@ -114,10 +90,7 @@ class PciDev : public DmaDevice
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}
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protected:
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/** The current config space. Unlike the PciConfigData this is
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* updated during simulation while continues to reflect what was
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* in the config file.
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*/
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/** The current config space. */
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PCIConfig config;
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/** The size of the BARs */
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@ -174,7 +147,6 @@ class PciDev : public DmaDevice
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protected:
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Platform *plat;
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PciConfigData *configData;
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Tick pioDelay;
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Tick configDelay;
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PciConfigPort *configPort;
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@ -202,15 +174,15 @@ class PciDev : public DmaDevice
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void
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intrPost()
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{ plat->postPciInt(letoh(configData->config.interruptLine)); }
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{ plat->postPciInt(letoh(config.interruptLine)); }
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void
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intrClear()
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{ plat->clearPciInt(letoh(configData->config.interruptLine)); }
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{ plat->clearPciInt(letoh(config.interruptLine)); }
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uint8_t
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interruptLine()
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{ return letoh(configData->config.interruptLine); }
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{ return letoh(config.interruptLine); }
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/** return the address ranges that this device responds to.
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* @params range_list range list to populate with ranges
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