X86: Add L1 caches for the TLB walkers.
Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.
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4b4cd0303e
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119f5f8e94
4 changed files with 29 additions and 9 deletions
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@ -43,8 +43,14 @@ def config_cache(options, system):
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for i in xrange(options.num_cpus):
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if options.caches:
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system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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if buildEnv['TARGET_ISA'] == 'x86':
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system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'),
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PageTableWalkerCache(),
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PageTableWalkerCache())
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else:
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system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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if options.l2cache:
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system.cpu[i].connectMemPorts(system.tol2bus)
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else:
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@ -42,6 +42,14 @@ class L2Cache(BaseCache):
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mshrs = 20
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tgts_per_mshr = 12
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class PageTableWalkerCache(BaseCache):
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assoc = 2
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block_size = 64
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latency = '1ns'
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mshrs = 10
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size = '1kB'
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tgts_per_mshr = 12
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class IOCache(BaseCache):
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assoc = 8
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block_size = 64
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@ -166,7 +166,7 @@ class BaseCPU(MemObject):
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if p != 'physmem_port':
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exec('self.%s = bus.port' % p)
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def addPrivateSplitL1Caches(self, ic, dc):
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def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
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assert(len(self._mem_ports) < 8)
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self.icache = ic
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self.dcache = dc
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@ -174,13 +174,19 @@ class BaseCPU(MemObject):
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self.dcache_port = dc.cpu_side
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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if buildEnv['FULL_SYSTEM']:
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if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
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self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
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if buildEnv['TARGET_ISA'] == 'x86':
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self.itb_walker_cache = iwc
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self.dtb_walker_cache = dwc
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self.itb.walker.port = iwc.cpu_side
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self.dtb.walker.port = dwc.cpu_side
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self._mem_ports += ["itb_walker_cache.mem_side", \
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"dtb_walker_cache.mem_side"]
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self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
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elif buildEnv['TARGET_ISA'] == 'arm':
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self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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self.addPrivateSplitL1Caches(ic, dc)
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
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self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
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self.toL2Bus = Bus()
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self.connectMemPorts(self.toL2Bus)
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self.l2cache = l2c
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@ -141,7 +141,7 @@ class DerivO3CPU(BaseCPU):
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smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
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smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
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def addPrivateSplitL1Caches(self, ic, dc):
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BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
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def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
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BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
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self.icache.tgts_per_mshr = 20
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self.dcache.tgts_per_mshr = 20
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