ruby: Disable migratory sharing for token and hammer
This patch allows one to disable migratory sharing for those cache blocks that are accessed by atomic requests. While the implementations are different between the token and hammer protocols, the motivation is the same. For Alpha, LLSC semantics expect that normal loads do not unlock cache blocks that have been locked by LL accesses. Therefore, locked blocks should not transfer write permissions when responding to these load requests. Instead, only they only transfer read permissions so that the subsequent SC access can possibly succeed.
This commit is contained in:
Brad Beckmann
parent
bcdd19df03
commit
72044e3f5a
4 changed files with 106 additions and 40 deletions
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@ -51,7 +51,9 @@ def define_options(parser):
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help="Token_CMP: cycles until issuing again");
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parser.add_option("--disable-dyn-timeouts", action="store_true",
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help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
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parser.add_option("--allow-atomic-migration", action="store_true",
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help="allow migratory sharing for atomic only accessed blocks")
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def create_system(options, system, piobus, dma_devices):
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if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
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@ -111,7 +113,9 @@ def create_system(options, system, piobus, dma_devices):
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fixed_timeout_latency = \
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options.timeout_latency,
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dynamic_timeout_enabled = \
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not options.disable_dyn_timeouts)
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not options.disable_dyn_timeouts,
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no_mig_atomic = not \
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options.allow_atomic_migration)
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exec("system.l1_cntrl%d = l1_cntrl" % i)
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#
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@ -44,7 +44,8 @@ class L2Cache(RubyCache):
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latency = 10
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def define_options(parser):
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return
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parser.add_option("--allow-atomic-migration", action="store_true",
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help="allow migratory sharing for atomic only accessed blocks")
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def create_system(options, system, piobus, dma_devices):
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@ -91,7 +92,9 @@ def create_system(options, system, piobus, dma_devices):
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sequencer = cpu_seq,
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L1IcacheMemory = l1i_cache,
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L1DcacheMemory = l1d_cache,
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L2cacheMemory = l2_cache)
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L2cacheMemory = l2_cache,
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no_mig_atomic = not \
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options.allow_atomic_migration)
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exec("system.l1_cntrl%d = l1_cntrl" % i)
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#
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@ -42,7 +42,8 @@ machine(L1Cache, "Token protocol")
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int l1_response_latency = 2,
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int retry_threshold = 1,
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int fixed_timeout_latency = 100,
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bool dynamic_timeout_enabled = true
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bool dynamic_timeout_enabled = true,
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bool no_mig_atomic = true
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{
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// From this node's L1 cache TO the network
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@ -92,6 +93,7 @@ machine(L1Cache, "Token protocol")
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Load, desc="Load request from the processor";
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Ifetch, desc="I-fetch request from the processor";
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Store, desc="Store request from the processor";
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Atomic, desc="Atomic request from the processor";
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L1_Replacement, desc="L1 Replacement";
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// Responses
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@ -120,7 +122,7 @@ machine(L1Cache, "Token protocol")
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Use_TimeoutStarverX, desc="Timeout";
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Use_TimeoutStarverS, desc="Timeout";
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Use_TimeoutNoStarvers, desc="Timeout";
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Use_TimeoutNoStarvers_NoMig, desc="Timeout Don't Migrate";
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}
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// TYPES
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@ -143,6 +145,7 @@ machine(L1Cache, "Token protocol")
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bool WentPersistent, default="false", desc="Request went persistent";
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bool ExternalResponse, default="false", desc="Response came from an external controller";
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bool IsAtomic, default="false", desc="Request was an atomic request";
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AccessType AccessType, desc="Type of request (used for profiling)";
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Time IssueTime, desc="Time the request was issued";
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@ -361,8 +364,14 @@ machine(L1Cache, "Token protocol")
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return Event:Load;
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} else if (type == CacheRequestType:IFETCH) {
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return Event:Ifetch;
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} else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
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} else if (type == CacheRequestType:ST) {
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return Event:Store;
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} else if (type == CacheRequestType:ATOMIC) {
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if (no_mig_atomic) {
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return Event:Atomic;
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} else {
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return Event:Store;
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}
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} else {
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error("Invalid CacheRequestType");
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}
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@ -422,13 +431,16 @@ machine(L1Cache, "Token protocol")
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if (persistentTable.isLocked(useTimerTable.readyAddress()) && (persistentTable.findSmallest(useTimerTable.readyAddress()) != machineID)) {
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if (persistentTable.typeOfSmallest(useTimerTable.readyAddress()) == AccessType:Write) {
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trigger(Event:Use_TimeoutStarverX, useTimerTable.readyAddress());
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}
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else {
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} else {
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trigger(Event:Use_TimeoutStarverS, useTimerTable.readyAddress());
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}
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}
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else {
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trigger(Event:Use_TimeoutNoStarvers, useTimerTable.readyAddress());
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} else {
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assert(L1_TBEs.isPresent(useTimerTable.readyAddress()));
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if (no_mig_atomic && L1_TBEs[useTimerTable.readyAddress()].IsAtomic) {
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trigger(Event:Use_TimeoutNoStarvers_NoMig, useTimerTable.readyAddress());
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} else {
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trigger(Event:Use_TimeoutNoStarvers, useTimerTable.readyAddress());
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}
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}
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}
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}
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@ -1245,6 +1257,9 @@ machine(L1Cache, "Token protocol")
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peek(mandatoryQueue_in, CacheMsg) {
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L1_TBEs[address].PC := in_msg.ProgramCounter;
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L1_TBEs[address].AccessType := cache_request_type_to_access_type(in_msg.Type);
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if (in_msg.Type == CacheRequestType:ATOMIC) {
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L1_TBEs[address].IsAtomic := true;
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}
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L1_TBEs[address].Prefetch := in_msg.Prefetch;
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L1_TBEs[address].AccessMode := in_msg.AccessMode;
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}
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@ -1444,7 +1459,7 @@ machine(L1Cache, "Token protocol")
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zz_recycleMandatoryQueue;
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}
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transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, Store) {
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transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, {Store, Atomic}) {
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zz_recycleMandatoryQueue;
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}
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@ -1475,7 +1490,7 @@ machine(L1Cache, "Token protocol")
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k_popMandatoryQueue;
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}
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transition(NP, Store, IM) {
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transition(NP, {Store, Atomic}, IM) {
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ii_allocateL1DCacheBlock;
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i_allocateTBE;
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b_issueWriteRequest;
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@ -1511,7 +1526,7 @@ machine(L1Cache, "Token protocol")
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k_popMandatoryQueue;
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}
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transition(I, Store, IM) {
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transition(I, {Store, Atomic}, IM) {
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i_allocateTBE;
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b_issueWriteRequest;
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uu_profileMiss;
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@ -1570,7 +1585,7 @@ machine(L1Cache, "Token protocol")
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k_popMandatoryQueue;
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}
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transition(S, Store, SM) {
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transition(S, {Store, Atomic}, SM) {
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i_allocateTBE;
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b_issueWriteRequest;
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uu_profileMiss;
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@ -1646,7 +1661,7 @@ machine(L1Cache, "Token protocol")
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k_popMandatoryQueue;
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}
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transition(O, Store, OM) {
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transition(O, {Store, Atomic}, OM) {
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i_allocateTBE;
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b_issueWriteRequest;
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uu_profileMiss;
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@ -1723,7 +1738,17 @@ machine(L1Cache, "Token protocol")
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k_popMandatoryQueue;
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}
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transition({MM, MM_W}, Store) {
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transition({MM_W}, {Store, Atomic}) {
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hh_store_hit;
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k_popMandatoryQueue;
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}
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transition(MM, Store) {
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hh_store_hit;
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k_popMandatoryQueue;
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}
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transition(MM, Atomic, M) {
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hh_store_hit;
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k_popMandatoryQueue;
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}
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@ -1755,12 +1780,16 @@ machine(L1Cache, "Token protocol")
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l_popPersistentQueue;
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}
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transition(MM_W, Use_TimeoutNoStarvers, MM) {
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s_deallocateTBE;
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jj_unsetUseTimer;
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}
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transition(MM_W, Use_TimeoutNoStarvers_NoMig, M) {
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s_deallocateTBE;
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jj_unsetUseTimer;
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}
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// Transitions from Dirty Exclusive
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transition({M, M_W}, {Load, Ifetch}) {
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h_load_hit;
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@ -1772,11 +1801,21 @@ machine(L1Cache, "Token protocol")
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k_popMandatoryQueue;
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}
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transition(M, Atomic) {
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hh_store_hit;
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k_popMandatoryQueue;
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}
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transition(M_W, Store, MM_W) {
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hh_store_hit;
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k_popMandatoryQueue;
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}
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transition(M_W, Atomic) {
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hh_store_hit;
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k_popMandatoryQueue;
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}
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transition(M, L1_Replacement, I) {
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c_ownedReplacement;
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gg_deallocateL1CacheBlock;
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@ -1825,7 +1864,7 @@ machine(L1Cache, "Token protocol")
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}
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// someone unlocked during timeout
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transition(M_W, Use_TimeoutNoStarvers, M) {
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transition(M_W, {Use_TimeoutNoStarvers, Use_TimeoutNoStarvers_NoMig}, M) {
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s_deallocateTBE;
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jj_unsetUseTimer;
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}
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@ -2065,7 +2104,7 @@ machine(L1Cache, "Token protocol")
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k_popMandatoryQueue;
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}
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transition(I_L, Store, IM_L) {
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transition(I_L, {Store, Atomic}, IM_L) {
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ii_allocateL1DCacheBlock;
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i_allocateTBE;
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b_issueWriteRequest;
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@ -2076,7 +2115,7 @@ machine(L1Cache, "Token protocol")
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// Transitions from S_L
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transition(S_L, Store, SM_L) {
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transition(S_L, {Store, Atomic}, SM_L) {
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i_allocateTBE;
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b_issueWriteRequest;
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uu_profileMiss;
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@ -40,7 +40,8 @@ machine(L1Cache, "AMD Hammer-like protocol")
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CacheMemory * L2cacheMemory,
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int cache_response_latency = 10,
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int issue_latency = 2,
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int l2_cache_hit_latency = 10
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int l2_cache_hit_latency = 10,
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bool no_mig_atomic = true
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{
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// NETWORK BUFFERS
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@ -94,6 +95,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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// Requests
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Other_GETX, desc="A GetX from another processor";
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Other_GETS, desc="A GetS from another processor";
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Other_GETS_No_Mig, desc="A GetS from another processor";
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// Responses
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Ack, desc="Received an ack message";
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@ -122,6 +124,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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bool Dirty, desc="Is the data dirty (different than memory)?";
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DataBlock DataBlk, desc="data for the block";
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bool FromL2, default="false", desc="block just moved from L2";
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bool AtomicAccessed, default="false", desc="block just moved from L2";
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}
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// TBE fields
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@ -280,7 +283,15 @@ machine(L1Cache, "AMD Hammer-like protocol")
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if (in_msg.Type == CoherenceRequestType:GETX) {
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trigger(Event:Other_GETX, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:GETS) {
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trigger(Event:Other_GETS, in_msg.Address);
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if (isCacheTagPresent(in_msg.Address)) {
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if (getCacheEntry(in_msg.Address).AtomicAccessed && no_mig_atomic) {
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trigger(Event:Other_GETS_No_Mig, in_msg.Address);
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} else {
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trigger(Event:Other_GETS, in_msg.Address);
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}
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} else {
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trigger(Event:Other_GETS, in_msg.Address);
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}
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} else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
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trigger(Event:Writeback_Ack, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
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@ -538,12 +549,16 @@ machine(L1Cache, "AMD Hammer-like protocol")
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action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
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DEBUG_EXPR(getCacheEntry(address).DataBlk);
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peek(mandatoryQueue_in, CacheMsg) {
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sequencer.writeCallback(address,
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testAndClearLocalHit(address),
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getCacheEntry(address).DataBlk);
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sequencer.writeCallback(address,
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testAndClearLocalHit(address),
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getCacheEntry(address).DataBlk);
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getCacheEntry(address).Dirty := true;
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getCacheEntry(address).Dirty := true;
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if (in_msg.Type == CacheRequestType:ATOMIC) {
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getCacheEntry(address).AtomicAccessed := true;
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}
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}
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}
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action(sx_external_store_hit, "sx", desc="store required external msgs.") {
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@ -798,7 +813,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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zz_recycleMandatoryQueue;
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}
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transition({IT, ST, OT, MT, MMT}, {Other_GETX, Other_GETS}) {
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transition({IT, ST, OT, MT, MMT}, {Other_GETX, Other_GETS, Other_GETS_No_Mig}) {
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// stall
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}
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@ -948,7 +963,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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rr_deallocateL2CacheBlock;
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}
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transition(I, {Other_GETX, Other_GETS}) {
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transition(I, {Other_GETX, Other_GETS, Other_GETS_No_Mig}) {
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f_sendAck;
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l_popForwardQueue;
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}
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@ -975,7 +990,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(S, Other_GETS) {
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transition(S, {Other_GETS, Other_GETS_No_Mig}) {
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ff_sendAckShared;
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l_popForwardQueue;
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}
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@ -1005,7 +1020,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(O, Other_GETS) {
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transition(O, {Other_GETS, Other_GETS_No_Mig}) {
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ee_sendDataShared;
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l_popForwardQueue;
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}
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@ -1037,6 +1052,11 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(MM, Other_GETS_No_Mig, O) {
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ee_sendDataShared;
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l_popForwardQueue;
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}
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// Transitions from Dirty Exclusive
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transition(M, {Load, Ifetch}) {
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h_load_hit;
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@ -1059,14 +1079,14 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(M, Other_GETS, O) {
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transition(M, {Other_GETS, Other_GETS_No_Mig}, O) {
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ee_sendDataShared;
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l_popForwardQueue;
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}
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// Transitions from IM
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transition(IM, {Other_GETX, Other_GETS}) {
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transition(IM, {Other_GETX, Other_GETS, Other_GETS_No_Mig}) {
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f_sendAck;
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l_popForwardQueue;
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}
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@ -1093,7 +1113,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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}
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// Transitions from SM
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transition(SM, Other_GETS) {
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transition(SM, {Other_GETS, Other_GETS_No_Mig}) {
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ff_sendAckShared;
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l_popForwardQueue;
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}
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@ -1138,7 +1158,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition(OM, Other_GETS) {
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transition(OM, {Other_GETS, Other_GETS_No_Mig}) {
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ee_sendDataShared;
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l_popForwardQueue;
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}
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@ -1158,7 +1178,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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// Transitions from IS
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transition(IS, {Other_GETX, Other_GETS}) {
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transition(IS, {Other_GETX, Other_GETS, Other_GETS_No_Mig}) {
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f_sendAck;
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l_popForwardQueue;
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}
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@ -1274,7 +1294,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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l_popForwardQueue;
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}
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transition({OI, MI}, Other_GETS, OI) {
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transition({OI, MI}, {Other_GETS, Other_GETS_No_Mig}, OI) {
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q_sendDataFromTBEToCache;
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l_popForwardQueue;
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}
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@ -1292,7 +1312,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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}
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// Transitions from II
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transition(II, {Other_GETS, Other_GETX}, II) {
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transition(II, {Other_GETS, Other_GETS_No_Mig, Other_GETX}, II) {
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f_sendAck;
|
||||
l_popForwardQueue;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue