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ruby: Python config files now sets a unique id for each sequencer

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This commit is contained in:
Brad Beckmann 2010-03-21 21:22:20 -07:00
parent d8e1e5abd0
commit 91b0c5487b
5 changed files with 10 additions and 5 deletions
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3
configs/ruby/MESI_CMP_directory.py
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@ -76,7 +76,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
cpu_seq = RubySequencer(icache = l1i_cache,
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = phys_mem.port,
physmem = phys_mem)

3
configs/ruby/MI_example.py
View file

@ -71,7 +71,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
cpu_seq = RubySequencer(icache = cache,
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
physMemPort = phys_mem.port,
physmem = phys_mem)

3
configs/ruby/MOESI_CMP_directory.py
View file

@ -76,7 +76,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
cpu_seq = RubySequencer(icache = l1i_cache,
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = phys_mem.port,
physmem = phys_mem)

3
configs/ruby/MOESI_CMP_token.py
View file

@ -82,7 +82,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc)
cpu_seq = RubySequencer(icache = l1i_cache,
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = phys_mem.port,
physmem = phys_mem)

3
configs/ruby/MOESI_hammer.py
View file

@ -77,7 +77,8 @@ def create_system(options, phys_mem, piobus, dma_devices):
l2_cache = L2Cache(size = options.l2_size,
assoc = options.l2_assoc)
cpu_seq = RubySequencer(icache = l1i_cache,
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = phys_mem.port,
physmem = phys_mem)