Configuration: Move iocache outside of processors loop so it works for MP systems

--HG--
extra : convert_revision : 0ba563555a94eb22a6d4e402388e75e70d3556c2
This commit is contained in:
Ali Saidi 2007-10-08 15:19:58 -04:00
parent 8858b0b667
commit a630d77ec5

View file

@ -119,16 +119,19 @@ if options.l2cache:
test_sys.l2.mem_side = test_sys.membus.port
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
if options.caches:
test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
test_sys.iocache.cpu_side = test_sys.iobus.port
test_sys.iocache.mem_side = test_sys.membus.port
for i in xrange(np):
if options.caches:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
test_sys.iocache.cpu_side = test_sys.iobus.port
test_sys.iocache.mem_side = test_sys.membus.port
if options.l2cache:
test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
else: