The disk image to use was always being forced to a particular value. This
change changes what disk image is selected as the default based on the
architecture being built. In the future, a more sophisticated system might be
used that selected a path based on certain rules instead of relying on one off
file names.
Most of the messages in the config scripts that report a time value already
print "@ tick" followed by the current tick value, but a few were printing
"@ cycle". Since this is a distinction that's frequently confusing to new
users, this changes those message to the more accurate and consistent "@ tick".
The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system. Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks. The result was many cpus were idle for large periods of time.
These changes fix the latency mismatch.
The separate restoreCheckpoint() call is gone; just pass
the checkpoint dir as an optional arg to instantiate().
This change is a precursor to some more extensive
reworking of the startup code.
Enforce that the Python Root SimObject is instantiated only
once. The C++ Root object already panics if more than one is
created. This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists). It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone. Users who use
configs/common/Simulate.py should not notice.
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester). This
code works for memory tester, but have not tested fs mode.
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers. Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
-option to allow threads to run to a max_inst_any_thread which is more useful/quicker in a lot of
cases then always having to figure out what tick to run your simulation to.
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
set the latency parameter in terms of a latency
add caches to tsunami-simple configs
configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
set the latency parameter in terms of a latency
configs/common/FSConfig.py:
give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
add caches to tsunami-simple configs
--HG--
extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier
--HG--
extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
configs/common/FSConfig.py:
add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy
--HG--
extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
relevant code directly into the SimConsole object. Now,
you can easily turn off the listen port by just specifying
0 as the port.
--HG--
extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
add configuration for memory mapped disk
src/dev/sparc/SConscript:
add memory mapped disk to sconscript
--HG--
extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
configs/common/FSConfig.py:
seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
Use instruction count from cpu rather than cycles because that is what legion does
we can change it back after were done with legion
src/base/bitfield.hh:
add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
change asserts of packet success to if panics wrapped with NDEBUG defines
so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
convert some tabs to spaces
src/python/m5/objects/T1000.py:
add more fake devices for each l1 bank and each memory controller
--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it
configs/common/FSConfig.py:
We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
Let kernel be none
src/sim/system.cc:
Let the system kernel be none, but warn about it
--HG--
extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
into zower.eecs.umich.edu:/eecshome/m5/newmemmid
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
hand merge
--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.
However the O3CPU must always use caches, so a check for that must still exist.
Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.
--HG--
extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
configs/common/Simulation.py:
simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
make a new m5 param called MaxTick.
src/sim/host.hh:
fix the M5 def. of MaxTick
src/sim/main.cc:
Simplify the MaxTick/num_cycles parsing within main.cc
--HG--
extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
configs/common/Simulation.py:
enable going from checkpoint into arbitrary CPU with or without caches.
--HG--
extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
configs/common/Simulation.py:
Remove mem parameter.
configs/example/se.py:
Remove debug output that got included in my other push.
--HG--
extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0
Accidentally committed this last time
configs/common/FSConfig.py:
Accidentally committed this last time
--HG--
extra : convert_revision : 32d49c17c661b57a9aa9c3b057258f6e037ba745
configs/common/Options.py:
make the warmup period in a standard switch part of the option.
configs/common/Simulation.py:
add some comments and also make the warmup period an option.
--HG--
extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
configs/example/fs.py:
factor out common code.
configs/example/se.py:
factor out common code
--HG--
extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
Add in default FUPool.
src/python/m5/objects/O3CPU.py:
Use defaults better. Also set checker parameters, and fix up a config bug.
--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().
src/python/m5/multidict.py:
Make get() return None by default, to match semantics
of built-in dictionary objects.
--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
configs/common/FSConfig.py:
Clean up some code to make functions look less like classes. Also put makeList function (formerly listWrapper) into m5 itself.
configs/test/fs.py:
Update for changed code.
src/python/m5/__init__.py:
Put makeList into m5.
--HG--
extra : convert_revision : 731806a7486f9abf986f52926126df666b024b1d
SConstruct:
Make test CPUs option non-sticky.
configs/common/FSConfig.py:
Be sure to set the memory mode.
configs/test/fs.py:
Wrong string.
tests/SConscript:
Only test valid CPUs that have been compiled in.
tests/test1/ref/alpha/atomic/config.ini:
tests/test1/ref/alpha/atomic/config.out:
tests/test1/ref/alpha/atomic/m5stats.txt:
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/config.ini:
tests/test1/ref/alpha/detailed/config.out:
tests/test1/ref/alpha/detailed/m5stats.txt:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/config.ini:
tests/test1/ref/alpha/timing/config.out:
tests/test1/ref/alpha/timing/m5stats.txt:
tests/test1/ref/alpha/timing/stdout:
Update output.
--HG--
extra : convert_revision : 6eee2a5eae0291b5121b41bcd7021179cdd520a3
configs/test/fs.py:
Pull out a lot of common code and put it into configs/common/FSConfig.py.
--HG--
extra : convert_revision : 175b18d75f82ddecbcc9a6418fe40df314db55d5
