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factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.

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configs/common/Simulation.py:
    enable going from checkpoint into arbitrary CPU with or without caches.

--HG--
extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
This commit is contained in:
Lisa Hsu 2006-11-01 19:25:09 -05:00
parent 7665be4f70
commit 74ff45d353
3 changed files with 57 additions and 32 deletions
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58
configs/common/Simulation.py
View file

@ -32,7 +32,31 @@ from m5.objects import *
m5.AddToPath('../common')
from Caches import L1Cache
def run(options, root, testsys):
def setCPUClass(options):
atomic = False
if options.timing:
TmpClass = TimingSimpleCPU
elif options.detailed:
TmpClass = DerivO3CPU
else:
TmpClass = AtomicSimpleCPU
atomic = True
CPUClass = None
test_mem_mode = 'atomic'
if not atomic:
if options.checkpoint_restore:
CPUClass = TmpClass
TmpClass = AtomicSimpleCPU
else:
test_mem_mode = 'timing'
return (TmpClass, test_mem_mode, CPUClass)
def run(options, root, testsys, cpu_class):
if options.maxtick:
maxtick = options.maxtick
elif options.maxtime:
@ -49,6 +73,24 @@ def run(options, root, testsys):
np = options.num_cpus
max_checkpoints = options.max_checkpoints
switch_cpus = None
if cpu_class:
switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
for i in xrange(np)]
for i in xrange(np):
switch_cpus[i].system = testsys
if not m5.build_env['FULL_SYSTEM']:
switch_cpus[i].workload = testsys.cpu[i].workload
switch_cpus[i].clock = testsys.cpu[0].clock
if options.caches:
switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
switch_cpus[i].connectMemPorts(testsys.membus)
root.switch_cpus = switch_cpus
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
if options.standard_switch:
switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
@ -65,17 +107,16 @@ def run(options, root, testsys):
switch_cpus[i].clock = testsys.cpu[0].clock
switch_cpus_1[i].clock = testsys.cpu[0].clock
## add caches to the warmup timing CPU (which will be
## xferred to O3 when you switch again)
if options.caches:
switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
else: # O3 CPU must have a cache to work.
switch_cpus[i].connectMemPorts(testsys.membus)
else:
# O3 CPU must have a cache to work.
switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
switch_cpus_1[i].connectMemPorts(testsys.membus)
switch_cpus[i].connectMemPorts(testsys.membus)
root.switch_cpus = switch_cpus
root.switch_cpus_1 = switch_cpus_1
@ -110,7 +151,7 @@ def run(options, root, testsys):
m5.restoreCheckpoint(root,
"/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
if options.standard_switch:
if options.standard_switch or cpu_class:
exit_event = m5.simulate(10000)
## when you change to Timing (or Atomic), you halt the system given
@ -123,8 +164,9 @@ def run(options, root, testsys):
m5.switchCpus(switch_cpu_list)
m5.resume(testsys)
exit_event = m5.simulate(options.warmup)
m5.switchCpus(switch_cpu_list1)
if options.standard_switch:
exit_event = m5.simulate(options.warmup)
m5.switchCpus(switch_cpu_list1)
num_checkpoints = 0
exit_cause = ''

16
configs/example/fs.py
View file

@ -72,16 +72,8 @@ if args:
DriveCPUClass = AtomicSimpleCPU
drive_mem_mode = 'atomic'
# system under test can be any of these CPUs
if options.detailed:
TestCPUClass = DerivO3CPU
test_mem_mode = 'timing'
elif options.timing:
TestCPUClass = TimingSimpleCPU
test_mem_mode = 'timing'
else:
TestCPUClass = AtomicSimpleCPU
test_mem_mode = 'atomic'
# system under test can be any CPU
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
TestCPUClass.clock = '2GHz'
DriveCPUClass.clock = '2GHz'
@ -103,7 +95,7 @@ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
np = options.num_cpus
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
for i in xrange(np):
if options.caches and not options.standard_switch:
if options.caches and not options.standard_switch and not FutureClass:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
test_sys.cpu[i].connectMemPorts(test_sys.membus)
@ -119,4 +111,4 @@ else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
Simulation.run(options, root, test_sys)
Simulation.run(options, root, test_sys, FutureClass)

15
configs/example/se.py
View file

@ -88,16 +88,7 @@ if options.detailed:
process += [smt_process, ]
smt_idx += 1
if options.timing:
CPUClass = TimingSimpleCPU
test_mem_mode = 'timing'
elif options.detailed:
CPUClass = DerivO3CPU
test_mem_mode = 'timing'
else:
CPUClass = AtomicSimpleCPU
test_mem_mode = 'atomic'
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.clock = '2GHz'
@ -110,7 +101,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
system.physmem.port = system.membus.port
for i in xrange(np):
if options.caches and not options.standard_switch:
if options.caches and not options.standard_switch and not FutureClass:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
system.cpu[i].connectMemPorts(system.membus)
@ -118,4 +109,4 @@ for i in xrange(np):
root = Root(system = system)
Simulation.run(options, root, system)
Simulation.run(options, root, system, FutureClass)